SM5865AM D/A Converter NIPPON PRECISION CIRCUITS INC. PINOUT ina ry OVERVIEW (Top view) DVSS BCKI ■ pre ■ Single-channel D/A converter built-in High performance (120 dB signal-to-noise ratio) (0.001% total harmonic distortion and noise) (110 dB dynamic range) Σ∆ D/A converter • 3rd-order noise shaper • 23-level quantizer Input data format • 20 or 24-bit word length • MSB first, right-justified format • 8 or 4 times oversampling at fs = 32/44.1/48/ 88.2/96/192 kHz System clock frequency • 128/192/256/384/512/768 fs Single 5 V operating supply voltage 24-pin SSOP package Molybdenum-gate CMOS process ■ ■ ■ ■ RAN TSTN TO DVDD CKI AVDDA AVDDB RBP IOUTB IOUTBN RBN CKDVN 12 13 AVSSB PACKAGE DIMENSIONS (Unit: mm) 24-pin SSOP 5.40 0.20 7.80 0.30 ■ IOUTAN RSTN lim ■ IOUTA IWSL CVSS AVSSA RAP WCKI A single SM5865AM IC can be used in combination with an 8-times oversampling digital filter for conversion for a single audio channel. FEATURES 24 1 DI S M 5 8 6 5 AM The SM5865AM is a 24-bit input D/A converter for high-quality digital audio equipment. It comprises newly developed DEM (dynamic element matching) circuits, 3rd-order Σ∆ noise shaper and 23-level quantizer to control wide-band residual quantization noise in the signal band, making it ideal for application with high-frequency sampling formats. Also, the order of the required final-stage analog lowpass filter can be reduced, compared to filters for available devices, enhancing output tone quality. The output stage employs complementary outputs for high-accuracy analog signals, with appropriate lowpass filtering of the output signal. + 0.1 0.15 − 0.05 10.05 0.20 10.20 0.30 SM5865AM 24-pin SSOP 0.8 0.36 0.10 0.10 0.12 M +0.20 1.90−0.10 Package 0.10 0.10 Device 1.80 ORDERING INFORMATION 0.50 0.20 0 10 NIPPON PRECISION CIRCUITS—1 SM5865AM BLOCK DIAGRAM 8 TSTN RSTN 7 IWSL 6 WCKI 5 BCKI 4 DI 3 2 ina ry TO Input interface 9 DVDD CKI CKDVN CVSS 10 Timing control Divider Interpolation 11 1 12 AVSSB 13 Noise shaper lim Noise shaper 23 Level DEM DAC 23 Level DEM DAC 14 16 15 DVSS 17 19 23 Level DEM DAC 23 Level DEM DAC 20 22 21 AVSSA 23 RAP IOUTA IOUTAN RAN AVDDA AVDDB RBP IOUTB IOUTBN RBN pre 18 24 NIPPON PRECISION CIRCUITS—2 SM5865AM PIN DESCRIPTION Name I/O 1 DVSS – Digital ground 2 DI I Data input 3 BCKI I Bit clock input 4 WCKI I Word clock input 5 IWSL Ip Input data word length select. 24-bit when HIGH, and 20-bit when LOW. 6 RSTN Ip System reset. Reset when LOW. 7 TSTN Ip Test pin. Tie HIGH or leave open for normal operation. 8 TO O Test output 9 DVDD – Digital supply 10 CKI I System clock input 11 CKDVN Ip System clock frequency divider ratio select. 1 when HIGH (no division), and 2 when LOW. 12 CVSS – System clock ground 13 AVSSB – Analog ground B 14 RBN I Built-in resistor connection B 15 IOUTBN O Inverse-phase analog output B 16 IOUTB O In-phase analog output B 17 RBP I Built-in resistor connection B 18 AVDDB – Analog supply B 19 AVDDA – Analog supply A 20 RAN I Built-in resistor connection A 21 IOUTAN O Inverse-phase analog output A 22 IOUTA O In-phase analog output A 23 RAP I Built-in resistor connection A 24 AVSSA – Analog ground A lim pre IP : Pull-up input Description ina ry Number NIPPON PRECISION CIRCUITS—3 SM5865AM SPECIFICATIONS Absolute Maximum Ratings DVSS = AVSSA = AVSSB = CVSS = 0 V, DVDD = AVDDA = AVDDB Parameter Input voltage range1 Storage temperature range Power dissipation Soldering temperature Soldering time 1. Pins DI, BCKI, WCKI, CKDVN, IWSL, RSTN, TSTN. Also applicable during supply switching. Rating Unit DVDD, AVDDA, AVDDB −0.3 to 7.0 V ina ry Supply voltage range Symbol VIN DVSS − 0.3 to DVDD + 0.3 V Tstg −55 to 125 °C PD 250 mW Tsld 255 °C tsld 10 s Symbol Rating Unit DVDD, AVDDA, AVDDB 4.5 to 5.5 V DVDD − AVDDA, DVDD − AVDDB, AVDDA − AVDDB, DVSS − AVSSA, DVSS − AVSSB, AVSSA − AVSSB, DVSS − CVSS, AVSSA − CVSS, AVSSB − CVSS ±0.1 V Topr −40 to 85 °C Recommended Operating Conditions DVSS = AVSSA = AVSSB = CVSS = 0 V, DVDD = AVDDA = AVDDB Parameter Supply voltage variation lim Supply voltage range pre Operating temperature range NIPPON PRECISION CIRCUITS—4 SM5865AM DC Electrical Characteristics Recommended operating conditions, unless otherwise specified Rating Parameter Symbol Condition Unit min IDDD AVDDA, AVDDB supply current1 IDDA CKI HIGH-level input voltage VIHC CKI LOW-level input voltage VILC CKI input voltage VINAC HIGH-level input voltage2 VIH LOW-level input voltage2 VIL HIGH-level output voltage3 VOH LOW-level output voltage3 VOL CKI HIGH-level input current IIHC CKI LOW-level input current IILC LOW-level input current4 IIL2 HIGH-level input leakage current5 IIH1 LOW-level input leakage current5 IIL1 HIGH-level input leakage current6 IIH2 mA TBD mA 0.7VDD – – V – – 0.3VDD V 1.0 – – V 2.4 – – V – – 0.5 V DVDD − 0.4 – – V IOL = 1 mA – – 0.4 V VIN = DVDD 30 60 120 µA VIN = 0 V 30 60 120 µA VIN = 0 V – 9 18 µA VIN = DVDD – – 1.0 µA VIN = 0 V – – 1.0 µA VIN = DVDD – – 1.0 µA AC coupling IOH = −1 mA lim DVDD = AVDDA = AVDDB = 5 V, system clock input frequency fCKI = 16.9344 MHz, no output load, NPC-standard input data pattern. Pins DI, BCKI, WCKI, CKDVN, IWSL, RSTN, TSTN. Pin TO. Pins CKDVN, IWSL, RSTN, TSTN. Pins DI, BCKI, WCKI. Pins CKDVN, IWSL, RSTN, TSTN. pre 1. 2. 3. 4. 5. 6. max ina ry DVDD supply current1 typ NIPPON PRECISION CIRCUITS—5 SM5865AM AC Electrical Characteristics System clock (CKI) Rating Symbol HIGH-level clock pulsewidth LOW-level clock pulsewidth Clock pulse cycle CKI Unit min typ max tCWH TBD – TBD ns tCWL TBD – TBD ns tCKI TBD – TBD ns ina ry Parameter t CWL VIH1 0.5VDD VIL1 t CWH t CKI Reset Input (RSTN) Rating Parameter Symbol Condition At power ON tRSTN After power ON lim RSTN LOW-level pulsewidth Unit min typ max 1 – – µs 100 – – ns Serial input (BCKI, DI, WCKI) Parameter Rating Symbol Unit min typ max BCKI HIGH-level pulsewidth tBCWH 10 – – ns BCKI LOW-level pulsewidth tBCWL 10 – – ns BCKI pulse cycle tBCY 20 – – ns tDS 5 – – ns tDH 5 – – ns WCKI edge to first BCKI rising edge tBW 10 – – ns Last BCKI rising edge to WCKI edge tWB 10 – – ns DI setup time pre DI hold time BCKI t BCWH t BCY 1.5V t BCWL DI t DS 1.5V t DH WCKI 1.5V t WB t WL NIPPON PRECISION CIRCUITS—6 SM5865AM AC Analog Characteristics DVDD = AVDDA = AVDDB = 5 V, DVSS = AVSSA = AVSSB = CVSS = 0 V, Ta = 25 °C, 44.1 kHz input sampling frequency, fCKI = 16.9344 MHz (384fs), 48fs operation Rating Parameter Symbol Condition Unit THD + N Total harmonic distortion LSI output level Vout1 Dynamic range D.R Signal-to-noise ratio S/N typ max ina ry min 1 kHz, 0 dB % 1 kHz, 0 dB Vrms TBD 1 kHz, −60 dB dB 1 kHz, 0/−∞ dB dB Estimated values for audio signal data with up to 20 kHz bandwidth, DVDD = AVDDA = AVDDB = 5 V, DVSS = AVSSA = AVSSB = CVSS = 0 V, Ta = 25 °C, 48 kHz input sampling frequency, fCKI = 24.576 MHz (512fs), 64fs operation 96 kHz input sampling frequency, fCKI = 24.576 MHz (256fs), 32fs operation Rating Parameter Symbol Condition Unit min THD + N Total harmonic distortion Vout1 Dynamic range D.R Signal-to-noise ratio S/N max 1 kHz, 0 dB % 1 kHz, 0 dB Vrms TBD 1 kHz, −60 dB dB 1 kHz, 0/−∞ dB dB lim LSI output level typ Measurement circuit block diagram CKO(384fs) Signal Generator BCK WCKI Evaluation Board L/R Channel Selector Distortion Analyzer 10kΩ Input Impedance NF Corporation 3346A RMS Measurement Corresponds to Shibasoku AD725C DATA pre fs= 44.1kHz Measurement conditions DVDD = AVDDA = AVDDB = 5 V, DVSS = AVSSA = AVSSB = CVSS = 0 V, Ta = 25 °C Parameter Symbol Total harmonic distortion THD + N 3346A left/right-channel selector switch THRU Output level Vout Dynamic range D.R D-RANGE Signal-to-noise ratio S/N THRU AD725C distortion analyzer with built-in filter 20 kHz lowpass filter ON 400 Hz highpass filter OFF 20 kHz lowpass filter ON 400 Hz highpass filter OFF JIS A filter ON NIPPON PRECISION CIRCUITS—7 SM5865AM ina ry Measurement circuit pre lim TBD NIPPON PRECISION CIRCUITS—8 SM5865AM FUNCTIONAL DESCRIPTION Quantization Noise Reduction ina ry The SM5865AM employs a 3rd-order 23-level quantizer noise shaper to effectively reduce quantization noise in the audio band. The quantization noise component at 16fs to 96fs operation is shown in figure 1. 0 10 0 dB sine wave equivalent white noise level 20 16fs 30 24fs 40 16-bit, fs quantization noise level 50 32fs 48fs 64fs 60 70 80 Quantization noise 90 (dB) 100 96fs 110 120 130 20-bit, fs quantization noise level 140 150 24-bit, fs quantization noise level lim 160 170 180 0 0.5 1 1.5 2 2.5 3 3.5 4 Frequency (fs) Figure 1. Quantization noise level Internal Oversampling Operation pre The SM5865AM accepts data output from an 8-times or 4-times oversampling digital filter, and oversampled internally again up to the noise shaper operating rate. The internal oversampling factor is determined automatically from the system clock input frequency and the input sampling frequency. This internal oversampling factor (n) must be an integer satisfying the conditions shown in table 1. Table 1. Operating conditions Parameter fWCKI and fCKI compulsory conditions1 Noise shaper operating frequency CKDVN = HIGH CKDVN = LOW f CKI = f WCKI × 8 × n f CKI = f WCKI × 16 × n where n = 1, 2, 3, ... where n = 1, 2, 3, ... f CKI f ns = f WCKI × n = ---------8 f CKI f ns = f WCKI × n = ---------16 1. fWCKI = word clock frequency, fCKI = input system clock frequency, n = internal oversampling factor NIPPON PRECISION CIRCUITS—9 SM5865AM Word clock input SM5865 ina ry WCKI System clock input CKI System clock divider select CKDVN Figure 2. Clock-related inputs Table 2 shows some possible combinations for the circuit configuration shown in figure 3. fs fWCKI Interpolating filter SM5865 (8-times/4-times) fCKI CKDVN lim Figure 3. Circuit configuration Table 2. System clock frequencies (CKDVN = HIGH) fs System clock frequency1 fCKI Noise shaper operating rate Internal factor (8fs input) Internal factor (4fs input) 32 kHz 4.096 MHz (128fs) 16fs 2 4 6.144 MHz (192fs) 24fs 3 6 8.192 MHz (256fs) 32fs 4 8 12.288 MHz (384fs) 48fs 6 12 16.384 MHz (512fs) 64fs 8 16 24.576 MHz (768fs) 96fs 12 24 44.1 kHz 5.6448 MHz (128fs) 16fs 2 4 44.1 kHz 8.4672 MHz (192fs) 24fs 3 6 44.1 kHz 11.2896 MHz (256fs) 32fs 4 8 44.1 kHz 16.9344 MHz (384fs) 48fs 6 12 44.1 kHz 22.5792 MHz (512fs) 64fs 8 16 44.1 kHz 33.8688 MHz (768fs) 96fs 12 24 48 kHz 6.144 MHz (128fs) 16fs 2 4 48 kHz 9.216 MHz (192fs) 24fs 3 6 48 kHz 12.288 MHz (256fs) 32fs 4 8 48 kHz 18.432 MHz (384fs) 48fs 6 12 48 kHz 24.576 MHz (512fs) 64fs 8 16 48 kHz 36.864 MHz (768fs) 96fs 12 24 32 kHz 32 kHz 32 kHz 32 kHz pre 32 kHz NIPPON PRECISION CIRCUITS—10 SM5865AM Table 2. System clock frequencies (CKDVN = HIGH) System clock frequency1 fCKI Noise shaper operating rate Internal factor (8fs input) Internal factor (4fs input) 88.2 kHz 11.2896 MHz (128fs) 16fs 2 4 88.2 kHz 16.9344 MHz (192fs) 24fs 3 6 88.2 kHz 22.5792 MHz (256fs) 32fs 4 8 88.2 kHz 33.8688 MHz (384fs) 48fs 6 12 96 kHz 12.288 MHz (128fs) 16fs 2 4 96 kHz 18.432 MHz (192fs) 24fs 3 6 96 kHz 24.576 MHz (256fs) 32fs 4 8 96 kHz 36.864 MHz (384fs) 48fs 6 12 192 kHz 24.576 MHz (128fs) 16fs 2 4 192 kHz 36.864 MHz (192fs) 24fs 3 6 ina ry fs 1. When CKDVN = LOW, the system clock frequency fCKI is halved, so the values shown are half the input frequency required for the same sampling rate and internal factors. System Clock Divider (CKDVN) Input data format The audio data is input in MSB-first, 2s-complement, 24-bit/20-bit serial format. The input word bit length is selected by IWSL, 24-bit when HIGH or open circuit, and 20-bit when LOW. lim The SM5865AM has a built-in divide-by-2 system clock frequency divider. The divider enables the internal system clock to operate at half the input frequency, for example when the external master clock input frequency is high. Audio Data Input (DI, BCKI, WCKI, IWSL) System Reset (RSTN) Jitter-free function The device should be reset in the following cases. ■ ■ At power ON When the system clock CKI stops, or other abnormalities occur. pre The device is reset by applying a LOW-level pulse on RSTN. Serial input data bits on DI are read into an SIPO register (serial-to-parallel converter register) on the rising edge of the bit clock BCKI where the serial data is converted into parallel data. The internal parallel data control timing is derived from the system clock, and is not affected by any jitter on the input data clocks (WCKI and BCKI). After a reset operation is released when RSTN goes HIGH, the internal timing and the WCKI input timing are phase compared on the first and subsequent WCKI falling edges and the comparison result is used to perform timing adjustment to maintain the word boundary relationship between the internal timing and the WCKI clock. NIPPON PRECISION CIRCUITS—11 SM5865AM TIMING DIAGRAMS 384fs System Clock Input Timing WCKI CKI BCKI (1)20bit * MSB DI ina ry 1 / 8fs LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 BCKI (2)20bit LSB MSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 lim DI BCKI (3)24bit LSB MSB DI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 pre * Data can be input at any period within the word clock cycle. NIPPON PRECISION CIRCUITS—12 SM5865AM 256fs System Clock Input Timing WCKI CKI BCKI (1)20bit * MSB DI ina ry 1 / 8fs LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 BCKI (2)20bit LSB MSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 BCKI (3)24bit * lim DI LSB MSB DI BCKI (4)24bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 LSB MSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 pre DI * Data can be input at any period within the word clock cycle. NIPPON PRECISION CIRCUITS—13 SM5865AM TYPICAL APPLICATIONS XTI CKI DI WCKI BCKI SM5865 CKI DI WCKI BCKI SM5865 pre lim SM5847 DOL DOR WCKO BCKO ina ry Input Interface Circuit NIPPON PRECISION CIRCUITS—14 SM5865AM Analog Output Circuit 1 23 Level DEM DAC 23 Level DEM DAC ina ry RAP IOUTA IOUTAN RAN SM5865 RBP 23 Level DEM DAC 23 Level DEM DAC IOUTB IOUTBN lim RBN Analog Output Circuit 2 RAP 23 Level DEM DAC IOUTAN pre 23 Level DEM DAC IOUTA RAN SM5865 RBP 23 Level DEM DAC 23 Level DEM DAC IOUTB IOUTBN RBN NIPPON PRECISION CIRCUITS—15 SM5865AM Analog Output Circuit 3 23 Level DEM DAC 23 Level DEM DAC ina ry RAP IOUTA IOUTAN RAN SM5865 RBP 23 Level DEM DAC 23 Level DEM DAC IOUTB IOUTBN lim RBN Analog Output Circuit 4 RAP 23 Level DEM DAC pre 23 Level DEM DAC IOUTA IOUTAN RAN SM5865 RBP 23 Level DEM DAC 23 Level DEM DAC IOUTB IOUTBN RBN Note that the analog output characteristics are not guaranteed for non-standard output circuit configurations. NIPPON PRECISION CIRCUITS—16 pre lim ina ry SM5865AM NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9804BE 1999.2 NIPPON PRECISION CIRCUITS—17