SM5877AM 3rd-order Σ∆, 2-channel D/A Converter OVERVIEW PINOUT The SM5877AM is a 3rd-order Σ∆, 2-channel D/A converter LSI for digital audio reproduction equipment. It also incorporates an 8-times oversampling digital filter and analog, post-converter lowpass filters. The SM5877AM has digital deemphasis filter, attenuator, and soft mute circuits built-in. Double-speed operation and low-voltage operation are also supported. FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ATCK 23 MODE CKO 3 22 RSTN DVSS 4 21 DS BCKI 5 20 XVSS DI 6 19 XTO DVDD 7 18 XTI LRCI 8 17 XVDD TSTN 9 16 MUTEO TO1 10 15 AVDDR AVDDL 11 14 RO LO 12 13 AVSS PACKAGE DIMENSIONS Unit: mm 24-pin SSOP 5.40 0.20 7.80 0.30 ■ ■ 24 2 + 0.1 0.15 − 0.05 10.05 0.20 10.20 0.30 1.80 0.10 ■ 2.7 to 5.5 V operating supply voltage range 4.5 to 5.5 V operating supply voltage range for double-speed mode 44.1 kHz sampling frequency Normal (384fs) and double-speed (192fs), 16.9344 MHz system clock 16.9344 MHz crystal oscillator circuits built-in 16-bit, MSB first, rear-packed serial data input format (≤ 64fs bit clock) 8-times oversampling digital filter • 32 dB stopband attenuation • ±0.05 dB passband ripple Deemphasis filter operation • 36 dB stopband attenuation • −0.09 to +0.23 dB deviation from ideal deemphasis filter characteristics Attenuator • 6-bit attenuator (64 steps) • Soft mute function when MODE is HIGH (approx. 1024/fs total muting time) Built-in infinity-zero detector Σ∆ 2-channel D/A converter • 3rd-order noise shaper • 32fs oversampling (16fs for double-speed mode) 3rd-order analog, post-converter lowpass filters built-in (165 kHz cut-off frequency) 24-pin SSOP Molybdenum-gate CMOS process 1 SM5877AM The SM5877AM operates from a 2.7 to 5.5 V supply, and is available in 24-pin SSOPs. ■ MUTE DEEM 0.7 0.8 0.36 0.10 0.10 0.10 2.10MAX NIPPON PRECISION CIRCUITS INC. 0.50 0.20 0 10 Package Marking S M 5 8 7 7 A M NIPPON PRECISION CIRCUITS—1 SM5877AM BLOCK DIAGRAM LRCI BCKI DI Input interface MODE L ATCK Attenuation counter MUTE R Filter & attenuation operation block L RSTN MUTEO DEEM CKO R Timing control DS XVSS XTO DVSS L PWM data generation block DVDD XTI Noise shaper operation block R TSTN XVDD TO1 AVDDL AVDDR + − LO − AVSS + RO PIN DESCRIPTION Number Name I/O Description 1 MUTE Ip When MODE is HIGH: Soft mute ON/OFF control. Mute is active when HIGH. When MODE is LOW: Attenuator level direction control. The attenuator direction is down when HIGH. 2 DEEM Ip Deemphasis control. Deemphasis is ON when HIGH, and OFF when LOW. 3 CKO O 16.9344 MHz clock output 4 DVSS 5 BCKI Ip Bit clock input pin 6 DI Ip Serial data input pin 7 DVDD 8 LRCI Ip Input sample data rate (fs) clock input pin. Left-channel input when HIGH, and rightchannel input when LOW. 9 TSTN Ip Test pin. Test mode when LOW. Digital ground pin Digital supply pin NIPPON PRECISION CIRCUITS—2 SM5877AM Number Name I/O Description 10 TO1 O 11 AVDDL 12 LO 13 AVSS 14 RO 15 AVDDR 16 MUTEO 17 XVDD 18 XTI I Crystal oscillator or 16.9344 MHz external clock input pin 19 XTO O Crystal oscillator output pin 20 XVSS 21 DS Ip Double/Normal-speed mode select. Double-speed mode when HIGH. 22 RSTN Ip Reset pin. Reset when LOW. 23 MODE Ip Soft mute/attenuator mode select. Soft mute mode when HIGH. 24 ATCK Ip Attenuator level setting clock. Disabled when MODE is HIGH. Test output 1. Normally LOW. Left-channel analog supply pin O Left-channel analog output Analog ground pin O Right-channel analog output Right-channel analog supply pin O Infinity-zero detection output Crystal oscillator supply pin Crystal oscillator ground pin SPECIFICATIONS Absolute Maximum Ratings DVSS = AVSS = XVSS = 0 V, AVDD = AVDDL = AVDDR Parameter Symbol Rating Unit Supply voltage range DVDD, AVDD, XVDD −0.3 to 7.0 V Input voltage range1 VIN1 DVSS − 0.3 to DVDD + 0.3 V XTI input voltage range VIN XVSS − 0.3 to XVDD + 0.3 V Storage temperature range Tstg −40 to 125 °C Power dissipation PD 250 mW Soldering temperature Tsld 255 °C Soldering time tsld 10 s Symbol Rating Unit DVDD, AVDD, XVDD 4.5 to 5.5 V DVDD − XVDD, DVDD − AVDD, XVDD − AVDD, DVSS − XVSS, DVSS − AVSS, XVSS − AVSS ±0.1 V Topr −40 to 85 °C 1. Pins MUTE, DEEM, BCKI, DI, LRCI, TSTN, DS, RSTN, MODE and ATCK. Also applicable during supply switching. Recommended Operating Conditions Normal-voltage: DVSS = AVSS = XVSS = 0 V, AVDD = AVDDL = AVDDR Parameter Supply voltage range Supply voltage variation Operating temperature range NIPPON PRECISION CIRCUITS—3 SM5877AM Low-voltage: DVSS = AVSS = XVSS = 0 V, AVDD = AVDDL = AVDDR Parameter Supply voltage range Supply voltage variation Symbol Rating Unit DVDD, AVDD, XVDD 2.7 to 4.5 V DVDD − XVDD, DVDD − AVDD, XVDD − AVDD, DVSS − XVSS, DVSS − AVSS, XVSS − AVSS ±0.1 V Topr −20 to 70 °C Operating temperature range DC Electrical Characteristics Normal-voltage: DVSS = AVSS = XVSS = 0 V, DVDD = AVDD = XVDD = 4.5 to 5.5 V, AVDD = AVDDL = AVDDR, Ta = −40 to 85 °C Rating Parameter Symbol Condition Unit min typ max DVDD digital supply current1 IDDD – 15 25 mA XVDD system clock supply current1 IDDX – 2 5 mA AVDD analog supply current1 IDDA2 – 4 8 mA XTI HIGH-level input voltage VIH1 Clock input 0.7XVDD – – V XTI LOW-level input voltage VIL1 Clock input – – 0.3XVDD V VINAC 0.3XVDD – – Vp-p HIGH-level input voltage3 VIH2 2.4 – – V LOW-level input voltage3 VIL2 – – 0.5 V HIGH-level output voltage4 VOHA IOH = −1 mA AVDD − 0.4 – – V LOW-level output voltage4 VOLA IOL = 1 mA – – 0.4 V CKO HIGH-level output voltage VOHC IOH = −1 mA DVDD − 0.4 – – V CKO LOW-level output voltage VOLC IOL = 1 mA – – 0.4 V XTI HIGH-level input current IIH1 VIN = XVDD – 12 25 µA XTI LOW-level input current IIL1 VIN = 0 V – 12 25 µA IIL2 VIN = 0 V – 12 25 µA ILH VIN = DVDD – – 1.0 µA XTI AC-coupled input voltage LOW-level input Input leakage current4 current4 1. DVDD = AVDD = XVDD = 5 V, DS = 5 V (double speed), XTI clock input frequency fXTI = 16.9344 MHz, no output load. 2. IDDA is the total current. 3. Pins MUTE, DEEM, BCKI, DI, LRCI, TSTN, DS, RSTN, MODE and ATCK. 4. Pins TO1 and MUTEO. NIPPON PRECISION CIRCUITS—4 SM5877AM Low-voltage: DVSS = AVSS = XVSS = 0 V, DVDD = AVDD = XVDD = 2.7 to 4.5 V, AVDD = AVDDL = AVDDR, Ta = −20 to 70 °C Rating Parameter Symbol Condition Unit min typ max DVDD digital supply current1 IDDD – 6 9 mA XVDD system clock supply current1 IDDX – 1 3 mA AVDD analog supply current1 IDDA2 – 1 2 mA XTI HIGH-level input voltage VIH1 Clock input 0.7XVDD – – V XTI LOW-level input voltage VIL1 Clock input – – 0.3XVDD V XTI AC-coupled input voltage VINAC 0.3XVDD – – Vp-p voltage3 VIH2 2.4 – – V voltage3 VIL2 – – 0.5 V AVDD − 0.4 – – V – – 0.4 V DVDD − 0.4 – – V HIGH-level input LOW-level input HIGH-level output voltage4 VOHA IOH = −0.5 mA LOW-level output voltage4 VOLA IOL = 0.5 mA CKO HIGH-level output voltage VOHC IOH = −0.5 mA CKO LOW-level output voltage VOLC IOL = 0.5 mA – – 0.4 V XTI HIGH-level input current IIH1 VIN = XVDD – 4 15 µA XTI LOW-level input current IIL1 VIN = 0 V – 4 15 µA LOW-level input current4 IIL2 VIN = 0 V – 4 15 µA Input leakage current4 ILH VIN = DVDD – – 1.0 µA 1. DVDD = AVDD = XVDD = 3 V, DS = 0 V (normal speed), XTI clock input frequency fXTI = 16.9344 MHz, no output load. 2. IDDA is the total current. 3. Pins MUTE, DEEM, BCKI, DI, LRCI, TSTN, DS, RSTN, MODE and ATCK. 4. Pins TO1 and MUTEO. AC Electrical Characteristics Normal-voltage: DVSS = AVSS = XVSS = 0 V, DVDD = AVDD = XVDD = 4.5 to 5.5 V, AVDD = AVDDL = AVDDR, Ta = −40 to 85 °C Low-voltage: DVSS = AVSS = XVSS = 0 V, DVDD = AVDD = XVDD = 2.7 to 4.5 V, AVDD = AVDDL = AVDDR, Ta = −20 to 70 °C System clock (XTI) Crystal Oscillator Rating Parameter Oscillator frequency Symbol fOSC Unit min typ max 4.0 16.9344 17.8 MHz NIPPON PRECISION CIRCUITS—5 SM5877AM External clock input Rating Parameter Symbol Unit min typ max HIGH-level clock pulsewidth tCWH 26.0 29.5 125 ns LOW-level clock pulsewidth tCWL 26.0 29.5 125 ns tXI 56.0 59.0 250 ns Clock pulse cycle XTI input clock VIH1 0.5V DD VIL1 t CWH t CWL t XI Serial input (BCKI, DI, LRCI) Rating Parameter Symbol Unit min typ max BCKI HIGH-level pulsewidth tBCWH 50 – – ns BCKI LOW-level pulsewidth tBCWL 50 – – ns BCKI pulse cycle tBCY 6tXI – – ns DI setup time tDS 50 – – ns DI hold time tDH 50 – – ns Last BCKI rising edge to LRCI edge tBL 50 – – ns LRCI edge to first BCKI rising edge tLB 50 – – ns Serial input timing t BCY t BCWH t BCWL 1.5 V BCKI t DS t DH 1.5 V DI t BL LRCI t LB 1.5 V NIPPON PRECISION CIRCUITS—6 SM5877AM Control input (MUTE, MODE, ATCK, DEEM, DS) Rating Parameter Symbol Unit min typ max ATCK LOW-level pulsewidth tATWL 0.5/fs – – µs ATCK HIGH-level pulsewidth tATWH 0.5/fs – – µs MUTE setup time tMUS 100 – – ns MUTE hold time tMUH 100 – – ns MODE setup time tMOS 100 – – ns MODE hold time tMOH 100 – – ns Rise time tr – – 50 ns Fall time tf – – 50 ns Control input timing MUTE MODE 1.5 V t MUS t MUH t MOS t MOH 1.5 V ATCK t ATWL t ATWH tf DEEM DS MUTE MODE ATCK tr 2.4 V 2.4 V 1.5 V 0.5 V 0.5 V Reset Input (RSTN) Rating Parameter RSTN LOW-level pulsewidth after supply rising edge Symbol tRSTN Unit min typ max 50 – – ns NIPPON PRECISION CIRCUITS—7 SM5877AM Theoretical Filter Characteristics Deemphasis OFF overall characteristics Frequency band Attenuation (dB) Parameter Passband ripple Stopband attenuation Built-in analog LPF compensation f @ fs = 44.1 kHz min typ max 0 to 0.4535fs 0 to 20.0 kHz −0.05 – +0.05 0.5465fs to 7.4535fs 24.1 to 328.7 kHz 32 – – 0.4535fs 20.0 kHz – −0.34 – Overall frequency characteristic (deemphasis OFF) 0 10 Gain (dB) 20 30 40 50 60 0.0 1.0 2.0 3.0 4.0 Frequency (fs) 5.0 6.0 7.0 8.0 Passband characteristic (deemphasis OFF) 0.0 Gain (dB) 0.2 0.4 0.6 0.8 0.000 0.125 0.250 0.375 0.4535 0.500 Frequency (fs) NIPPON PRECISION CIRCUITS—8 SM5877AM Deemphasis ON overall characteristics Frequency band Attenuation (dB) Parameter f @ fs = 44.1 kHz min typ max 0 to 0.4535fs 0 to 20.0 kHz −0.09 – +0.23 0.5465fs to 7.4535fs 24.1 to 328.7 kHz 36 – – 0.4535fs 20.0 kHz – −0.34 – Deviation from ideal deemphasis filter characteristics Stopband attenuation Built-in analog LPF compensation Overall frequency characteristic (deemphasis ON) 0 10 Gain (dB) 20 30 40 50 60 0.0 1.0 2.0 3.0 4.0 Frequency (fs) 5.0 6.0 7.0 8.0 Passband characteristic (deemphasis ON) 0 2 Gain (dB) 4 6 8 10 12 0.000 0.125 0.250 Frequency (fs) 0.375 0.4535 0.500 NIPPON PRECISION CIRCUITS—9 SM5877AM AC Analog Characteristics Normal-voltage: DVSS = AVSS = XVSS = 0 V, DVDD = AVDD = XVDD = 5 V, AVDD = AVDDL = AVDDR, DS = 0 V, DEEM = 0 V, crystal oscillator frequency fOSC = 16.9344 MHz, Ta = 25 °C Rating Parameter Symbol Condition Unit min typ max THD + N 1 kHz, 0 dB – 0.004 0.010 % LSI output level Vout1 1 kHz, 0 dB 1.1 1.2 1.3 Vrms Evaluation board output level Vout2 1 kHz, 0 dB – 1.2 – Vrms Dynamic range D.R 1 kHz, −60 dB 91 97 – dB S/N 1 kHz, 0/−∞ dB 90 96 – dB Ch. Sep 1 kHz, −∞/0 dB 87 93 – dB Total harmonic distortion Signal-to-noise ratio1 Channel separation 1. Signal-to-noise is measured following a device reset, with DATA = 0 (DI = LOW). Under these conditions, the signal-to-noise ratio includes noise-shaper noise. Low-voltage: DVSS = AVSS = XVSS = 0 V, DVDD = AVDD = XVDD = 3 V, AVDD = AVDDL = AVDDR, DS = 0 V, DEEM = 0 V, crystal oscillator frequency fOSC = 16.9344 MHz, Ta = 25 °C Rating Parameter Symbol Condition Unit min typ max THD + N 1 kHz, 0 dB – 0.009 0.030 % LSI output level Vout1 1 kHz, 0 dB 0.65 0.71 0.77 Vrms Evaluation board output level Vout2 1 kHz, 0 dB – 0.71 – Vrms Dynamic range D.R 1 kHz, −60 dB 74 86 – dB Signal-to-noise ratio1 S/N 1 kHz, 0/−∞ dB 74 84 – dB Ch. Sep 1 kHz, −∞/0 dB 72 82 – dB Total harmonic distortion Channel separation 1. Signal-to-noise is measured following a device reset, with DATA = 0 (DI = LOW). Under these conditions, the signal-to-noise ratio includes noise-shaper noise. NIPPON PRECISION CIRCUITS—10 SM5877AM AC Measurement Circuit and Conditions Measurement circuit block diagram CKO (384fs) Left channel BCK Signal generator LRCK (fs) Evaluation board Right channel Left/Right channel selector Distortion analyzer NF Corporation 3346A. 10 kΩ input impedance Shibasoku AD725C. RMS measurement DATA fs = 44.1 kHz DATA = 16 bits Measurement conditions Parameter1 Total harmonic distortion Symbol THD + N 3346A left/right-channel selector switch THRU AD725C distortion analyzer with built-in filter 20 kHz lowpass filter ON 400 Hz highpass filter OFF Output level Vout Dynamic range DR D-RANGE Signal-to-noise ratio S/N THRU 20 kHz lowpass filter ON 400 Hz highpass filter OFF JIS A filter ON Channel separation Ch. Sep THRU 20 kHz lowpass filter ON 400 Hz highpass filter OFF 1. Pins LO and RO should have an output load of 10 kΩ (min). NIPPON PRECISION CIRCUITS—11 SW2 SW3 MODE 23 2 DEEM SW4 3 CKO 0.1u + 0.01u + 100u DVSS DVDD 100u 0.01u + 1000p 680 1000p 680 33k 22k 33k 33u 10u 33u 10u 22k + RSTN 4 DVSS 100u 22k 22k + - + - 1/2 NJM2100D U3 33k 100p 1/2 NJM2100D U2 33k 100p 33u 22k 33u 22k + DEEM DS 21 SM5877AM XVSS 20 5 BCKI AVSS 22k 22k 6.8k 6.8k 1500p 5.6k 0.1u 1500p 5.6k + - + - 0.1u NJM2100D U3 1/2 220p 5.6k 10u 100k 2.2u 10u 100k 2.2u NJM2100D U2 1/2 220p 5.6k + MUTE DI BCKI 6 DI LRCI 7 DVDD ATCK 8 LRCI MODE MUTEO 16 9 TSTN CKO XTO 19 X’tal AVDDR 15 10 TO1 DS ATCK 24 1 MUTE 10p 10p XTI 18 SW1 RSTN 22 0.01u RO 14 11 AVDDL + AVSS 13 12 LO 100u XVDD 17 AVDD 100 100 100p 100p R OUTPUT L VEE VCC OUTPUT SM5877AM Measurement circuit + + + NIPPON PRECISION CIRCUITS—12 SM5877AM FUNCTIONAL DESCRIPTION System Clock/Speed Switching (XTI, XTO, CKO, DS) The system clock on XTI can be set to run at one of two speeds, 384fs (normal speed) or 192fs (doublespeed), where fs is the input frequency on LRCI. The speed for CD playback is set by the input level on DS, as shown in table 1. The system clock should be fixed at 16.9344 MHz. Table 1. System clock select DS LOW (normal speed) HIGH (double speed) fXI (= 1/tXI) 384fs 192fs CD playback XTI frequency fXI 16.9344 MHz at fs = 44.1 kHz 16.9344 MHz at fs = 88.2 kHz CKO output clock frequency fCO 384fs 192fs Internal system clock period TSYS tXI tXI Parameter Symbol XTI input clock frequency Note that the input clock accuracy and signal-tonoise ratio greatly influence the AC analog characteristics. Accordingly, care should be taken to ensure that the clock is free from jitter. The system clock can be controlled by a crystal oscillator comprising a crystal connected between XTI and XTO and the built-in CMOS inverter. Alternatively, an external system clock can be input on XTI. As the internal CMOS inverter has a feedback resistor, the external clock can be AC coupled to XTI. The system clock is output on CKO. System Reset (RSTN) The device should be reset in the following cases. ■ ■ At power ON When LRCI and/or the system clock XTI stop, or other abnormalities occur. RSTN The device is reset by applying a LOW-level pulse on RSTN. At system reset, the internal arithmetic operation and output timing counter are synchronized on the next LRCI rising edge, as shown in figure 1. LOW 1 2 3 9 10 LRCI Internal reset LO Outputs muted RO Figure 1. System reset timing Audio Data Input (DI, BCKI, LRCI) Serial data bits are read into the SIPO register (serialto-parallel converter register) on the rising edge of the bit clock BCKI. as long as the clock frequency ratio between LRCI and the system clock XTI is maintained, phase differences between LRCI, BCKI and the system clock XTI do not affect the functional operation. Also, any jitter present on the data input clock does not appear as output pulse jitter. The arithmetic operation and output timing are independent of the input timing. Accordingly, after a reset, The bit clock frequency on BCKI should be between 32fs and 64fs. The digital audio data is input on DI in MSB-first, 2scomplement, 16-bit serial format. NIPPON PRECISION CIRCUITS—13 SM5877AM Deemphasis Filter (DEEM) The built-in digital deemphasis filter is designed to operate at 44.1 kHz. Deemphasis is ON when DEEM is HIGH, and OFF when DEEM is LOW. Attenuation (MDT, MCK, MLEN) The digital attenuation mode is selected when MODE is LOW. The attenuator operates by multiplying the internal 6-bit up/down counter’s output data with the signal data. The direction of the 6-bit up/down counter is controlled by the level on MUTE (down when MUTE is HIGH, and up when MUTE is LOW). The count is advanced on the rising edge of ATCK. When the count reaches 0 (down) or 63 (up), the counter automatically stops. The gain is set by the counter contents DATT as follows. DATT Gain = 20 × log ---------------- [dB] 63 Upon system initialization or when MODE changes state, DATT is set to 63, which corresponds to the maximum gain of 0 dB as shown in table 2. Table 2. Attenuator gain DATT Gain (dB) DATT Gain (dB) DATT Gain (dB) DATT Gain (dB) 63 0.0 47 −2.545 31 −6.160 15 −12.465 62 −0.139 46 −2.732 30 −6.444 14 −13.064 61 −0.280 45 −2.923 29 −6.739 13 −13.708 60 −0.424 44 −3.118 28 −7.044 12 −14.403 59 −0.570 43 −3.317 27 −7.360 11 −15.159 58 −0.718 42 −3.522 26 −7.687 10 −15.987 57 −0.869 41 −3.731 25 −8.028 9 −16.902 56 −1.023 40 −3.946 24 −8.383 8 −17.925 55 −1.180 39 −4.166 23 −8.752 7 −19.085 54 −1.339 38 −4.391 22 −9.138 6 −20.424 53 −1.501 37 −4.623 21 −9.542 5 −22.007 52 −1.667 36 −4.861 20 −9.966 4 −23.946 51 −1.835 35 −5.105 19 −10.412 3 −26.444 50 −2.007 34 −5.357 18 −10.881 2 −29.966 49 −2.183 33 −5.617 17 −11.378 1 −35.987 48 −2.362 32 −5.884 16 −11.904 0 −∞ Soft Mute (SMUTE) Soft mute mode is selected when MODE is HIGH. The up/down counter is switched to internal clock drive, and soft mute operation is controlled by MUTE only. When MUTE is LOW, soft mute is released. The attenuation counter output counts up, increasing the gain. The time taken to return to 0 dB is also 1024/fs. Soft mute operation is shown in figure 2. When MUTE goes HIGH, the up/down counter counts down. The total time to go from 0 to maximum mute is 1024/fs. This corresponds to approximately 23.2 ms at fs = 44.1 kHz. Upon system initialization or when MODE changes state, mute is released, which corresponds to the maximum gain of 0 dB. NIPPON PRECISION CIRCUITS—14 SM5877AM Infinity-Zero (MUTEO) The SM5877AM outputs an infinity-zero detection output signal under the following circumstances. MUTE From immediately after a reset input on RSTN until the initialization cycle finishes and the first data cycle occurs. When an infinity-zero occurs in the input data. When an infinity-zero is detected, a period of 214 × (1/fs) ≈ 0.37 seconds takes place before MUTEO goes HIGH. ■ 0 dB Gain –∞ 1024/fs 1024/fs ■ Figure 2. Soft mute operation example 214/fs 1 2 3 8 9 LRCI DI Signal No Signal Signal RSTN MUTEO Initialize Figure 3. MUTEO output timing TIMING DIAGRAMS Input Timing (DI, BCKI, LRCI) 1/fs MSB LSB MSB 16 bits LSB 16 bits Left channel Right channel DI BCKI (64fs max) LRCI TYPICAL APPLICATIONS Input Interface Circuits Normal Speed 16.9344 MHz crystal XTAI Sony CXD2500 LRCK 44.1 kHz XTI 2.1168 MHz XTO CKO LRCI DI DA16 DA15 PSSL 16.9344 MHz SM5877 BCKI DS NIPPON PRECISION CIRCUITS—15 SM5877AM 16.9344 MHz crystal X1 Matsushita MN6617 R/L 44.1 kHz XTI 2.1168 MHz XTO CKO LRCI SM5877 DI SRDATA SRCK SEL 16.9344 MHz BCKI IPSEL DS Double Speed 16.9344 MHz crystal XTAI Sony CXD2500 LRCK 16.9344 MHz 44.1 kHz (88.2 kHz) DA16 DA15 XTI LRCI DI 2.1168 MHz (4.2336 MHz) PSSL XTO CKO SM5877 BCKI DS Normal Normal/double speed control Double speed ( ) indicate double-speed mode Note that the output analog characteristics and other specifications are not guaranteed for a particular format or application circuit. Pins LO and RO should have an output load of 10 kΩ (min). NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9501AE 1995.06 NIPPON PRECISION CIRCUITS—16