SM5879AV NIPPON PRECISION CIRCUITS INC. 3rd-order Σ∆, 2-channel D/A Converter OVERVIEW The SM5879AV is a 3rd-order ∑∆, two-channel D/A convertor LSI for digital audio reproduction equipment. This device incorporate NPC's molybdenumgate CMOS technology and incorporates an 8-times oversampling digital filter and analog 3rd-order ∑∆ post-converter low-pass filters. This device features a compact 24-pin VSOP package and a D/A converter that provides both compact size and low power consumption. DVDD TEST P/M AVDDR RO AVSSR TO1 AVSSL LO AVDDL MUTEO DVSS 1 24 LRCI BCKI DI BB2 / BBON BB1 / MDT DEEM / MCK MUTE / MLEN XVDD XTO XTI S M 5 8 7 9 AV The SM5879AV also incorporates built-in digital bass boost and deemphasis filters, an attenuator, and soft mute function. Low-voltage operation is also supported. PINOUT (TOP VIEW) 12 XVSS CKO 13 FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Unit: mm 24-pin VSOP + 0.05 0.15 − 0.02 7.8 ± 0.1 0.65 0.5 ± 0.2 ■ ■ PACKAGE DIMENSIONS 1.25 +0.2 −0.1 ■ 2.7 to 3.3 V operating supply voltage 44.1 kHz sampling frequency 16.9344 MHz (384fs) system clock Built-in crystal oscillator circuit 16-bit, MSB first, rear-packed serial data input format (≤ 64 fs bit clock) 8-times oversampling digital filter • 32 dB stopband attenuation • +0.05 to -0.05 dB passband ripple Deemphasis filter operation • 36 dB stopband attenuation • -0.09 to +0.23 dB deviation from ideal deemphasis filter characteristics Attenuator • 7-bit attenuator (128 steps) set by microcontroller Soft mute function set by parallel setting • (approximately 1024/fs total muting time) Mono setting • Left or right channel mono selectable by microcontroller Built-in infinity-zero detection circuit ∑∆, two-channel D/A converter • 3rd-order noise shaper • 32fs oversampling Built-in 3rd-order post-converter low-pass filters 24-pin VSOP package Molybdenum-gate CMOS process 5.6 ± 0.1 7.6 ± 0.2 ■ 0.1 ± 0.1 ■ 0 to 10 0.22 +0.1 −0.05 ORDERING INFOMATION Device Package SM5879AV 24pin VSOP NIPPON PRECISION CIRCUITS—1 SM5879AV Theoretical Filter Characteristics Deemphasis OFF overall characteristics Frequency band Attenuation (dB) Parameter Passband ripple Stopband attenuation Built-in analog LPF compensation f @ fs = 44.1 kHz min typ max 0 to 0.4535fs 0 to 20.0 kHz −0.05 – +0.05 0.5465fs to 7.4535fs 24.1 to 328.7 kHz 32 – – 0.4535fs 20.0 kHz – −0.34 – Overall frequency characteristic (deemphasis OFF) 0 10 Gain(dB) 20 30 40 50 60 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 Frequency (Fs) Passband characteristic (deemphasis OFF) 0.0 Gain(dB) 0.2 0.4 0.6 0.8 0.000 0.125 0.250 0.375 0.4535 0.500 Frequency (Fs) NIPPON PRECISION CIRCUITS—2 SM5879AV Deemphasis ON overall characteristics Frequency band Attenuation (dB) Parameter Deviation from ideal deemphasis filter characteristics Stopband attenuation f @ fs = 44.1 kHz min typ max 0 to 0.4535fs 0 to 20.0 kHz −0.09 – +0.23 0.5465fs to 7.4535fs 24.1 to 328.7 kHz 36 – – 0.4535fs 20.0 kHz – −0.34 – Built-in analog LPF compensation Overall frequency characteristic (deemphasis ON) 0 10 Gain(dB) 20 30 40 50 60 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 Frequncy (Fs) Passband characteristic (deemphasis ON) 0 2 4 Gain(dB) 6 8 10 12 0.000 0.125 0.250 0.375 0.4535 0.500 Frequncy (Fs) NIPPON PRECISION CIRCUITS—3 SM5879AV PIN DESCRIPTION Number Name I/O Description 1 DVDD I- Digital supply pin. 2 TEST I Input for testing LSI. Test mode when HIGH. 3 P/M I Parallel/microcontroller setting selection pin. Parallel setting when HIGH. 4 AVDDR - Right-channel analog supply pin. 5 RO O Right channel analog output pin. 6 AVSSR - Right-channel analog ground pin. 7 TO1 O Test mode output. Normally LOW. 8 AVSSL - Left-channel analog ground pin. 9 LO O Left-channel analog output pin. 10 AVDDL O Left-channel analog supply pin. 11 MUTEO O Infinity-zero detection output 12 DVSS - Digital ground pin 13 CKO O Oscillator clock output. 16.9344 MHz. 14 XVSS - Crystal oscillator ground pin 15 XTI I Crystal oscillator or 16.9344-MHz external clock input pin 16 XTO O Crystal oscillator output pin 17 XVDD - Crystal oscillator supply pin 18 MUTE/ MLEN I P/M=H; soft mute control pin. Mute is active when HIGH. P/M=L; microcontroller interface clock 19 DEEM/ MCK I P/M=H; deemphasis control pin. Deemphasis is ON when HIGH. P/M=L; microcontroller interface clock 20 BB1/ MDT I P/M=H; bass boost setting switch pin 1 P/M=L; microcontroller interface serial data 21 BB2/ BBON IO 22 DI I Serial data input pin 23 BCKI I Bit clock input pin 24 LRCI I Sample rate clock (fs) input pin. Left channel when HIGH, and right channel when LOW. P/M=H; bass boost setting switch pin 2 P/M=L; bass boost detection output NIPPON PRECISION CIRCUITS—4 SM5879AV BLOCK DIAGRAM LRCI BCKI DI Input interface P /M MUTE / MLEN DEEM / MCK BB1 / MDT BB2 / BBON L Microcontroller interface MUTEO R Filter & attenuation operation block L R Timing control DVSS DVDD TEST TO1 CKO XVSS XTO XTI L PWM data generation block Noise shaper operation block XVDD R AVDDL AVDDR + − LO − AVSSL AVSSR + RO NIPPON PRECISION CIRCUITS—5 SM5879AV SPECIFICATIONS Absolute Maximum Ratings DVSS = AVSSL = AVSSR= XVSS = 0 V, AVDD = AVDDL = AVDDR Parameter Symbol Rating Unit Supply voltage range DVDD, AVDD, XVDD −0.3 to 7.0 V Input voltage range1 VIN1 DVSS − 0.3 to DVDD + 0.3 V XTI input voltage range VIN XVSS − 0.3 to XVDD + 0.3 V Storage temperature range Tstg −55 to 125 °C Power dissipation PD 250 mW Soldering temperature Tsld 255 °C Soldering time tsld 10 s Symbol Rating Unit DVDD, AVDD, XVDD 2.7 to 3.3 V DVDD − XVDD, DVDD − AVDD, XVDD − AVDD, DVSS − XVSS, DVSS − AVSS, XVSS − AVSS ±0.1 V Topr −20 to 70 °C 1. Pins TEST, P/ M, MUTE/ MLEN, DEEM/ MCK, BB1/ MDT, BB2/ BBON, DI, BCKI, LRCI Also applicable during supply switching. Recommended Operating Conditions DVSS = AVSSL = AVSSR = XVSS = 0 V, AVDD = AVDDL = AVDDR Parameter Supply voltage range Supply voltage variation Operating temperature range note) Since DVDD, XVDD, AVDDL, and AVDDR are connected via the LSI base board, current may flow if potential difference occurs among them. NIPPON PRECISION CIRCUITS—6 SM5879AV DC Electrical Characteristics Rating Parameter Symbol Condition Unit min typ max DVDD digital supply current1 IDDD – 3.70 7.40 mA XVDD system clock supply current1 IDDX – 0.55 1.10 mA 2 – 0.68 1.36 mA AVDD analog supply current1 IDDA XTI HIGH-level input voltage VIH1 Clock input 0.7XVDD – – V XTI LOW-level input voltage VIL1 Clock input – – 0.3XVDD V XTI AC-coupled input voltage VINAC 0.3XVDD – – Vp-p HIGH-level input voltage3 VIH2 0.7DVDD – – V LOW-level input voltage3 VIL2 – – 0.3DVDD V HIGH-level output voltage4 VOH IOH = −0.5mA DVDD − 0.4 – – V LOW-level output voltage4 VOL IOL = 0.5mA – – 0.4 V XTI HIGH-level input current IIH1 VIN = XVDD – 4 10 µA XTI LOW-level input current IIL1 VIN = 0 V – 4 10 µA IILH VIN = DVDD -1.0 – 1.0 µA ILL VIN = 0V -1.0 – 1.0 µA Input leakage current3 1. DVDD = AVDD = XVDD = 2.7V, XTI clock input frequency fXTI = 16.9344 MHz, no output load. 2. IDDA is the total current. 3. Pins TEST, P/ M, MUTE/ MLEN, DEEM/ MCK, BB1/ MDT, BB2/ BBON, DI, BCKI, LRCI 4. Pins MUTEO, CKO, BB2/ BBON, TO1 NIPPON PRECISION CIRCUITS—7 SM5879AV AC Electrical Characteristics System clock (XTI) Crystal Oscillator Rating Parameter Symbol Oscillator frequency Unit fOSC min typ max 10.0 16.9344 18.5 MHz External clock input Rating Parameter Symbol Unit min typ max HIGH-level clock pulsewidth tCWH 20.0 29.5 50 ns LOW-level clock pulsewidth tCWL 20.0 29.5 50 ns tXI 54.0 59.0 100 ns Clock pulse cycle XTI input clock t XI t CWL VIH1 0.5VDD VIL1 t CWH Serial input (BCKI, DI, LRCI) Rating Parameter Symbol Unit min typ max BCKI HIGH-level pulsewidth tBCWH 50 – – ns BCKI LOW-level pulsewidth tBCWL 50 – – ns BCKI pulse cycle tBCY 6tXI – – ns DI setup time tDS 50 – – ns DI hold time tDH 50 – – ns Last BCKI rising edge to LRCI edge tBL 50 – – ns LRCI edge to first BCKI rising edge tLB 50 – – ns Serial input timing BCKI 0.5VDD t BCWH t BCY t BCWL DI 0.5VDD t DS t DH LRCI 0.5VDD t LB t BL NIPPON PRECISION CIRCUITS—8 SM5879AV Control input P/M=H Rating Parameter Symbol Unit min typ max Rise time tr – – 50 ns Fall time tf – – 50 ns tr MUTE DEEN BB1 BB2 tr 90% 90% 10% 0.5VDD 10% Figure 1. P/M=L Rating Parameter Symbol Unit min typ max MCK LOW-level pulsewidth tMCWL 200 – – ns MCK HIGH-level pulsewidth tMCWH 200 – – ns MCK pulse width tMcy 400 – – ns MDT setup time tMDS 100 – – ns MDT hold time tMDH 100 – – ns MLEN setup time tMLH 100 – – ns MLEN hold time tMLW 200 – – ns Rise time tr – – 50 ns Fall time tf – – 50 ns 0.5VDD MCK t MCWH t MCWL t MCY MDT 0.5VDD t MDS t MDH MLEN 0.5VDD t MLS t MLH t MLW NIPPON PRECISION CIRCUITS—9 SM5879AV AC Analog Characteristics DVSS = AVSSL= AVSSR = XVSS = 0 V, DVDD = AVDDL = AVDDR = XVDD = 2.7V, P/M=2.7V, MUTE=0V, DEEM=0V, BB1=2.7V, BB2=2.7V, crystal oscillator frequency fOSC = 16.9344 MHz, Ta = 25 °C Rating Parameter Symbol Condition Unit min typ max THD + N 1 kHz, 0 dB – 0.0075 0.015 % LSI output level Vout1 1 kHz, 0 dB 0.65 0.70 0.75 Vrms Evaluation board output level Vout2 1 kHz, 0 dB – 0.70 – Vrms Dynamic range D.R 1 kHz, −60 dB 86.0 91.0 – dB Signal-to-noise ratio1 S/N 1 kHz, 0/−∞ dB 86.0 91.5 – dB Channel separation Ch. Sep 1 kHz, −∞/0 dB 80.0 87.0 – dB Total harmonic distortion 1. Signal-to-noise is measured following a device reset, with DATA = 0 (DI = LOW). Under these conditions, the signal-to-noise ratio includes noise-shaper noise. AC Measurement Circuit and Conditions Measurement circuit block diagram CKO(384fs) Signal Generator BCK LRCK(fs) DATA Left Channel Evaluation L/R Channel Board Selector Right Channel Distortion Analyzer 10kΩ Input Impedance NF Corporation 3346A fs= 44.1kHz DATA= 16bit RMS Measurement Shibasoku AD725C Measurement conditions Parameter1 Total harmonic distortion Symbol THD + N 3346A left/right-channel selector switch THRU AD725C distortion analyzer with built-in filter 20 kHz lowpass filter ON 400 Hz highpass filter OFF Output level Vout Dynamic range DR D-RANGE Signal-to-noise ratio S/N THRU 20 kHz lowpass filter ON 400 Hz highpass filter OFF JIS A filter ON Channel separation Ch. Sep THRU 20 kHz lowpass filter ON 400 Hz highpass filter OFF 1. Pins LO and RO should have an output load of 10 kΩ (min). NIPPON PRECISION CIRCUITS—10 CKO MLEN DI BCKI LRCI MCK MDT DVSS DVDD AVDD 100u - + 0.01u 0.01u 100u 0.01u 10p 10p AVSS TO1 33u 33u 33u 33k - + 33u 33u 33u 33k - + + 22k + 22k 5 22k + 4 2100D 6 NJM 33k 100p 2 NJM 2100D + 4 3 22k 33k 1 1500p 5.6k 1500p 5.6k 33u 6.8k 33u 6.8k + 22k + 22k 3 22k + 33u 2100D 8 2 NJM 220p 5.6k 8 6 NJM 2100D + 5 22k 33u 220p 5.6k + + - 100p 0.1u 0.1u + - 2.2u + - 2.2u 470u 100k 100p 100 100k 100 + 100p - 16.9344MHz - + MUTEO DVDD - SM5879 - LRCI - + 0.01u DVSS CKO XVSS MUTEO XTI AVDDL XTO LO AVSSL XVDD MUTE/MLEN TO1 DEEM/MCK AVSSR BB1/MDT RO BB2/BBON AVDDR DI P/M BCKI TEST - - + BBON R OUT VEE VCC L OUT SM5879AV Measurement circuit NIPPON PRECISION CIRCUITS—11 SM5879AV FUNCTIONAL DESCRIPTION System Clock Note that the input clock accuracy and jitter greatly influence the AC analog characteristics. The system clock can be controlled by a crystal oscillator consisting of a crystal connected between XTI and XTO and a built-in CMOS invertor or, alterna- tively, an external system clock. Since the built-in CMOS invertor has a feedback resistor, the external system clock can be AC coupled to XTI. The system clock is output from CKO. System Reset (RSTN) System reset for SM5879AV is performed by a builtin power ON reset circuit. Analog output is muted by this resetting, and muting is cleared by the ninth LCRI rise (See Figure 1). At system reset, the internal arithmetic operation and output timing counter are synchronized with the next LCRI rising edge and thereby reset again for synchronization with external elements. However, noise is generated due to the change in PWM output during a timing reset. An external mute circuit is necessary to prevent this noise. Power on Switch 1 2 3 9 10 LRCI Internal Reset LO RO Output Muted Figure 2. System reset timing Audio Data Input (DI, BCKI, LRCI) The digital audio data is input on DI in MSB-first, 2scomplement, 16-bit serial format. The bit clock frequency on BCKI should be between 32fs and 64fs. Serial data bits are read into the SIPO register (serialto-parallel converter register) on the rising edge of the bit clock BCKI. 1 / fs LRCI BCKI (MAX64fs) DI Lch Rch 16bit MSB LSB 16bit MSB LSB Figure 3. NIPPON PRECISION CIRCUITS—12 SM5879AV Selection and Setting of Functions SM5879AV offers a variety of functions. Fundamentally, there are two methods available for selecting and setting these functions. Microcontroller interface refers here to serial data transfer from the microcontroller using the three pins MDT, MCK, and MLEN. One method is using an external input pin; this is called parallel setting. The other method is by using the microcontroller interface, which is called microcontroller setting. These two methods of setting and selection are set by the P/M pin. When P/M is HIGH, parallel setting is used. When P/M is LOW, microcontroller setting is used. Table 1. Selection and Setting of Functions Function Setting Methods Function Parallel setting Related external pin name (When P/M is HIGH) Microcontroller setting Related flag (When P/M is LOW) Notes Bass boost BB1, BB2 FBB1, FBB2 Bass boost Bass boost detection output None Output to BBON Bass boost detection output Deemphasis filter DEEM FDEM Deemphasis filter Soft mute MUTE None (Enabled by attenuator) Soft mute Attenuator setting None 7 bits (A6 - A0) Attenuation Monaural setting None MONO, CSEL Stereo/mono output setting NIPPON PRECISION CIRCUITS—13 SM5879AV Microcontroller Interface For microcontroller setting (when P/M is HIGH), the microcontroller interface consisting of MDT (data), MCK (clock) and MLEN (latch enable) can be used. Data from the microcontroller is input to the inputstage shift registers at the rise of MCK. Changes in MDT should be performed at the rise of MCK. Serial data in the shift registers is latched in parallel to the flag registers at the rise of MLEN. Two flag registers are available, divided into the attenuation factor and mode flag by the D7 data. MLEN MCK MDT D0 D1 D2 D3 D4 D5 D6 D7 Figure 4. Format of microcontroller interface input Table 2. microcontroller setting flags Microcontroller serial data Flag D7 0 1 D6 A6 - D5 A5 FDEM D4 A4 FBB1 D3 A3 FBB2 D2 A2 MONO D1 A1 CSEL D0 A0 - A0 to A6: Attenuation factor (A6: MSB) FDEM: Deemphasis ON/OFF (ON when 1) FBB1: Bass boost setting switch flag 1 FBB2: Bass boost setting switch flag 2 MONO: Stereo/mono setting (Mono when 1) CSEL: Mono output channel selection (Right channel when 1) NIPPON PRECISION CIRCUITS—14 SM5879AV Bass Boost Two types of bass boost and gain modification can be set by either parallel or microcontroller. Table 3. Parallel setting pin name BB1 BB2 Mode Microcontroller setting flag FBB1 FBB2 H H Flat 1 H L Bass boost MIN L H Bass boost MAX L L Flat2 3 Max. Chrasteristic 2 1 Flat1 (0dB) 0 Boost (dB) -1 -2 Min. Charasteristic -3 -4 -5 -6 -7 -8 Flat2 (-8dB) -9 10 100 4 5 10 1000 10 Frequency (Fs) Figure 5. Bass boost mode frequency response Bass boost detection output With microcontroller setting (when P/M is LOW), the 21st pin is the BBON output pin and functions as output that detects the bass boost mode. BBON output is LOW when the bass boost mode is set to Flat 1 and HIGH in all other cases. Table 4. Microcontroller setting flag BB1 BB2 Mode BBON pin H H Flat 1 L H L Bass boost MIN H L H Bass boost MAX H L L Flat 2 H NIPPON PRECISION CIRCUITS—15 SM5879AV Deemphasis filter The built-in deemphasis filter in the SM5879AV operates at fs = 44.1 kHz. Table 5. Parallel setting pin name DEEM Microcontroller setting flag FDEM Deemphasis mode H ON L OFF Soft Mute With parallel setting (when P/M is HIGH), soft mute can be activated by the MUTE pin level setting using the built-in attenuation counter. When muting is activated, MUTE is HIGH. When soft mute is activated, the attenuation counter operates and lowers gain in 128 steps. The time until mute is activated is approximately 1024/fs ≈ 23.2 msec. The time required to release muting is the same. MUTE 0dB (Gain) −∞ 1024/fs 1024/fs Figure 6. Example of soft mute operation NIPPON PRECISION CIRCUITS—16 SM5879AV Attenuation The SM5879AV loads the attenuation factor with serial data by means of the microcontroller interface, thus enabling attenuation operation. MLEN MCK MDT A0 A1 (LSB) D0 D1 A2 A3 A4 A5 D2 D3 D4 D5 A6 (MSB) D6 0 D7 Figure 7. Method of setting the attenuation factor The attenuation computation is performed by multiplying the output of the internal 7-bit UP/DOWN counter output data by the signal data. When the con- tents of the counter are DATT, gain can be expressed by the following equations. L channel DATT Gain = 20 × log ---------------- [dB] 127 R channel DATT Gain = 20 × log ---------------- [dB] 127 When DATT = 0, this becomes -∞. When the attenuation factor is changed, it is smoothly changed from the previous setting until it reaches the value of the new setting as expressed by the above equations. The time required to change gain is approximately 1024 fs ≈ 23.2 msec when the time required to change one step of the attenuation factor is approximately 8 / fs ≈ 181.4 µsec over the range 0 dB to -∞. Setting1 Setting5 Setting3 (Gain) Setting2 Setting4 Time Figure 8. Example of attenuation gain NIPPON PRECISION CIRCUITS—17 SM5879AV Stereo/Mono Output Setting Mono output can be set via the microcontroller (when P/M is HIGH). Table 6. Microcontroller setting flag MONO CSEL Output H H R channel H L L channel L H L L Stereo Infinity-Zero Detection Output HIGH level is output from the infinity-zero detection output pin in the following cases with the SM5879AV. (1) From the time that power ON is reset until the first data comes in. (2) When the LOW level space of the DI pin has continued for 214× (1/fs) ≈ 0.37 [sec] or more. 214/fs 1 2 3 9 LRCI DI Signal No Signal Signal RSTN MUTEO Internal Status Initialize Figure 9. NIPPON PRECISION CIRCUITS—18 SM5879AV TIMING DIAGRAMS Input Timing (DI, BCKI, LRCI) 1 / fs LRCI BCKI (MAX64fs) DI Lch Rch 16bit MSB LSB 16bit MSB LSB TYPICAL APPLICATIONS Input Interface Circuits Normal Speed X'tal (16.9344MHz) SONY CXD2500 XTI XTAI 16.9344MHz CKO LRCK 44.1kHz LRCI DA16 DA15 DI 2.1168MHz XTO SM5879 BCKI PSSL NIPPON PRECISION CIRCUITS—19 SM5879AV NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2 chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9702BE 1997.11 NIPPON PRECISION CIRCUITS—20