SM5907AF compression and non compression type shock-proof memory controller NIPPON PRECISION CIRCUITS INC. Overview Features selected from 4 options (4M, 4M× 2, 16M, 16M× 2). It operates from a 2.4 to 3.6 V supply voltage range. ina ry The SM5907AF is a compression and non compression type shock-proof memory controller LSI for compact disc players. The compression level can be set in 4 levels, and external memory can be - 2-channel processing - Serial data input ⋅ 2s complement, 16-bit/MSB first, right-justified format - Microcontroller interface ⋅ Serial command write and status read-out ⋅ Data residual detector: 15-bit operation, 16-bit output ⋅ Forced mute ⋅ Wide capture function (up to 3 × speed input rate) - System clock input ⋅ 384fs (16.9344 MHz) - Shock-proof memory controller ⋅ ADPCM compression method lim ⋅ 4-level compression mode selectable 4-bit compression mode 2.78 s/Mbit 5-bit compression mode 2.22 s/Mbit 6-bit compression mode 1.85 s/Mbit Full-bit non compression mode 0.74 s/Mbit ⋅ 4 external DRAM configurations selectable - Extension I/O Microcontroller interface for external control using 5 extension I/O pins - +2.4 to +3.6 V operating voltage range - Schmitt inputs All input pins (including I/O pins) except CLK (system clock) - Reset signal noise elimination Approximately 3.8 µs or longer (65 system clock pulses) continuous LOW-level reset - 44-pin QFP package (0.8 mm pin pitch) 1 or 2 × 16M DRAM (4M × 4 bits, refresh pre cycle = 2048 cycle) 1 or 2 × 4M DRAM (1M × 4 bits) Ordering Information SM5907AF 44-pin QFP NIPPON PRECISION CIRCUITS-1 SM5907AF Package dimensions (Unit: mm) 44-pin QFP 10.00 0.30 ina ry 12.80 0.30 10.00 0.30 0.60 0.20 0.15 0.05 .7 0.15 0.80 0.35 0.10 A3 A2 A1 A0 A4 A5 A6 A7 A8 A9 NRAS 44 43 42 41 40 39 38 37 36 35 34 lim 0.20MAX 1 33 NWE UC1 2 32 D1 UC2 3 31 D0 30 D3 29 D2 28 NCAS 27 A10/ NCAS2 26 YMCLK 25 YMDATA SM5 9 0 7 A F VDD2 pre 21 22 VDD1 YDMUTE 20 23 ZSENSE 11 NRESET YMLD YSRDATA 19 24 18 10 YFCLK VSS 17 9 YFLAG CLK 16 8 ZSRDATA NTEST 15 7 ZLRCK NCAS3 14 6 ZSCK UC5 13 5 YSCK UC4 12 4 YLRCK UC3 YBLKCK (Top View) C0 0.20 1.50 0.10 (1.40) 4 Pinout (1.40) 0 to 10 12.80 0.30 0.17 0.05 NIPPON PRECISION CIRCUITS-2 SM5907AF Pin description Pin number Pin name I/O Function Setting 1 VDD2 - VDD supply pin 2 UC1 Ip/O Microcontroller interface extension I/O 1 3 UC2 Ip/O Microcontroller interface extension I/O 2 4 UC3 Ip/O 5 UC4 Ip/O 6 UC5 Ip/O 7 NCAS3 O 8 NTEST Ip 9 CLK I 10 VSS - 11 YSRDATA I 12 YLRCK I 13 YSCK I ZSCK O 15 ZLRCK O 16 ZSRDATA O 17 YFLAG I 18 YFCLK I 19 YBLKCK I Microcontroller interface extension I/O 3 Microcontroller interface extension I/O 4 Microcontroller interface extension I/O 5 DRAM2 CAS control (with two 16M DRAMs) Test pin Ground Audio serial input data Audio serial input LR clock Left channel Right channel Left channel Right channel Audio serial input bit clock Audio serial output bit clock Audio serial output LR clock Audio serial output data Signal processor IC RAM overflow flag Overflow Crystal-controlled frame clock Subcode block clock signal 20 NRESET I System reset pin 21 ZSENSE O Microcontroller interface status output Reset 22 VDD1 - VDD supply pin 23 YDMUTE I Forced mute pin 24 YMLD I Microcontroller interface latch clock 25 YMDATA I Microcontroller interface serial data 26 YMCLK I Microcontroller interface shift clock 27 A10 O DRAM address 10 Mute (NCAS2) O DRAM2 CAS control (with two 4M DRAMs) 28 NCAS O DRAM CAS control 29 D2 Ip/O DRAM data input/output 2 30 D3 Ip/O DRAM data input/output 3 31 D0 Ip/O DRAM data input/output 0 32 D1 Ip/O DRAM data input/output 1 33 NWE O DRAM WE control 34 NRAS O DRAM RAS control 35 A9 O DRAM address 9 36 A8 O DRAM address 8 37 A7 O DRAM address 7 38 A6 O DRAM address 6 39 A5 O DRAM address 5 40 A4 O DRAM address 4 41 A0 O DRAM address 0 42 A1 O DRAM address 1 43 A2 O DRAM address 2 44 A3 O DRAM address 3 Ip : Input pin with pull-up resistor Test 16.9344 MHz clock input pre lim 14 L ina ry H Ip/O : Input/Output pin (With pull-up resistor when in input mode) NIPPON PRECISION CIRCUITS-3 SM5907AF Absolute maximum ratings (VSS = 0V, VDD1, VDD2 pin voltage = VDD) Symbol Rating Unit Supply voltage VDD - 0.3 to 4.6 V Input voltage VI VSS - 0.3 to VDD + 0.3 V Storage temperature TSTG - 55 to 125 ˚C Power dissipation PD 350 mW ina ry Parameter Note. Refer to pin summary on the next page. Values also apply for supply inrush and switch-off. Electrical characteristics Recommended operating conditions (VSS = 0V, VDD1, VDD2 pin voltage = VDD) Parameter Symbol Supply voltage VDD Operating temperature TOPR Rating 2.4 to 3.6 V - 40 to 85 ˚C lim DC characteristics Unit Standard voltage:(VDD1 = VDD2 = 3.0 to 3.6 V, VSS = 0 V, Ta = - 40 to 85 ˚C) Parameter Current consumption Input voltage Pin Symbol VDD CLK Condition IDD H level VIH1 L level VIL1 VINAC Max (*A)SHPRF ON 4.5 8.0 mA (*A)Through mode 1.8 3.0 mA AC coupling L level VIL2 Output voltage (*4,5) H level VOH1 IOH = - 0.5 mA VOL1 IOL = 0.5 mA Input current CLK pre H level Input leakage current IIH1 Unit Typ (*2,3,4) L level Rating VIH2 Min 0.7VDD V 0.3VDD 1.0 VP-P 0.7VDD V 0.3VDD VIN = VDD V VDD - 0.4 V V 0.4 V 5 25 115 µA IIL1 VIN = 0V 5 25 115 µA (*3,4) IIL2 VIN = 0V 1 4 15 µA (*2,3,4) ILH VIN = VDD 1.0 µA (*2) ILL VIN = 0V 1.0 µA (*A) VDD1 = VDD2 = 3 V, CLK input frequency fXTI= 384fs = 16.9344 MHz, all outputs unloaded, SHPRF: Shock-proof, typical values are for VDD1 = VDD2 = 3 V. NIPPON PRECISION CIRCUITS-4 SM5907AF Low-voltage:(VDD1 = VDD2 = 2.4 to 3.0 V, VSS = 0 V, Ta = - 20 to 70 ˚C) Parameter Pin Symbol Condition Rating Min Input voltage VDD CLK IDD H level VIH1 L level VIL1 H level Output voltage (*4,5) H level Input current CLK L level (*3,4) Input leakage current (*2,3,4) (*2) (*B)SHPRF ON 4.5 8.0 mA (*B)Through mode 1.8 3.0 mA 0.7VDD 0.3VDD VINAC (*2,3,4) L level Max ina ry Current consumption Unit Typ AC coupling VIH2 1.0 VP-P V IIH1 0.3VDD IOH = - 0.5 mA VOL1 IOL = 0.5 mA V 0.7VDD VIL2 VOH1 V VDD - 0.4 VIN = VDD V V 0.4 V 5 25 115 µA IIL1 VIN = 0V 5 25 115 µA IIL2 VIN = 0V 1 4 15 µA ILH VIN = VDD 1.0 µA ILL VIN = 0V 1.0 µA pre lim (*B) VDD1 = VDD2 = 3 V, CLK input frequency fXTI= 384fs = 16.9344 MHz, all outputs unloaded, SHPRF: Shock-proof, typical values are for VDD1 = VDD2 = 3 V. <Pin summary> (*1) (*2) Pin function Clock input pin (AC input) Pin name CLK Pin function Schmitt input pins Pin name YSRDATA, YLRCK, YSCK, YFLAG, YFCLK, NRESET, YBLKCK, YDMUTE, YMLD, YMDATA, YMCLK (*3) Pin function Schmitt input pin with pull-up Pin name NTEST (*4) Pin function I/O pins (Schmitt input with pull-up in input state) Pin name UC1, UC2, UC3, UC4, UC5, D0, D1, D2, D3 (*5) Pin function Outputs Pin name ZSCK, ZLRCK, ZSRDATA, ZSENSE, NCAS, NCAS2, NCAS3, NWE, NRAS, A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10 NIPPON PRECISION CIRCUITS-5 SM5907AF AC characteristics Standard voltage: VDD1 = VDD2 = 3.0 to 3.6 V, VSS = 0 V, Ta = -40 to 85 ˚C Low-voltage: VDD1 = VDD2 = 2.4 to 3.0 V, VSS = 0 V, Ta = -20 to 70 ˚C (*) Typical values are for fs = 44.1 kHz Parameter Symbol ina ry System clock (CLK pin) Condition Rating System clock Clock pulsewidth (HIGH level) Clock pulsewidth (LOW level) Clock pulse cycle tCWH tCWL tCY System clock input CLK 384fs Unit Min Typ Max 26 29.5 125 ns 26 29.5 125 ns 58 59 250 ns 0.5VDD t CWH t CWL t CY lim Serial input (YSRDATA, YLRCK, YSCK pins) Parameter Symbol YSCK pulsewidth (HIGH level) tBCWH tBCWL tBCY tDS tDH tBL tLB Min YSCK pulsewidth (LOW level) YSCK pulse cycle YSRDATA setup time YSRDATA hold time Last YSCK rising edge to YLRCK edge YLRCK edge to first YSCK rising edge Rating Typ Unit Max 75 ns 75 ns 150 ns 50 ns 50 ns 50 ns 50 ns 0 3fs Memory system ON pre YLRCK pulse frequency See note below. Condition (MSON=H) fs fs Memory system OFF (MSON=L) Note. When the memory system is OFF (through mode), the input data rate is synchronized to the system clock input (384fs), so input data needs to be at 1/384 of this frequency. But, this IC can tolerate a certain amount of jitter. For details, refer to Through-mode operation. t BCWH t BCY t BCWL YSCK t DS 0.5VDD t DH YSRDATA 0.5VDD t BL YLRCK t LB 0.5VDD NIPPON PRECISION CIRCUITS-6 SM5907AF Microcontroller interface (YMCLK, YMDATA, YMLD, ZSENSE pins) Parameter Symbol Rating Min tMCWL tMCWH tMDS tMDH tMLWL tMLS tMLH tr tf tPZS YMCLK LOW-level pulsewidth YMDATA setup time YMDATA hold time YMLD LOW-level pulsewidth YMLD setup time YMLD hold time Rise time Fall time ZSENSE output delay Max 30 + 2tCY ns 30 + 2tCY ns 30 + tCY ns 30 + tCY ns 30 + 2tCY ns 30 + tCY ns ina ry YMCLK HIGH-level pulsewidth Unit Typ 30 + tCY ns 100 ns 100 ns 100 + 3tCY ns Note. tCY is the system clock cycle time (59ns typ). YMDATA 0.5VDD t MDS t MDH YMCLK 0.5VDD t MCWH t MLS t MLH pre lim t MCWL YMLD t MLWL 0.5VDD t PZS ZSENSE 0.5VDD tf YMCLK YMDATA YMLD tr 0.7 V DD 0.7 V DD 0.3 V DD 0.3 V DD 0.5VDD Reset input (NRESET pin) Parameter Symbol First HIGH-level after supply voltage rising edge NRESET pulsewidth tHNRST tNRST Rating Min 0 64 Typ Unit Max tCY (Note) tCY (Note) Note. tCY is the system clock (CLK) input (384fs) cycle time. tCY = 59 ns, tNRST (min) = 3.8 µs when fs = 44.1 kHz VDD1,VDD2 NRESET t HNRST t NRST NIPPON PRECISION CIRCUITS-7 SM5907AF Serial output (ZSRDATA, ZLRCK, ZSCK pins) Parameter Symbol Condition ZSCK pulsewidth tSCOW tSCOY tDHL tDLH 15 pF load Rating Min ZSCK Typ Max 1/96fs 15 pF load 1/48fs 15 pF load 0 60 ns 15 pF load 0 60 ns ina ry ZSCK pulse cycle ZSRDATA and ZLRCK output delay time Unit 0.5VDD t SCOW t SCOW t SCOY ZSRDATA ZLRCK 0.5VDD t DHL t DLH DRAM access timing (NRAS, NCAS, NCAS2, NCAS3, NWE, A0 to A10, D0 to D3) Parameter Symbol Condition NRAS pulsewidth tRASL tRASH tRCD tCASH tCASL tRADS tRADH tCADS tCADH tCWDS tCWDH tCRDS tCRDH tWEL tWCS 15 pF load Rating lim Min NRAS falling edge to NCAS falling edge NCAS pulsewidth NRAS Setup time falling edge to address Hold time NCAS Setup time falling edge to address Hold time NCAS Setup time Hold time pre falling edge to data write NCAS Input setup rising edge to data read Input hold NWE pulsewidth NWE falling edge to NCAS falling edge Refresh cycle (fs = 44.1 kHz playback) tREF 15 pF load (RDEN=H) tCY(note) tCY tCY tCY tCY tCY tCY tCY tCY tCY tCY 3 2 5 15 pF load 3 15 pF load 1 15 pF load 1 15 pF load 1 15 pF load 5 15 pF load 3 15 pF load 3 40 ns 0 ns 15 pF load 6 15 pF load 3 tCY tCY Non compression 3.0 ms 6-bit compression 7.3 ms DRAM 5-bit compression 8.8 ms × 1 or × 2 4-bit compression 10.9 ms Non compression 5.9 ms 6-bit compression 14.6 ms DRAM 5-bit compression 17.5 ms × 1 or × 2 4-bit compression 21.8 ms 4M Memory system ON Decode sequence operation Max 5 15 pF load 15 pF load Typ Unit 16M Note. tCY is the system clock (CLK) input (384fs) cycle time. tCY = 59 ns when fs = 44.1 kHz NIPPON PRECISION CIRCUITS-8 SM5907AF DRAM access timing (with single DRAM) t RASL 5 tCY t RASH 3 tCY NRAS A0 to A10 ;;;;;;; ;;;;;;; ;;;;;;; ;;;;;;; t RADS 1tCY t RADH 1tCY t CWDS 3tCY D0 to D3 (WRITE) ina ry NCAS t CASH 5tCY t CASL 3 tCY t RCD 2tCY t CADS 1tCY t CADH 5tCY t CWDH 3tCY t CRDS D0 to D3 (READ) ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; t CRDH ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; t WCS 3tCY NWE (WRITE) ;;;;;;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; t WEL 6tCY pre lim The NWE terminal output is fixed HIGH during read timing. DRAM access timing (with double DRAMs) t RASL 5 tCY t RASH 3tCY NRAS t RCD 2tCY t CASL 3tCY t CASH 5tCY t RDC 2 tCY t CASL 3tCY t CASH 5tCY NCAS (DRAM1 SELECT) NCAS2, NCAS3 (DRAM2 SELECT) t RADS 1t ;;;;;;; ;;;;;;; ;;;;;;; ;;;;;;; CY A0 to A10 t RADH 1tCY t CADS 1tCY t CWDS 3tCY t CADH 5tCY ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; t CWDH 3tCY ;;;;;;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;; D0 to D3 (WRITE) D0 to D3 (READ) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; t WCS 3 tCY NWE (WRITE) t WCS t CRDS t CRDH ;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; t WEL 6 tCY The NWE terminal output is fixed HIGH during read timing. NCAS terminal output is fixed HIGH when selecting "DRAM2". NCAS2/NCAS3 terminal outputs are fixed HIGH when selecting "DRAM1". NIPPON PRECISION CIRCUITS-9 SM5907AF Control Input 1 YFLAG Compression Mode Decoder pre YSRDATA Control Input 2 NCAS NRAS CLK NWE DRAM Interface NTEST NCAS2 NRESET Encoder NCAS3 YDMUTE YSCK YLRCK ZSRDATA General Port D0 to D3 UC1 to UC5 Through Mode A0 to A10 ZSENSE Microcontroller Interface lim YMLD Input Interface Input Buffer YMDATA YMCLK ina ry Output Interface YBLKCK YFCLK ZSCK SM5907 ZLRCK Block diagram NIPPON PRECISION CIRCUITS-10 SM5907AF Functional description SM5907AF has two modes of operation; shockproof mode and through mode. The operating sequences are controlled using commands from a microcontroller. Command format ina ry Microcontroller interface Commands from the microcontroller are input using 3-wire serial interface inputs; data (YMDATA), bit clock (YMCLK) and load signal (YMLD). In the case of a read command from the microcontroller, bit serial data is output (ZSENSE) synchronized to the bit clock input (YMCLK). Write command format (Commands 80 to 85) DATA 8bit YMDATA D7 D6 D5 D4 D3 YMCLK D2 D1 D0 B7 B6 pre lim YMLD COMMAND 8bit B5 B4 B3 B2 B1 B0 Read command format (Commands 90, 91, 93) COMMAND 8bit YMDATA B7 B6 B5 B4 B3 B2 B1 B0 YMCLK YMLD ZSENSE S7 STATUS 8bit S6 S5 S4 S3 S2 S1 S0 Read command format (Command 92 (memory residual read)) COMMAND 8bit YMDATA B7 B6 B5 B4 B3 B2 B1 B0 YMCLK YMLD RESIDUAL DATA 16bit ZSENSE S7 S6 S1 S0 M1 M2 M7 M8 NIPPON PRECISION CIRCUITS-11 SM5907AF Command table Write command summary 80hex = 1000 0000 Bit Name MSWREN D6 MSWACL D5 MSRDEN D4 MSRACL D3 MSDCN2 ina ry Shock-proof memory system settings D7 B3 B2 B1 B0 B7 B6 B5 B4 MS command 80 Function H operation Reset level Encode sequence start/stop Start L L Write address reset Reset Decode sequence start/stop Start L Read address reset Reset L MSDCN2=H, MSDCN1=H: 3-pair comparison start L MSDCN2=H, MSDCN1=L: 2-pair comparison start D2 MSDCN1 D1 WAQV D0 MSON MSDCN2=L, MSDCN1=H: Direct-connect start L MSDCN2=L, MSDCN1=L: Connect operation stop L ON L 81hex = 1000 0001 Extension I/O port input/output settings Name D6 D5 UC5OE D3 UC4OE D2 UC3OE D1 UC2OE D0 UC1OE H operation Reset level Extension I/O port UC5 input/output setting Output L Extension I/O port UC4 input/output setting Output L Extension I/O port UC3 input/output setting Output L Extension I/O port UC2 input/output setting Output L Extension I/O port UC1 input/output setting Output L pre D4 Function lim Bit D7 B3 B2 B1 B0 Valid B7 B6 B5 B4 Extension I/O settings 81 Q data valid Memory system ON B7 B6 B5 B4 Extension port HIGH/LOW output level A port setting is invalid if that port has already been defined as an input using the 81H command above. Bit B3 B2 B1 B0 Extension I/O output data settings 82 82hex = 1000 0010 Name Function D4 UC5WD Extension I/O port UC5 output data setting H output L D3 UC4WD Extension I/O port UC4 output data setting H output L D2 UC3WD Extension I/O port UC3 output data setting H output L D1 UC2WD Extension I/O port UC2 output data setting H output L D0 UC1WD Extension I/O port UC1 output data setting H output L H operation Reset level D7 D6 D5 NIPPON PRECISION CIRCUITS-12 SM5907AF B3 B2 B1 B0 B7 B6 B5 B4 MUTE, CMP12 settings 83 83hex = 1000 0011 Bit Name Function H operation Reset level MUTE Forced muting (changes instantaneously) Mute ON L CMP12 12-bit comparison connect/ 16-bit comparison connect D6 D5 D4 D3 D2 D1 D0 ina ry D7 12-bit comparison L B7 B6 B5 B4 Option settings 85 B3 B2 B1 B0 Refer to "Force mute", "12-bit comparison connection". 85hex = 1000 0101 Bit Name D7 RAMS1 Function H operation Reset level DRAM type setting L RAMS1=0 RAMS2=0 when 16M DRAM(4M × 4bit) × double RAMS1=1 RAMS2=0 when 4M DRAM(1M × 4bit) × single D6 RAMS2 RAMS1=0 RAMS2=1 when 4M DRAM(1M × 4bit) × double L pre lim RAMS1=1 RAMS2=1 when 16M DRAM(4M × 4bit) × single D5 YFLGS FLAG6 set conditions (reset using status read command 90H) L - When YFLGS=0, YFCKP=0, YFCLK input falling edge, YFLAG=L - When YFLGS=0, YFCKP=1, YFCLK input rising edge, YFLAG=L D4 YFCKP - When YFLGS=1, YFCKP=0, YFLAG=L L - When YFLGS=1, YFCKP=1, YFLAG=H D3 COMPFB Full-bit compression mode L D2 COMP6B 6-bit compression mode H D1 COMP5B 5-bit compression mode L D0 COMP4B 4-bit compression mode L When the number of compression bits is set incorrectly (2 or more bits in D0 to D3 are set to 1 or all bits are set to 0), 6-bit compression mode is selected. NIPPON PRECISION CIRCUITS-13 SM5907AF Read command summary B3 B2 B1 B0 B7 B6 B5 B4 Shock-proof memory status (1) 90 90hex = 1001 0000 Name Function S7 FLAG6 Signal processor IC jitter margin exceeded HIGH-level state Exceeded S6 MSOVF Write overflow (Read once only when RA exceeds WA) DRAM overflow S5 BOVF Input buffer memory overflow Input buffer memory overflow ina ry Bit because sampling rate of input data is too fast S4 S3 DCOMP Data compare-connect sequence operating S2 MSWIH Encode sequence stop due to internal factors Encoding stopped S1 MSRIH Decode sequence stop due to internal factors Decoding stopped S0 Compare-connect sequence operating B7 B6 B5 B4 Shock-proof memory status (2) 91 B3 B2 B1 B0 Refer to "Status flag operation summary". 91hex = 1001 0001 Name S7 MSEMP S6 OVFL S5 ENCOD S4 DECOD S3 S2 S1 HIGH-level state Valid data empty state (Always HIGH when RA exceeds VWA) No valid data Write overflow state (Always HIGH when WA exceeds RA) Memory full Encode sequence operating state Encoding Decode sequence operating state Decoding Refer to "Status flag operation summary". pre S0 Function lim Bit NIPPON PRECISION CIRCUITS-14 SM5907AF B3 B2 B1 B0 B7 B6 B5 B4 Shock-proof memory valid data residual 92 92hex = 1001 0010 Name Function S7 AM21 Valid data accumulated VWA-RA (MSB) S6 AM20 S5 AM19 S4 AM18 S3 AM17 S2 AM16 S1 AM15 S0 AM14 M1 AM13 M2 AM12 M3 AM11 M4 AM10 M5 AM09 M6 AM08 M7 AM07 M8 AM06 4M×1, 4M×2, 16M×1 16M×2 8M bits 16M bits 4M bits 8M bits 2M bits 4M bits 1M bits 2M bits 512k bits 256k bits 1M bits 512k bits 128k bits 64k bits 32k bits 256k bits 128k bits 64k bits 16k bits 32k bits 8k bits 16k bits 4k bits 8k bits 2k bits 4k bits 1k bits 512 bits 256 bits 2k bits 1k bits 512 bits ina ry Bit Note. The time conversion factor varies depending on the compression bit mode.(M = 1,048,576 K= 1,024) Residual time (sec) = Valid data residual (Mbits) × Time conversion value K pre lim where the Time conversion value K (sec/Mbit) ≈ 2.78(4 bits), 2.22 (5 bits), 1.85 (6 bits) and 0.74 (Full bits). Bit Name Function B3 B2 B1 B0 Input data entering (or output data from) an extension port terminal is echoed to the microcontroller. (That is, the input data entering an I/O port configured as an input port using the 81H command, OR the output data from a pin configured as an output port using the 82H command.) B7 B6 B5 B4 Extension I/O inputs 93 93hex = 1001 0011 HIGH-level state S7 S6 S5 S4 UC5RD S3 UC4RD S2 UC3RD S1 UC2RD S0 UC1RD NIPPON PRECISION CIRCUITS-15 SM5907AF Status flag operation summary Flag Read name method FLAG6 READ Meaning - Indicates to the CD signal processor DSP (used for error correction, de-interleaving) that a 90H Set - Set according to the YFLAG input and the operating state of YFCKP and YFLGS. ina ry bit 7 disturbance has exceeded the RAM jitter margin. FLAG6 set conditions When YFLGS=0, YFCKP=0, YFCLK input falling edge, YFLAG=L When YFLGS=0, YFCKP=1, YFCLK input rising edge, YFLAG=L When YFLGS=1, YFCKP=0, YFLAG=L When YFLGS=1, YFCKP=1, YFLAG=H Reset - By 90H status read - By 80H command when MSON=ON - After external reset MSOVF READ Meaning 90H bit 6 - Indicates once only that a write to external DRAM has caused an overflow. (When reset by the 90H status read command, this flag is reset even if the overflow condition continues.) Set Reset - When the write address (WA) exceeds the read address (RA) - By 90H status read - When a read address clear (MSRACL) or write address clear (MSWACL) command is issued - After external reset READ 90H bit 5 Meaning - Indicates input data rate was too fast causing buffer overflow and loss of data Set - When inputs a data during a buffer memory overflow lim BOVF Reset - By 90H status read - When a read address clear (MSRACL) or write address clear (MSWACL) command is issued DCOMP READ 90H bit 3 - After external reset Meaning - Indicates that a compare-connect sequence is operating Set - When a (3-pair or 2-pair) compare-connect start command is received (MSDCN2=1) - When a direct connect command is received (MSDCN2=0, MSDCN1=1) Reset - When a (3-pair or 2-pair) comparison detects conforming data - When the connect has been performed after receiving a direct connect command - When a compare-connect stop command (MSDCN2=0, MSDCN1=0) is received - When a MSWREN=1 command is received (However, if a compare-connect command is pre received at the same time, the compare-connect command has priority.) MSWIH READ Meaning 90H bit 2 Set Reset - After external reset - Indicates that the encode sequence has stopped due to internal factors (not microcontroller commands) - When FLAG6 (above) is set - When BOVF (above) is set - When MSOVF (above) is set - When conforming data is detected after receiving a compare-connect start command - When the connect has been performed after receiving a direct connect command - When a read address clear (MSRACL) or write address clear (MSWACL) command is received MSRIH READ Meaning 90H bit 1 - After external reset - Indicates that the decode sequence has stopped due to internal factors (not microcontroller commands) Set - When the valid data residual becomes 0 Reset - By 90H status read - When a read address clear (MSRACL) or write address clear (MSWACL) command is issued - After external reset NIPPON PRECISION CIRCUITS-16 SM5907AF Flag Read name method MSEMP READ Meaning - Indicates that the valid data residual has become 0 91H Set - When the VWA (final valid data's next address) = RA (address from which the next read would take place) Reset OVFL READ Meaning 91H Set bit 6 ina ry bit 7 - Whenever the above does not apply - Indicates a write to external DRAM overflow state - When the write address (WA) exceeds the read address (RA). (Note: This flag is not set when WA=RA through an address initialize or reset operation.) Reset - When the read address (RA) is advanced by the decode sequence - When a read address clear (MSRACL) or write address clear (MSWACL) command is issued - After external reset ENCOD READ Meaning - Indicates that the encode sequence (input data entry, encoding, DRAM write) is operating 91H Set - By the 80H command when MSWREN=1 bit 5 - When conforming data is detected during compare-connect operation - When the connect has been performed after receiving a direct connect command Reset - When the FLAG6 flag=1 (above) - When the OVFL flag=1 (above) - By the 80H command when MSWREN=0 - By the 80H command when MSDCN1=1 or MSDCN2=1 (compare-connect start command) pre lim - By the 80H command when MSON=0 - After external reset Note. Reset conditions have priority over set conditions. For example, if the 80H command has MSWREN=1 and MSDCN1=1, the ENCOD flag is reset and compare-connect operation starts. DECOD READ Meaning 91H bit 4 - Indicates that the decode sequence (read from DRAM, decoding, attenuation, data output) is operating Set - By a new 80H command when MSRDEN=1 and the MSEMP flag=0 (above) Reset - Whenever the above does not apply NIPPON PRECISION CIRCUITS-17 SM5907AF Write command supplementary information 80H (MS command) -MSRACL - MSWREN When 0: Encode sequence stops - MSWACL When 1: Initializes the write address (WA) When 0: No operation - MSRDEN When 1: Initializes the read address (RA) When 0: No operation - MSDCN2, MSDCN1 ina ry When 1: Encode sequence starts Invalid when MSON is not 1 within the same 80H command Invalid when FLAG6=1 Invalid when OVFL=1 Invalid when a compare-connect start command (MSDCN2=1 or MSDCN1=1) occurs simultaneously Direct connect if a compare-connect sequence is already operating When 1 and 0: 2-pair compare-connect sequence starts When 0 and 1: Direct connect sequence starts When 0 and 0: Compare-connect sequence stops. No operation if a compare-connect sequence is not operating. - WAQV When 1: The immediately preceding YBLKCK falling-edge timing WA (write address) becomes the VWA (valid write address). When 0: No operation - MSON lim When 1: Decode sequence starts Does not perform decode sequence if MSON=1.If there is no valid data, decode sequence temporarily stops. But, because the MSRDEN flag setting is maintained as is, the sequence automatically re-starts when valid data appears. When 1 and 1: 3-pair compare-connect sequence starts When 0: Decode sequence stops When 1: Memory system turns ON and shockproof operation starts When 0: Memory system turns OFF and throughmode playback starts. (In this mode, the attenuator is still active.) 81H (Extension I/O port settings) pre 82H (Extension I/O port output data settings) NIPPON PRECISION CIRCUITS-18 SM5907AF 83H ( MUTE, 12-bit comparison connection settings) - MUTE (forced muting) - MUTE, YDMUTE relationship When 0: No muting(note 1) (note1) Effective at the start left-channel output data. 85H (option settings) - RAMS1, RAMS2 When all mute inputs are 0, mute is released. - CMP12 (12-bit comparison connection) When 1: Performs comparison connection using only the most significant 12 bits of input data. ina ry When 1: Outputs are instantaneously muted to 0.(note 1) Same effect as taking the YDMUTE pin HIGH. When 0 and 0 : 16M DRAM (4M×4 bits)×double When 1 and 0 : 4M DRAM (1M×4 bits)×single When 0: Performs comparison connection using all 16 bits of input data. - COMPFB, COMP6B, COMP5B, COMP4B When 0, 0, 0 and 1: Selects 4-bit compression mode When 0 and 1 : 4M DRAM (1M×4 bits)×double When 0, 0, 1 and 0: Selects 5-bit compression mode When 1 and 1 : 16M DRAM (4M×4 bits)×single - YFLGS, YFCKP When 1, 0, 0 and 0: Selects full-bit compression mode In all other cases: Selects 6-bit compression mode Changing mode without initializing during operation is possible. pre lim When 0 and 0: Sets FLAG6 on the falling edge of YFCLK when YFLAG=0 When 0 and 1: Sets FLAG6 on the rising edge of YFCLK when YFLAG=0 When 1 and 0: Sets FLAG6 when YFLAG=0 When 1 and 1: Sets FLAG6 when YFLAG=1 NIPPON PRECISION CIRCUITS-19 SM5907AF Shock-proof operation overview - Encode sequence 1. Input data from a signal processor IC is stored in internal buffers. 2. Encoder starts after a fixed number of data have been received. - Decode sequence 1. Reads compressed data stored in external buffer RAM at rate fs. 2. Decoder starts, using the predicting filter type and quantization levels used when encoded. - Compare-connect sequence troller command 80H. This mode comprises the following 3 sequences. ina ry Shock-proof mode is the mode that realizes shockproof operation using external DRAM. Shock-proof mode is invoked by setting MSON=H in microcon- 3. Outputs the result. 3. Compares data re-read from the CD with the processed final valid data stored in RAM (confirms its correctness). 4. As soon as the comparison detects conforming data, compare-connect sequence stops and encode sequence re-starts, connecting the data directly behind previous valid data. pre lim 1. Encoding immediately stops when either external buffer RAM overflows or when a CD read error occurs due to shock vibrations. 2. Then, using microcontroller command 80H, the compare-connect start command is executed and compare-connect sequence starts. 3. The encoder, after the most suitable predicting filter type and quantization steps have been determined, performs ADPCM encoding and then writes to external DRAM. NIPPON PRECISION CIRCUITS-20 SM5907AF RAM addresses The SM5907AF uses either 1 or 2 external 4M or 16M DRAMs as external buffers. Connect data work area Three kinds of addresses are used for external RAM control. WA (write address) RA (read address) VWA (valid write address) Among these, VWA is the write address for conforming data whose validity has been confirmed. Determination of the correctness of data read from the CD is delayed relative to the encode write processing, so VWA is always delayed relative to WA. ina ry RA WA VWA Valid data area The region available for valid data is the area between VWA-RA. - Connect data work area This is an area of memory reserved for connect data. This area is 4k bits if using 4M DRAMs or 8k bits if using 16M DRAMs. pre lim VWA (valid write address) Fig 1. RAM addresses The VWA is determined according to the YBLKCK pin and WAQV command. Refer to the timing chart below. 1.YBLKCK is a 75 Hz clock(HIGH for 136 µs) when used for normal read mode and it is a 150 Hz clock when used for double-speed read mode, synchronized to the CD format block end timing. When this clock goes LOW, WA which is the write address of internal encode sequence, is stored (see note 2). 2.The microcontroller checks the subcode and, if confirmed to be correct, generates a WAQV command (80H). 3.When the WAQV command is received, the previously latched WA is stored as the VWA. (note 2) Actually, there is a small time difference, or gap, between the input data and YBLKCK. This gap serves to preserves the preceding WA to protect against incorrect operation. 13.3ms VWA latch set YBLKCK Microcontroller data set WAQV set Refer to Microcontroller interface VWA VWA(x) VWA(x + 1) Values shown are for rate fs. The values are 1/2 those shown at rate 2fs. Fig 2. YBLKCK and VWA relationship NIPPON PRECISION CIRCUITS-21 SM5907AF YFLAG, YFCLK, FLAG6 85H command 1 YFLGS YFCKP FLAG6 set conditions FLAG6 reset conditions 0 0 When YFLAG=LOW on YFCLK input falling edge - By status read (90H command) 1 When YFLAG=LOW on YFCLK input rising edge - When MSON=LOW 2 3 4 encode sequence when such a disturbance has occurred, and then makes FLAG6 active. The YFLAG check method used changes depending on the YFLGS flag and YFCKP flag (85H command). See table1. If YFLAGS is set to 1, then YFCLK should be tied either High or Low. ina ry Correct data demodulation becomes impossible for the CD signal processor IC when a disturbance exceeding the RAM jitter margin occurs. The YFLAG signal input pin is used to indicate when such a condition has occurred. The YFCLK is a 7.35 kHz clock synchronized to the CD format frame 1. The IC checks the YFLAG input and stops the 1 0 When YFLAG=LOW 1 When YFLAG=HIGH YFCLK be tied either High or Low - After system reset pre lim Table 1. YFLAG signal check method NIPPON PRECISION CIRCUITS-22 SM5907AF Compare-connect sequence - Compare-connect preparation time sequence is re-started and data is written to VWA. In 2-pair compare-connect mode, comparison occurs just as for 3-pair comparison except that only 2 pairs from the three compared need to conform with the valid data. At this point, the encode sequence is re-started and data is written to VWA. In direct-connect mode, comparison is not performed at all, and encode sequence starts and data is written to the VWA. This mode is for systems that cannot perform compare-connect operation. ina ry The SM5907AF supports three kinds of connect modes; 3-pair compare-connect, 2-pair compareconnect and direct connect. Note that the SM5907AF can also operate in 12-bit comparison connect mode using only the most significant 12 bits of data for connection operation. In 3-pair compare-connect mode, the final 6 valid data (3 pairs of left- and right-channel data input before encode processing) and the most recently input data are compared until three continuous data pairs all conform. At this point, the encode 3. If the compare-connect command is issued again, the preparation time above is not necessary and operation starts from step 2. 4. The same sequence takes place in direct-connect mode also. However, at the point when 3 words have been input, all data is directly connected as if comparison and conformance had taken place. pre lim 1. Comparison data preparation time Internally, when the compare-connect start command is issued, a sequence starts to restore the data for comparison. The time required for this preparation after receiving the command is approximately 2.5 × (1/fs). (approximately 60 µs when fs = 44.1 kHz) 2. After the above preparation is finished, data is input beginning from the left-channel data and comparison starts. - Compare-connect sequence stop If a compare-connect stop command (80H with MSDCN1= 1, MSDCN2= 0) is input from the microcontroller, compare-connect sequence stops. If compare-connect sequence was not operating, the compare-connect stop command performs no operation. However, make sure that the other bit settings within the same 80H command are valid. NIPPON PRECISION CIRCUITS-23 SM5907AF Encode sequence temporary stop - But if the MSWREN is set HIGH (80H command) after using the compare-connect start command even only once, data is written to VWA. If data is input before comparison and conformance is detected, the same operation as direct-connect mode takes place when the command is issued. After comparison and conformance are detected, no operation is performed because the encode sequence has already been started. However, make sure that the other bit settings within the same 80H command are valid. ina ry - When RAM becomes full, MSWREN is set LOW using the 80H command and encode sequence stops. (For details of the stop conditions, refer to the description of the ENCOD flag.) - Then, if MSWREN is set HIGH without issuing a compare-connect start command, the encode sequence re-starts. At this time, new input data is written not to VWA, but to WA. In this way, the data already written to the region between VWA and WA is not lost. DRAM refresh A data access to DRAM can occur in an encode sequence write operation or in a decode sequence read operation. Write sequence write operation stops during a connect operation whereas a read sequence read operation always continues while data is output to the D/A. The refresh rate for each DRAM during decode sequence is shown in the table below. The decode sequence, set by MSON=1 and MSRDEN=1, operates when valid data is in DRAM (when MSEMP=0). - When MSON=0, DRAM is not refreshed because no data is being accessed. Although MSON=1, DRAM is not refreshed if ENCOD=0 and DECOD=0 (both encode and decode sequence are stopped). pre lim - DRAM initialization refresh A 15-cycle RAS-only refresh is carried out for DRAM initialization under the following conditions. When MSON changes from 0 to 1 using command 80H. When from MSON=1, MSRDEN=0 and MSWREN=0 states only MSWREN changes to 1. In this case, encode sequence immediately starts and initial data is written (at 2fs rate input) after a delay of 0.7ms. - Refresh during Shock-proof mode operation In this IC, a data access operation to any address also serves as a data refresh. Accordingly, there are no specific refresh cycles other than the initialization refresh cycle (described above). This has the resulting effect of saving on DRAM power dissipation. DRAMs used (same for 1 or 2 DRAMs) Data compression mode 4M (1M×4 bits) 16M(4M×4 bits) 4 bit 10.88 ms 21.77ms 5 bit 8.71 ms 17.42ms 6 bit 7.26 ms 14.52ms Full bit 2.72 ms 5.81ms Table 2. Decode sequence refresh rate NIPPON PRECISION CIRCUITS-24 SM5907AF Through-mode operation Force mute clock be at rate fs by the time jitter-free timing starts. The jitter margin is 0.2/ fs (80 clock cycles). This jitter margin is the allowable difference between the system clock (CLK) divided by 384 (fs rate clock) and the YLRCK input clock. If the timing difference exceeds the jitter margin, irregular operation like data being output twice or, conversely, incomplete data output may occur. In the worst case, a click noise may also be generated. When switching from shock-proof mode to through mode, an output noise may be generated, and it is therefore recommended to use the YDMUTE setting to mute ZSRDATA until just before data output. ina ry If MSON is set LOW (80H command), an operating mode that does not perform shock-proof functions becomes active. In this case, input data is passed as-is (except Force mute operation) to the output. External DRAM is not accessed. - In this case, input data needs to be at a rate fs and the input word clock must be synchronized to the CLK input (384fs). However, short-range jitter can be tolerated (jitter-free system). - Jitter-free system timing starts from the first YLRCK rising edge after either (A) a reset (NRESET= 0) release by taking the reset input from LOW to HIGH or (B) by taking MSON from HIGH to LOW. Accordingly, to provide for the largest possible jitter margin, it is necessary that the YLRCK When MSON is HIGH and valid data is empty (MSEMP=H), the output is automatically forced into the mute state. pre lim Serial output data is muted by setting the YDMUTE pin input HIGH or by setting the MUTE flag to 1. Mute starts and finishes on the leading left-channel bit. 12-bit comparison connection When the CMP12 flag is set to 1, the least significant 4 bits of the 16-bit comparison connection input data are discarded and comparison connection is performed using the remaining 12 bits. Note that if the CMP12 flag is set to 1 during a comparison connection operation, only the most significant 12 bits are used for comparison connection from that point on. NIPPON PRECISION CIRCUITS-25 SM5907AF Timing charts Input timing (YSCK, YSRDATA, YLRCK) YSCK 16 ina ry 16 L ch LSB MSB YLRCK LSB MSB LSB YSRDATA R ch 1/(3fs ) Output timing (ZSCK, ZSRDATA, ZLRCK) ZSCK 9 24 33 L ch R ch MSB LSB MSB ZLRCK LSB ZSRDATA 48 LSB lim 1 pre 1/fs NIPPON PRECISION CIRCUITS-26 SM5907AF DRAM write timing (NRAS, NCAS, NCAS2, NCAS3, NWE, A0 to A10, D0 to D3) Write timing (with single DRAM) NRAS t RADS A0 to A10 ;;;;;;;; ;;;;;;;; ;;;;;;;; ;;;;;;;; t CADS t RADH t CWDS t CASH t CASL t RDC NCAS t RASH ina ry t RASL t CADH ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; t CWDH ;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;; D0 to D3 (WRITE) t WEL NWE pre lim Write timing (with double DRAMs) t RASL t RASH NRAS t RDC t CASL t CASH t RDC t CASL t CASH NCAS1 (DRAM1 SELECT) NCAS2, NCAS3 (DRAM2 SELECT) A0 to A10 ;;;;;;; ;;;;;;; ;;;;;;; ;;;;;;; ;;;;;;; t RADS t RADH t CADS t CWDS t CWDH D0 to D3 (WRITE) t WEL t CADH ;;;;;;;;;;;;; ;;;;;;;; ;;;;;;;;;;;;; ;;;;;;;; ;;;;;;;;;;;;; ;;;;;;;; ;;;;;;;;;;;;; ;;;;;;;; ;;;;;;;;;;;;; ;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;; NWE NIPPON PRECISION CIRCUITS-27 SM5907AF DRAM read timing (NRAS, NCAS, NCAS2, NCAS3, NWE, A0 to A10, D0 to D3) Read timing (with single DRAM) NRAS t RCD NCAS ;;;;;;; ;;;;;;; A0 to A10 ;;;;;;; ;;;;;;; ;;;;;;; t RADS t RADH t RASH ina ry t RASL t CASL t CADS t CASH t CADH ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; D0 to D3 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (READ) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; t CRDS t CRDH ;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; t OEL NWE lim Read timing (with double DRAMs) t RASL NRAS NCAS1 (DRAM1 SELECT) NCAS2, NCAS3 (DRAM2 SELECT) t RADS t RADH D0 to D3 (READ) t RASH t RCD t CASL t CASH t RCD t CASL t CASH t CADS ;;;;;;; ;;;;;;; ;;;;;;; ;;;;;;; ;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; pre A0 to A10 ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; t CADH t CRDS t CRDH ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; NWE NIPPON PRECISION CIRCUITS-28 SM5907AF Connection example 4M DRAM × 1 or 2 typical connection SM5907 UC1 to UC5 ina ry Microcontroller YMDATA YMCLK YMLD ZSENSE 4M DRAM 1 YBLKCK YFCLK CD DSP YFLAG YSCK YLRCK YSRDATA NRAS NWE A0 to A9 D0 to D3 NCAS RAS WE A0 to A9 D0 to D3 CAS OE 4M DRAM 2 NRAS RAS NWE WE A0 to A9 A0 to A9 D0 to D3 D0 to D3 CAS OE NCAS2 D/A converter ZSCK ZLRCK ZSRDATA CLK NRESET YDMUTE pre lim 16M DRAM × 1 or 2 typical connection SM5907 Microcontroller YMDATA YMCLK YMLD ZSENSE UC1 to UC5 YBLKCK YFCLK CD DSP YFLAG YSCK YLRCK YSRDATA NRAS NWE A0 to A10 D0 to D3 NCAS 16M DRAM 1 RAS WE A0 to A10 D0 to D3 CAS OE 16M DRAM 2 NRAS RAS NWE WE A0 to A10 A0 to A10 D0 to D3 D0 to D3 CAS OE NCAS3 D/A converter ZSCK ZLRCK ZSRDATA CLK NRESET YDMUTE DRAM OE pin is tied LOW. In response to the YFLAG input, the 85H command (option settings) should be: D5: YFLGS =1, D4: YFCKP set to the YFLAG active level. If YFLAG is active LOW, set YFCKP=0. If YFLAG is active HIGH, set YFCKP=1. If 4M DRAM × 2 are used, use A10/NCAS2 pin. If 16M DRAM × 2 are used, use NCAS3 pin. NIPPON PRECISION CIRCUITS-29 SM5907AF Device comparison with SM5903BF SM5903BF SM5907AF 7 pin N.C. NCAS3 ina Pin No. ry Pin difference Microcontroller interface functions 85H (RAMS1=0, RAMS2=0) SM5903BF: 1M DRAM × 1 SM5907AF: 16M DRAM × 2 When 16M × 2 configuration is used, the microcontroller interface valid residual memory is different (92H status read). See "Read command summary". pre l im 92H (valid residual) In the SM5907AF, if 16M DRAM × 2 configuration is selected using the 85H command (85H RAMS1=0, RAMS2=0), the residual data is 1-bit shifted in order to represent the maximum 32Mbits. As pin 7 on the SM5903BF is not connected internally, the possible DRAM configurations are 4M × 1, 4M × 2, and 16M × 1, all of which are completely compatible with the SM5907AF. Note that the chip process is different, and hence some DC characteristics are different. NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS INC. 4-3, FUKUZUMI 2 CHOME, KOTO-KU TOKYO,135-8430, JAPAN Telephon: +81-3-3642-6661 Facsimile: +81-3-3642-6698 http://www.npc.co.jp/ Email: [email protected] NP0018AE 2000.10 NIPPON PRECISION CIRCUITS-30