SM8701BM DVD Player Clock Generator NIPPON PRECISION CIRCUITS INC. OVERVIEW The SM8701BM is a 27 MHz master clock, 5-system output clock generator for DVD players. It has 2 built-in PLLs that, with the addition of a single crystal oscillator element, can generate 256fs, 384fs and 768fs clocks plus independent fixed-frequency 27 MHz and 33.8688 MHz output clocks. Supported sampling frequencies (fs) include the standard 32, 44.1 or 48 kHz, or double-frequency 64, 88.2 or 96 kHz. FEATURES ■ ■ ■ ■ ■ ■ 27 MHz master clock (internal PLL reference clock) Generated clocks • 27 MHz output • 33.8688 MHz output • 256fs output • 384fs output • 768fs output Sampling frequency fs • 32/64 kHz • 44.1/88.2 kHz • 48/96 kHz Low jitter output 3-wire serial or parallel control Supply voltage: VDD = VDDP = 5.0V VDDO = VDD3 = 3.3V 20-pin SSOP package APPLICATIONS ■ (Top View) MLEN/R2 P/S VDD GND XTO XTI GNDP VDDP VDD3 MO 1 20 SM8 7 0 1B ■ PINOUT 10 11 MCK/R1 MDT/R0 RSTN SO3 VDDO GNDO SO2 SO4 SO1 MON PACKAGE DIMENSIONS DVD players (Unit: mm) ORDERING INFORMATION 0.6 0.15 1.30 0.10 0.62TYP 0.20 0.05 7.90 0.20 20-pin SSOP 5.30 0.05 SM8701BM 7.40MAX 7.20 0.05 1.80 0.10 0.10 0.10 P ackag e 2.10MAX D e vice 0 to 8 0.65 0.68 0.12 0.10 0.30 0.10 0.13 M NIPPON PRECISION CIRCUITS—1 SM8701BM BLOCK DIAGRAM Divider0 XTI Phase Comparator0 Charge Pump0 LPF0 VCO0 Oscillator SO4 XTO Divider0 SO3 P/S MLEN/R2 MDT/R0 Divider SO2 External Interface SO1 MCK/R1 Divider1 Phase Comparator1 Charge Pump1 LPF1 VCO1 Divider1 MO MON RSTN Reset Circuits NIPPON PRECISION CIRCUITS—2 SM8701BM PIN DESCRIPTION Number Name I/O Description 1 MLEN/R2 Ip 1 Control signal input. In serial mode: latch enable signal In parallel mode: sampling rate select signal 2 P/S Ip 1 Mode select signal. L O W : serial mode, HIGH: parallel mode 3 VDD – 5 V supply (Digital block) 4 GND – Ground (Digital block) 5 X TO O Reference signal crystal oscillator element connection 6 XTI I Reference signal crystal oscillator element connection or external clock input 7 GNDP – Ground (PLL block) 8 VDDP – 5 V supply (PLL block) 9 VDD3 – 3.3 V supply (output buffer) 10 MO O 27 MHz fixed-frequency output 11 MON O 27 MHz fixed-frequency output (inverted) 12 SO1 O 33.8688 MHz fixed-frequency output 13 SO4 O 768fs output 14 SO2 O 256fs output 15 GNDO – Ground (output buffer) 16 VDDO – 3.3 V supply (output buffer) 17 SO3 O 384fs output 18 RSTN Ip 2 L O W -level reset input 19 MDT/R0 Ip 1 Control signal input. In serial mode: control data input signal In parallel mode: sampling frequency select signal 20 MCK/R1 Ip 1 Control signal input. In serial mode: clock signal In parallel mode: sampling frequency select signal 1. Schmitt trigger input with pull-down resistor 2. Schmitt trigger input with pull-up resistor NIPPON PRECISION CIRCUITS—3 SM8701BM SPECIFICATIONS Absolute Maximum Ratings P arameter Supply voltage range Supply voltage deviation Input voltage range Output voltage range Symbol Condition Rating Unit V DD , V DDP , V DDO , V DD3 −0.3 to 6.5 V VDD – VDDP , VDDO – VDD3 , G N D – G N D P, GND – G N D O, GNDP – G N D O ±0.1 V V IN Digital inputs −0.3 to V D D + 0.3 V VOUT Digital outputs −0.3 to V D D O , V D D 3 + 0.3 V Pow er dissipation PD 300 mW Storage temperature range T stg −55 to 125 °C Rating Unit V DDO , V DD3 2.7 to 3.6 V V DD , V D D P 4.5 to 5.5 V T opr −40 to 85 °C Recommended Operating Conditions P arameter Supply voltage ranges Operating temperature range Symbol Condition NIPPON PRECISION CIRCUITS—4 SM8701BM DC Electrical Characteristics External clock, Ta = −40 to 85 °C, VDD = VDDP = 4.5 to 5.5 V, VDDO = VDD3 = 2.7 to 3.6 V unless otherwise stated Rating P arameter Symbol Condition Unit min typ max – 32 45 mA Current consumption ID D All supplies. V D D = V D D P = 5.0V, V D D O = V D D 3 = 3.3 V, T a = 25 °C , fs = 48 kHz, using XTI external 27 M H z master clock, no load on clock outputs (MO, M O N , SO1 to SO4) HIGH-level input voltage V IH1 P/S, MLEN/R2, MCK/R1, MDT/R0, RSTN 2.0 – – V L O W -level input voltage V IL1 P/S, MLEN/R2, MCK/R1, MDT/R0, RSTN – – 0.8 V HIGH-level input voltage V IH2 XTI 0.7 × V D D – – V L O W -level input voltage V IL2 XTI – – 0.3 × V D D V HIGH-level input current 1 IIH1 V IN = V D D – – 150 µA L O W -level input current 1 IIL1 V IN = 0 V – – −1 µA HIGH-level input current 2 IIH2 V IN = V D D – – 1 µA L O W -level input current 2 IIL2 V IN = 0 V – – −150 µA HIGH-level input current IIH3 XTI, V IN = V D D – – 40 µA L O W -level input current IIL3 XTI, V IN = 0 V – – −40 µA HIGH-level output voltage VOH All outputs. IO H = −2 m A V D D O − 0.4 – – V L O W -level output voltage VOL All outputs. IO L = 4 mA – – 0.4 V 1. P/S, MLEN/R2, MCK/R1, MDT/R0. Schmitt trigger input, internal pull-down. 2. R S T N . Schmitt trigger input, internal pull-up. NIPPON PRECISION CIRCUITS—5 SM8701BM PLL AC Electrical Characteristics External clock, Ta = −40 to 85 °C, VDD = VDDP = 4.5 to 5.5 V, VDDO = VDD3 = 2.7 to 3.6 V unless otherwise stated Rating P arameter Symbol Condition Unit min typ max XTI external input clock frequency fM D U T Y: 50 ± 5% – 27.0000 – MHz Output clock rise time tR All outputs, 0.2 to 0.8V D D O or V D D 3 , C L = 20 p F – 2.5 – ns Output clock fall time tF All outputs, 0.8 to 0.2V D D O or V D D 3 , C L = 20 p F – 2.5 – ns – 150 – ps – 150 – ps – 450 – ps Cr ystal oscillator element, C L = 20 p F 45 50 55 % C L = 20 p F 40 50 60 % C L = 20 p F 23.3 33.3 43.3 % M O , M O N output clock jitter1 SO1, SO2 (Standard), SO3, SO4 output clock jitter1 JITTER Standard tolerance Cr ystal oscillator element SO2 (Double) output clock jitter1 M O , M O N output clock duty 1 SO1, SO2 (Standard), SO3, SO4 output clock duty 1 DUTY SO2 (Double) output clock duty 1 Settling time tS All outputs – – 40 ms Pow er-up time 2 tP All outputs – – 50 ms 100 – – ns R S T N external reset LOW -level pulsewidth tR S T L 1.4 V to 1.4 V 1. 1.4V to 1.4V. Ta = 2 0 °C . The characteristics of output clock jitter and output clock duty depends on crystal oscillator. N P C ’s standard crystal oscillator: R = 10.5 Ω, L = 5.38 mH, Ca = 6.74 fF, Cb = 1.85 p F measurement apparatus: HP4195 Load capacitance: C1 = 7 p F, C2 = 11 p F Cb L Ca R 2. Time from OFF condition to stable frequency output. NIPPON PRECISION CIRCUITS—6 SM8701BM Serial Interface AC Characteristics External clock, Ta = −40 to 85 °C, VDD = VDDP = 4.5 to 5.5 V, VDDO = VDD3 = 2.7 to 3.6 V unless otherwise stated Rating P arameter Symbol Condition Unit min typ max MCK HIGH-level pulsewidth tM C W H 40 – – ns M C K L O W -level pulsewidth tM C W L 40 – – ns MCK pulse cycle time tM C Y 100 – – ns MDT setup time tM D S 40 – – ns MDT hold time tM D H 40 – – ns MLEN setup time 1 tM L S 40 – – ns time 2 tM L H 40 – – ns MLEN HIGH-level pulsewidth tM H H 200 – – ns M L E N L OW -level pulsewidth tM L L 16 × tM C Y – – ns MLEN hold 1. Time from the MLEN falling edge to the next MCK rising edge. If the MCK clock stops after the LSB, the MLEN rise timing is optional. 2. Time from MCK rising edge corresponding to the LSB to the MLEN rising edge. tMCWH tMCWL tMLH tMLS MCK 1.4V tMCY MDT MSB LSB tMLS tMDS tMDH tMLL 1.4V tMHH MLEN 1.4V NIPPON PRECISION CIRCUITS—7 SM8701BM FUNCTIONAL DESCRIPTION 27 MHz Master Clock The 27 MHz master clock is generated either by connecting a crystal oscillator element between XTI (pin 6) and XTO (pin 5), as shown in figure 1, or by connecting an external 27 MHz clock to XTI, as shown C2 in figure 2. Input 27MHz master clock on XTI when using an external clock. Crystal oscillator element must be fundamental. XTO (Pin5) Internal Circuits Oscillator XTI (Pin6) C1 MO (Pin10) C1, C2 = 5 to 33pF MON (Pin11) SM8701BM Figure 1. Crystal oscillator connection Open XTO (Pin5) Oscillator External Clock Internal Circuits XTI (Pin6) MO (Pin10) MON (Pin11) SM8701BM Figure 2. External clock input NIPPON PRECISION CIRCUITS—8 SM8701BM Sampling Frequency and Output Clock Frequency The SM8701BM generates several output clocks from the 27 MHz master clock, with frequencies of 256fs (SO2), 384fs (SO3) and 768fs (SO4), where fs is the sampling frequency selected by external con- trol inputs. SO1 outputs 33.8688 MHz clock. The supported sampling frequencies and the output clock frequencies are shown in table 1. Table 1. Sampling frequency and output clock frequency Sampling rate Standard D o u ble Output clock frequency (MHz) Sampling frequency fs SO1 SO2 SO3 SO4 32 kHz 33.8688 8.192 12.288 24.576 44.1 kHz 33.8688 11.2896 16.9344 33.8688 48 kHz 33.8688 12.288 18.432 36.864 64 kHz 33.8688 16.384 24.576 24.576 88.2 kHz 33.8688 22.5792 33.8688 33.8688 96 kHz 33.8688 24.576 36.864 36.864 Reset The SM8701BM supports an external reset using RSTN (pin 18). At reset, the mode register takes its default value, and the output clocks have default frequencies. When RSTN goes HIGH, an internal reset continues for a period of 1024 cycles of the 27 MHz master clock. The timing is shown in figure 3. RSTN Reset Internal Reset 1 2 3 1024 Master Clock 1024 Master Clock Figure 3. External reset timing NIPPON PRECISION CIRCUITS—9 SM8701BM Operation Control The SM8701BM functions are controlled by inputs MLEN/R2 (pin 1), MDT/R0 (pin 19) and MCK/R1 (pin 20). The operating mode is selected by input P/S (pin 2)—serial control when P/S is LOW, and parallel control when P/S is HIGH. Table 2 shows the relationship between functions and mode. Table 2. Control functions Controllable Function Serial P arallel Sampling frequency group: 48/44.1/32 kHz Yes Yes Sampling rate: standard/double Yes Yes Clock output: enable/disable Yes No Serial control (P/S = LOW) When P/S is LOW, the control interface is serial control mode. The serial control data is set by 16-bit MDT data in sync with the MCK clock and the MLEN enable signal clock at the serial control mode. The format is shown in figure 4. MCK MDT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MLEN Figure 4. Serial control format The 16-bit mode register (MREG) is shown in figure 5, and the name and function of each bit is described in tables 3 to 5. In serial control mode, mode register MREG bits D15 to D10 must be set to 011100. D3 is fixed as LOW. 0 1 1 1 0 0 CE6 CE5 CE4 CE3 CE2 CE1 RSV R2 R1 R0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Note: RSV is fixed as LOW . Figure 5. Mode register Table 3. Mode register control bit functions Function Table 4. CE6 to CE1 clock output control setting Bit Name CE6 to CE1 Clock output D9 CE6 M O N output enable/disable LOW Disable (LOW -level output) D8 CE5 MO output enable/disable HIGH E n a ble (default) D7 CE4 SO4 output enable/disable D6 CE3 SO3 output enable/disable D5 CE2 SO2 output enable/disable D4 CE1 SO1 output enable/disable D3 RSV Fixed as LOW D2/D1/D0 R2/R1/R0 Sampling frequency select NIPPON PRECISION CIRCUITS—10 SM8701BM Table 5. Sampling frequency select (R2, R1, R0) R2 R1 R0 Sampling rate Sampling frequency gro u p Sampling frequency LOW LOW LOW Standard 48 kHz 48 kHz (default) LOW LOW HIGH Standard 44.1 kHz 44.1 kHz LOW HIGH LOW Standard 32 kHz 32 kHz LOW HIGH HIGH HIGH LOW LOW D o u ble 48 kHz 96 kHz HIGH LOW HIGH D o u ble 44.1 kHz 88.2 kHz HIGH HIGH LOW D o u ble 32 kHz 64 kHz HIGH HIGH HIGH Prohibited (test mode) Prohibited (test mode) When the sampling frequency is changed, a settling time of 40 ms (max) is required to make the output frequency stable. The SO2 to SO4 output response MLEN SO2 to 4 SO1 when the frequency is changed is shown in figure 6. SO1 fixed on 33.8688 MHz. tS Clock Transition Region 33.8688MHz Figure 6. System clock transient timing NIPPON PRECISION CIRCUITS—11 SM8701BM Parallel control (P/S = HIGH) When P/S is HIGH, the control interface is parallel control mode. The parallel control pins R2 (pin 1), R1 (pin 20) and R0 (pin 19) and functions are shown in table 6. Table 6. Sampling frequency select (R2, R1, R0) R2 R1 R0 Sampling rate Sampling frequency gro u p Sampling frequency LOW LOW LOW Standard 48 kHz 48 kHz (default) LOW LOW HIGH Standard 44.1 kHz 44.1 kHz LOW HIGH LOW Standard 32 kHz 32 kHz LOW HIGH HIGH HIGH LOW LOW D o u ble 48 kHz 96 kHz HIGH LOW HIGH D o u ble 44.1 kHz 88.2 kHz HIGH HIGH LOW D o u ble 32 kHz 64 kHz HIGH HIGH HIGH Prohibited (test mode) Note that in parallel control mode, clock output enable/disable controls are not available. Also note that the reset function does not affect the sampling Prohibited (test mode) frequency group or sampling rate select settings (it is determined by R2, R1, R0 condition). NIPPON PRECISION CIRCUITS—12 SM8701BM TYPICAL APPLICATION CPU +3.3V +5V MLEN/R2 MCK/R1 P/S MDT/R0 VDD RSTN GND SO3 XTO VDDO C3 C1 384fs 256fs C6 X'tal XTI GNDO 768fs C2 GNDP SO2 VDDP SO4 VDD3 SO1 C4 33.8688MHz C5 MO MON 27MHz(Inverted) SM8701BM 27MHz ■ ■ ■ ■ Connect the decoupling capacitors (approximately 0.1µF and 1000pF) in parallel, as close to power supply pins as possible. In order to minimize noise, it is useful to make ground as solid pattern. Master clock stability affects the other outputs stability. In the usage of crystal oscillator, load capacitor and crystal oscillator should be placed as close to the SM8701BM as possible, and wired shortly. Select crystal oscillators and load capacitance carefully, depending on the condition, as those combination will have influence on the frequency accuracy(C1, C2). Supply pattern including decoupling capacitors needs careful attention to make the IC’s performance better, since the SM8701BM outputs several high frequency clocks. Pattern capacitance from output pins should not to be large for prevention of the noise. Connecting output pins to buffers is useful if it is necessary. ■ Power supply and ground pins. • VDD :5V Power supply for digital block (CPU I/F*, XT1, XT2). • GND : Ground for digital block (CPU I/F*, XT1, XT2, output block except SO3). • VDDP :5V Power supply for PLL block. • GNDP : Ground for PLL block. • VDDO :3.3V Power supply for SO3. • GNDO : Ground for SO3. • VDD3 :3.3V Power supply for output block (except SO3). *: CPU I/F: MDT/R0, MCK/R1, MLEN/R2, RSTN, P/S NIPPON PRECISION CIRCUITS—13 SM8701BM NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility fo r the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with expor t controls on the distribution or dissemination of the products. Customers shall not expor t, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9822BE 2000.1 NIPPON PRECISION CIRCUITS—14