NTE1254 Integrated Circuit Phase–Lock Loop (PLL) Frequency Synthesizer for CB Features: D Programmable Divider – Divided by 3 to 255 D 10–Bit Divider D Phase Detector D Reference Oscillation Circuit D On–Chip Filter Amplifier D Code Converter D Only two or three crystals required for CB radio AM frequency selection D Unlocked signals are detected at instant stop “IS” terminal D Two type program mode can be selected to change input mode level M: Low level . Binary code input enables, divided by 3 to 255 M: High level . BCD code enables that the data at P1 to P6 port is offset 90 by code converter D Internal active filter amplifier has a long holding time due to very high input impedance characteristics of the CMOS–this is to obtain very good spurious response. D Output signal of the “I” can be used to stop the spurious radiation when the channel selector makes misprogramming such as rotary switch’s lose contact. D High speed and low power consumption due to CMOS D Single power supply and fully TTL compatible: VDD = 5 ± 0.5 Volts D Operating Temperature: TA = –30° to 65°C D Pull down resistors installed in program and mode switch inputs Absolute Maximum Ratings: Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to +6.0V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to +6.0V Operating Temperature Range, Topr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –35° to +75°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55° to +125°C Electrical Characteristics: (TA = – 35° to +75°C unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit 4.5 5.0 5.5 V – – 10 mA Power Supply VDD Total Current IDD f=0 High Level Input Voltage VIH All Inputs 0.8VDD – VDD V Low Level Input Voltage VIL All Inputs –0.3 – 0.2VDD V High Level Output Voltage VOH All Outputs Except D2, IO = –0.3mA, VDD = 4.5V 0.85VDD – VDD V IO = –0.15mA, VDD = 4.5V 0.85VDD – VDD V –0.3 – 0.15VDD V Low Level Output Voltage VOL All Inputs, IO = 0.5mA, VDD = 4.5V Leakage Current IL EO (Floating), Al TA = +25°C – 1.0 – nA Input Capacitance Ci PI, FD, FP, X1, Vi = 0 – – 10 pF fdmax X1 – X2, Divider 11 – – MHz fpmax Programmable Divider – 2 – MHz Maximum Frequency Response Pin Connection Diagram Program Input P1 1 24 Inhibit Output Program Input P2 2 Program Input P3 3 23 VSS 22 Instant Stop Program Input P4 4 21 Phase Error Output Program Input P5 5 20 Filter Amp Input Program Input P6 Program Input P7 6 19 Filter Amp Output 7 18 Detector Input Program Input P8 8 17 Divider Output 1/2 Output Reference 9 16 Detector Input X’tal Input 10 15 Divider Output X’tal Input 11 VDD 12 14 Input Mode Switch 13 Divider Input 24 13 1 12 1.300 (33.02) Max .520 (13.2) .225 (5.73) Max .100 (2.54) 1.100 (27.94) .126 (3.22) Min .600 (15.24)