NTE1853 Integrated Circuit Digital Filter for Compact Disc Digital Audio System Features: D 16–Bit Serial Data Input (Two’s Complement) D Interpolated Data Replaces Erroneous Data Samples D –12dB Attenuation via the Active Low Attenuation Input Control (ATSB) D Smoothed Trasitions Before and After Muting D Two Identical Finite Impulse Response Transversal Filters each with a Sampling Rate of Four Times that of the Normal Digital Audio Data D Digital Audio Output of 32–Bit Words Transmitted in Biphasemark Code Applications: D Compact Disc Digital Audio System D Digital Filter Absolute Maximum Ratings: Supply Voltage Range (Pin24), VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5V to +7.0V Maximum Input Voltage Range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5V to VDD+0.5V Electrostatic Handling (Note 2), VES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1000V to +1000V Operating Ambient Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20° to +70°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65° to +150°C Note 1. All outputs are short–circuit protected except the crystal oscillator output. Note 2. Equivalent to discharging a 100pF capacitor through a 1.5Ω series resistor with a rise time of 15ns. DC and AC Electrical Characteristics: (VDD = 4.5 to 5.5V, VSS = 0, TA = –20° to +70°C unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Supply Voltage (Pin24) VDD 4.5 5.0 5.5 V Supply Current (Pin24) IDD – 180 – mA DC and AC Electrical Characteristics (Cont’d): (VDD = 4.5 to 5.5V, VSS = 0, TA = –20° to +70°C unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit WSAB, DAAB Input Voltage, Low VIL –0.3 – +0.8 V Input Voltage, High VIH 2.0 – VDD+0.5 V Input Leakage Current ILI –10 – +10 µA Input Capacitance CI – – 7 pF Input Voltage, Low VIL –0.3 – +0.8 V Input Voltage, High VIH 2.0 – VDD+0.5 V Input Leakage Current ILI VI = 0V –10 – – µA VI = VDD – – +50 µA CI – – 7 pF Input Voltage, Low VIL –0.3 – +0.8 V Input Voltage, High VIH 2.0 – VDD+0.5 V Input Leakage Current ILI VI = 0V –30 – – µA VI = VDD – – +10 µA CI – – 7 pF Mutual Conductance at 100kHz GM 1.5 – – mA/V Small–Signal Voltage Gain AV 3.5 – – V/V Input Capacitance CI – – 10 pF Feedback Capacitance CFB – – 5 pF Output Capacitance CO – – 10 pF Input Leakage Current ILI –10 0 +10 µA EFAB, SDAB (Note 1) Input Capacitance CLAB, SCAB, ATSB, MUSB (Note 2) Input Capacitance Output XOUT AV = GM x RO Slave Clock Mode Input Voltage (Peak to Peak) VI(P–P) Note 3 3.0 – VDD+0.5 V Input Voltage, Low VIL Note 3 0 – 1 V Input Voltage, High VIH Note 3 3.0 – VDD+0.5 V Input Rise Time tR Note 4 – – 20 ns Input Fall Time tF Note 4 – – 20 ns 35 – 65 % Input High Time at 2V (Relative to Clock Period) tHIGH Note 1. Inputs EFAB and SDAB both have internal pull–downs. Note 2. Inputs CLAB, SCAB, ATSB, and MUSB have internal pull–ups. Note 3. The minimum peak–to–peak voltage can be reduced to 2V if the output XSYS is not being used. Similarly VIH can be reduced to 2.4V (Min). All other levels remain the same. Note 4. Reference levels = 10% and 90%. DC and AC Electrical Characteristics (Cont’d): (VDD = 4.5 to 5.5V, VSS = 0, TA = –20° to +70°C unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit 0 – 0.4 V 2.4 – VDD V CL – – 50 pF Output Voltage, Low VOL 0 – 0.4 V Output Voltage, High VOH 2.4 – VDD V CL – – 50 pF VL(P–P) 0.4 – 0.6 V DABD, CLBD, WSBD Output Voltage, Low VOL IOL = 1.6mA Output Voltage, High VOH –IOH = 0.2mA Load Capacitance XSYS (Note 5) Load Capacitance DOBM Voltage Across a 75Ω Load via Attenuator (Peak–to–Peak) Note 5. The output current conditions are dependent on the drive conditions. When a crystal oscillator is being used, the output current capability is IOL = +1.6mA; IOH = –0.2mA. But if a slave input is being used, the output currents are reduced to IOL = +0.2mA; IOH = –0.2mA. Timing Characteristics: Parameter Min Typ Max Unit fXTAL 10.16 11.2896 12.42 MHz SCAB Clock Frequency (Burst Clock) fSCAB – 2.8224 – MHz CLAB Clock Frequency fCLAB – 2.8224 – MHz – 1.4112 – MHz Operating Frequency (XTAL) Symbol Test Conditions Inputs SCAB, CLAB (Note 6) Note 7 Clock Low Time tCKL 110 – – ns Clock High Time tCKH 110 – – ns Input Rise Time tR – – 20 ns Input Fall Time tF – – 20 ns Data Setup Time tSU, tDAT 40 – – ns Data Hold Time tHD, tDAT 0 – – ns Input Rise Time tR – – 20 ns Input Fall Time tF – – 20 ns DAAB, WSAB, EFAB (Note 8) Note 6. Reference levels = 0.8V and 2.0V Note 7. The signal CLAB can run at either 2.8MHz (1/4 system clock) or 1.4MHz (1/8 system clock) under typical conditions. It does not have a minimum or maximum frequency, but is limited to being 1/4 or 1/8 of the system clock frequency. Note 8. Input setup and hold times measured with respect to clock input from A–chip (CLAB). Reference levels = 0.8V and 2.0V. Timing Characteristics (Cont’d): Parameter Symbol Test Conditions Min Typ Max Unit SDAB (Note 9) Subcode Data Setup Time tSU, tSDAT 40 – – ns Subcode Data Hold Time tHD, tSDAT 0 – – ns Input Rise Time tR – – 20 ns Input Fall Time tF – – 20 ns Word Select Setup Time tSU, tWS 40 – – ns Word Select Hold Time tHD, tWS 0 – – ns Output Rise Time tR – – 20 ns Output Fall Time tF – – 20 ns Data Setup Time tSU, tDATD 40 – – ns Data Hold Time tHD, tDATD 0 – – ns Output Rise Time tR – – 20 ns Output Fall Time tF – – 20 ns Clock Period tCK 161 177 197 ns Clock Low Time tCKL 65 – – ns Clock High Time tCKH 65 – – ns Clock Setup Time tSU, tCLD 40 – – ns Clock Hold Time tHD, tCLD 0 – – ns Output Rise Time tR – – 20 ns Output Fall Time tF – – 20 ns Data Setup Time tSU, tDATBD 40 – – ns Data Hold Time tHD, tDATBD 60 – – ns Outputs WSBD (Note 6 & Note 10) WSBD (Note 6) DABD (Note 6 & Note 10) Outputs (Cont’d) DABD (Note 6) CLBD (Note 6 & Note 10) CLBD (Note 6) DABD (Note 6 & Note 11) Note 6. Reference levels = 0.8V and 2.0V Note 7. The signal CLAB can run at either 2.8MHz (1/4 system clock) or 1.4MHz (1/8 system clock) under typical conditions. It does not have a minimum or maximum frequency, but is limited to being 1/4 or 1/8 of the system clock frequency. Note 8. Input setup and hold times measured with respect to clock input from A–chip (CLAB). Reference levels = 0.8V and 2.0V. Note 9. Input setup and hold times measured with respect to subcode burst clock input from A–chip (SCAB). Reference levels = 0.8V and 2.0V. Note10. Output setup and hold times measured with respect to system clock output (XSYS). Note 11. Output setup and hold times measured with respect to clock output (CLBD). Timing Characteristics (Cont’d): Parameter Symbol Test Conditions Min Typ Max Unit tSU, tDATWSD tSU, tDATWSD 40 – – ns 60 – – ns Output Rise Time tR – – 20 ns Output Fall Time tF – – 20 ns Data Bit 0 Pulse Width High tHIGH(0) – 354 – ns Data Bit 0 Pulse Width Low tLOW(0) – 354 – ns Data Bit 1 Pulse Width High tHIGH(1) – 177 – ns Data Bit 1 Pulse Width Low tLOW(1) – 177 – ns WSBD (Note 6 & Note 11) Word Select Setup Time Word Select Hold Time DOBM (Note 12) XSYS Output Rise Time tR Note 6 – – 20 ns Output Fall Time tF Note 6 – – 20 ns 35 – 65 % Output High Time at 2V (Relative to Clock Period) tHIGH Note 6. Reference levels = 0.8V and 2.0V Note 11. Output setup and hold times measured with respect to clock output (CLBD). Note12. Output rise and fall times measured between the 10% and 90% levels; the data bit pulse width measured at the 50% level. Pin Connection Diagram WSAB 1 24 VDD 23 MUSB CLAB 2 DAAB 3 EFAB 4 22 ATSB 21 N.C. N.C. 5 20 N.C. SCAB 6 SDAB 7 19 N.C. N.C. 8 17 N.C. XSYS 9 XOUT 10 16 CLBD 15 DABD XIN 11 VSS 12 14 DOBM 13 TEST 18 WSDB 24 13 1 12 1.300 (33.02) Max .520 (13.2) .225 (5.73) Max .100 (2.54) 1.100 (27.94) .600 (15.24) .126