TI TMS416400ADJ

TMS416400A, TMS417400A
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
D
D
D
D
D
D
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D
D
This data sheet is applicable to all
TMS41x400As symbolized by Revision “B”,
Revision “E” and subsequent revisions as
described in the device symbolization section.
Organization . . . 4 194304 × 4
Single 5-V Power Supply (±10% Tolerance)
2 048-Cycle Refresh in 32 ms for
TMS417400A
4 096-Cycle Refresh in 64 ms for
TMS416400A
Performance Ranges:
’41x400A-50
’41x400A-60
’41x400A-70
ACCESS ACCESS ACCESS READ OR
TIME
TIME
TIME
WRITE
tRAC
tCAC
tAA
CYCLE
MAX
MAX
MAX
MIN
50 ns
13 ns
25 ns
90 ns
60 ns
15 ns
30 ns
110 ns
70 ns
18 ns
35 ns
130 ns
Enhanced Page-Mode Operation With
CAS-Before-RAS ( CBR) Refresh
3-State Unlatched Output
Low Power Dissipation
High-Reliability Plastic 24 / 26-Lead
300-Mil-Wide Surface-Mount Small-Outline
J-Lead (SOJ) Package (DJ Suffix)
Ambient Temperature Range:
0°C to 70°C
DJ PACKAGE
( TOP VIEW )
VCC
DQ1
DQ2
W
RAS
A11†
1
2
3
4
5
26
25
24
23
22
6
21
A10
A0
A1
A2
A3
VCC
8
19
9
10
11
12
13
18
17
16
15
14
VSS
DQ4
DQ3
CAS
OE
A9
A8
A7
A6
A5
A4
VSS
PIN NOMENCLATURE
A[0: 11]†
CAS
DQ[1:4]
OE
NC
RAS
VCC
VSS
W
Address Inputs
Column-Address Strobe
Data In / Data Out
Output Enable
No Internal Connection
Row-Address Strobe
5-V Supply
Ground
Write Enable
† A11 is NC for TMS417400A
description
The TMS41x400A is a set of 16 777 216-bit dynamic random-access memory (DRAMs) devices organized as
4 194 304 words of 4 bits each. The TMS41x400A employs state-of-the-art technology for high performance,
reliability, and low power.
These devices feature maximum RAS access times of 50-, 60-, and 70 ns. All address and data-in lines are
latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The TMS416400A and TMS417400A are offered in a 24 / 26-lead plastic surface-mount SOJ package
(DJ suffix). This package is designed for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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DYNAMIC RANDOM-ACCESS MEMORIES
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logic symbol (TMS416400A)†
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
RAS
CAS
W
OE
DQ1
DQ2
DQ3
DQ4
9
10
11
12
RAM 4096 K × 4
20D10/21D0
15
16
17
18
19
21
8
6
5
23
4
22
2
3
24
25
A
0
4 194 303
20D19/21D9
20D20
20D21
C20 [ROW]
G23/[REFRESH ROW]
24 [PWR DWN]
C21[COLUMN]
G24
&
23,21D
G25
23C22
24,25 EN
A,22D
26
A,Z26
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12.
2
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TMS416400A, TMS417400A
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
logic symbol (TMS417400A)†
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
RAS
CAS
W
OE
DQ1
DQ2
DQ3
DQ4
9
10
11
12
RAM 4096 K × 4
20D11/21D0
15
16
17
18
A
0
4 194 303
19
21
8
5
23
4
22
2
3
24
25
20D21/21D10
C20 [ROW]
G23/[REFRESH ROW]
24 [PWR DWN]
C21[COLUMN]
G24
&
23,21D
G25
23C22
24,25 EN
A,22D
26
A,Z26
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12.
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TMS416400A, TMS417400A
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
functional block diagram
TMS416400A
RAS
CAS
W
OE
Timing and Control
A0
A1
10
Column Decode
Sense Amplifiers
ColumnAddress
Buffers†
R
o
w
A11
RowAddress
Buffers
DataIn
Reg.
256K Array
4
D
e
c
o
d
e
12
4
256K Array
I/O
Buffers
64
4
4
DataOut
Reg.
256K Array
DQ1 – DQ4
12
† Column addresses A10 and A11 are not used.
TMS417400A
RAS
CAS
W
OE
Timing and Control
A0
A1
11
Column Decode
Sense Amplifiers
ColumnAddress
Buffers
256K Array R
256K Array o
w
A10
32
RowAddress
Buffers
11
4
256K Array
D
e
c
o
d
256K Array e 256K Array
4
32
11
4
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DataIn
Reg.
256K Array
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I/O
Buffers
4
4
DataOut
Reg.
DQ1 – DQ4
TMS416400A, TMS417400A
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
operation
enhanced page mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The
maximum number of columns that can be accessed is determined by tRASP, the maximum RAS low time.
Unlike conventional page-mode DRAMs, the column-address buffers in these devices are activated on the
falling edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge
of CAS latches the column addresses and enables the output. This feature allows the devices to operate at a
higher data bandwidth than conventional page-mode devices because data retrieval begins as soon as the
column address is valid rather than when CAS transitions low. This performance improvement is referred to as
enhanced-page mode. A valid column address can be presented immediately after row-address hold time has
been satisfied, usually well in advance of the falling edge of CAS. In this case, data is obtained after tCAC max
(access time from CAS low) if tAA max (access time from column address) and tRAC have been satisfied. In the
event that column address for the next cycle is valid at the time CAS goes high, access time for the next cycle
is determined by the later occurrence of tCPA or tCAC.
address: A0 – A11 ( TMS416400A) and A0 – A10 (TMS417400A)
Twenty-two address bits are required to decode each of the 4 194 304 storage cell locations. For the
TMS416400A, 12 row-address bits are set up on A0 through A11 and latched onto the chip by the row-address
strobe (RAS). Ten column-address bits are set up on A0 through A9. For TMS417400A, 11 row-address bits
are set up on inputs A0 through A10 and latched onto the chip by RAS. Eleven column-address bits are set up
on A0 through A10. All addresses must be stable on or before the falling edge of RAS and CAS. RAS is similar
to a chip enable because it activates the sense amplifiers as well as the row decoder. CAS is used as a chip
select, activating the output buffers and latching the address bits into the column-address buffers.
write enable ( W)
The read- or write mode is selected through W. A logic high on W selects the read mode, and a logic low selects
the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to CAS
(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with
OE grounded.
data in (DQ1 – DQ4)
Data is written during a write- or read-modify-write cycle. Depending on the mode of operation, the falling edge
of CAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to CAS, and
the data is strobed in by CAS with setup-and-hold times referenced to this signal. In a delayed-write- or
read-modify-write cycle, CAS is already low, and the data is strobed in by W with the setup-and-hold time
referenced to this signal. Also, OE must be high to bring the output buffers to the high-impedance state prior
to impressing data on the I/O lines.
data out (DQ1 – DQ4)
Data out is the same polarity as data in. The output is in the high-impedance (floating) state until CAS and OE
are brought low. In a read cycle, the output becomes valid after the access-time interval tCAC (which begins with
the negative transition of CAS) as long as tRAC and tAA are satisfied.
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DYNAMIC RANDOM-ACCESS MEMORIES
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RAS-only refresh
TMS416400A
A refresh operation must be performed at least once every 64 ms to retain data. This can be achieved by strobing
each of the 4 096 rows (A0 – A11). A normal read- or write cycle refreshes all bits in each row that is selected.
A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output
buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only
refresh.
TMS417400A
A refresh operation must be performed at least once every 32 ms to retain data. This can be achieved by strobing
each of the 2 048 rows (A0 – A10). A normal read- or write cycle refreshes all bits in each row that is selected.
A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output
buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only
refresh.
hidden refresh
Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding
CAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only
refresh cycle. The external address is ignored, and the refresh address is generated internally.
CAS-before-RAS ( CBR) refresh
CBR refresh is utilized by bringing CAS low earlier than RAS (see parameter tCSR) and holding it low after RAS
falls (see parameter tCHR). For successive CBR refresh cycles, CAS can remain low while cycling RAS. The
external address is ignored, and the refresh address is generated internally.
power up
To achieve proper device operation, an initial pause of 200 µs, followed by a minimum of eight initialization
cycles, is required after power up to the full VCC level. These eight initialization cycles must include at least one
refresh ( RAS-only or CBR ) cycle.
test mode
The test mode is initiated with a CBR-refresh cycle while simultaneously holding the W input low. The entry cycle
performs an internal-refresh cycle while internally setting the device to perform a parallel read or write on
subsequent cycles. While in the test mode, any data sequence can be performed. The device exits test mode
if a CBR-refresh cycle (with W held high) or a RAS-only refresh cycle is performed.
In the test mode, the device is configured as 1 024K bits × 4 bits for each DQ. Each DQ pin has a separate 4-bit
parallel-read- and write data bus that ignores column addresses A0 and A1. During a read cycle, the four internal
bits are compared for each DQ pin separately. If the four bits agree, DQ goes high; if not, DQ goes low. Test
time is reduced by a factor of four for this series of events.
6
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DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
test mode (continued)
Exit Cycle
Entry Cycle
Test Mode Cycle
Normal
Mode
RAS
CAS
W
NOTE A: The states of W, data in, and address are defined by the type of cycle used during test mode.
Figure 1. Test-Mode Cycle
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DYNAMIC RANDOM-ACCESS MEMORIES
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absolute maximum ratings over ambient temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1 V to 7 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
TMS41x400A
MIN
NOM
MAX
4.5
5
5.5
UNIT
VCC
VSS
Supply voltage
VIH
VIL
High-level input voltage
2.4
6.5
V
Low-level input voltage (see Note 2)
–1
0.8
V
Supply voltage
0
V
V
TA
Ambient temperature
0
70
°C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
8
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electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted)
TMS416400A
PARAMETER
TEST CONDITIONS†
VOH
High-level output
voltage
IOH = – 5 mA
VOL
Low-level output
voltage
IOL = 4.2 mA
II
Input current
(leakage)
IO
ICC1‡§
ICC2
’416400A - 50
MIN
’416400A - 60
MAX
2.4
MIN
MAX
2.4
’416400A - 70
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
VCC = 5.5 V,
VI = 0 V to 6.5 V,
All others = 0 V to VCC
± 10
± 10
± 10
µA
Output current
(leakage)
VCC = 5.5 V,
CAS high
VO = 0 V to VCC,
± 10
± 10
± 10
µA
Average read- or
write-cycle current
VCC = 5.5 V,
Minimum cycle
100
80
70
mA
VIH = 2.4 V ( TTL),
After one memory cycle,
RAS and CAS high
2
2
2
mA
VIH = VCC – 0.2 V (CMOS),
After one memory cycle,
RAS and CAS high
1
1
1
mA
100
80
70
mA
80
70
60
mA
Average
g standby
y
current
ICC3‡§
Average refresh
current (RAS-only
refresh or CBR)
VCC = 5.5 V,
Minimum cycle,
RAS cycling,
CAS high (RAS only),
RAS low after CAS low (CBR)
ICC4‡¶
Average page current
VCC = 5.5 V,
RAS low,
tPC = MIN,
CAS cycling
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RAS = VIL
¶ Measured with a maximum of one address change during each page-mode cycle, tPC.
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DYNAMIC RANDOM-ACCESS MEMORIES
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electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted) (continued)
TMS417400A
PARAMETER
TEST CONDITIONS†
VOH
High-level output
voltage
IOH = – 5 mA
VOL
Low-level output
voltage
IOL = 4.2 mA
II
Input current
(leakage)
IO
ICC1‡§
ICC2
’417400A - 50
MIN
’417400A - 60
MAX
2.4
MAX
2.4
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
VCC = 5.5 V,
VI = 0 V to 6.5 V,
All others = 0 V to VCC
± 10
± 10
± 10
µA
Output current
(leakage)
VCC = 5.5 V,
CAS high
VO = 0 V to VCC,
± 10
± 10
± 10
µA
Average read- or
write-cycle current
VCC = 5.5 V,
Minimum cycle
130
110
100
mA
VIH = 2.4 V ( TTL),
After one memory cycle,
RAS and CAS high
2
2
2
mA
VIH = VCC – 0.2 V (CMOS),
After one memory cycle,
RAS and CAS high
1
1
1
mA
130
110
100
mA
90
70
60
mA
Average
g standby
y
current
ICC3‡§
Average refresh
current (RAS-only
refresh or CBR)
VCC = 5.5 V,
Minimum cycle,
RAS cycling,
CAS high (RAS only),
RAS low after CAS low (CBR)
ICC4‡¶
Average page
current
VCC = 5.5 V,
RAS low,
tPC = MIN,
CAS cycling
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RAS = VIL
¶ Measured with a maximum of one address change during each page-mode cycle, tPC.
10
MIN
’417400A - 70
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capacitance over recommended ranges of supply voltage and ambient temperature,
f = 1 MHz (see Note 3)
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, A0 – A11†
5
pF
Ci(OE)
Input capacitance, OE
7
pF
Ci(RC)
Input capacitance, CAS and RAS
7
pF
Ci(W)
Input capacitance, W
Output capacitance‡
7
pF
7
pF
Co
† A11 is NC (no internal connection) for TMS417400A.
‡ CAS = VIH to disable outputs.
NOTE 3: VCC = 5 V ± 10%, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and ambient temperature
(see Note 4)
’41x400A - 50
PARAMETER
MIN
’41x400A - 60
MAX
MIN
MAX
’41x400A - 70
MIN
MAX
UNIT
tAA
tCAC
Access time from column address
25
30
35
ns
Access time from CAS
13
15
18
ns
tCPA
tRAC
Access time from CAS precharge
30
35
40
ns
Access time from RAS
50
60
70
ns
tOEA
tCLZ
Access time from OE
13
15
18
ns
Delay time, CAS to output in low-impedance state
0
0
0
ns
tOH
tOHO
Output data hold time from CAS
3
3
3
ns
Output data hold time from OE
3
3
3
ns
tOFF
tOEZ
Output buffer turn-off delay from CAS (see Note 5)
0
13
0
15
0
18
ns
Output buffer turn-off delay from OE (see Note 5)
0
13
0
15
0
18
ns
NOTES: 4. With ac parameters, it is assumed that tT = 5 ns.
5. tOFF and tOEZ are specified when the output is no longer driven. Data-in should not be enabled until one of the maximum values
is satisfied.
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ac timing requirements (see Note 4)
’41x400A - 50
’41x400A - 60
’41x400A - 70
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
tRC
tWC
Cycle time, read
90
110
130
ns
Cycle time, write
90
110
130
ns
tRWC
tPC
Cycle time, read-write
131
155
181
ns
Cycle time, page-mode read or write (see Note 6)
35
40
45
ns
tPRWC
tRASP
Cycle time, page-mode read-write
76
85
96
ns
Pulse duration, RAS active, page mode (see Note 7)
50 100 000
60 100 000
70
100 000
ns
tRAS
tCAS
Pulse duration, RAS active, nonpage mode (see Note 7)
50
10 000
60
10 000
70
10 000
ns
Pulse duration, CAS active (see Note 8)
13
10 000
15
10 000
18
10 000
ns
tCP
tRP
Pulse duration, CAS precharge
8
10
10
ns
Pulse duration, RAS precharge
30
40
50
ns
tWP
tASC
Pulse duration, write command
10
10
10
ns
Setup time, column address
0
0
0
ns
tASR
tDS
Setup time, row address
0
0
0
ns
Setup time, data-in (see Note 9)
0
0
0
ns
tRCS
tCWL
Setup time, read command
0
0
0
ns
Setup time, write command before CAS precharge
13
15
18
ns
tRWL
Setup time, write command before RAS precharge
13
15
18
ns
tWCS
Setup time, write command before CAS active
(early-write only)
0
0
0
ns
tWRP
Setup time, write before RAS active (CBR refresh only)
10
10
10
ns
tWTS
Setup time, write command before RAS active
(test mode only)
10
10
10
ns
tCAH
tDH
Hold time, column address
10
10
15
ns
Hold time, data-in (see Note 9)
10
10
15
ns
tRAH
tRCH
Hold time, row address
8
10
10
ns
Hold time, read command referenced to CAS (see Note 10)
0
0
0
ns
tRRH
Hold time, read command referenced to RAS (see Note 10)
0
0
0
ns
tWCH
Hold time, write command during CAS active
(early-write only)
10
10
15
ns
tRHCP
tOEH
Hold time, RAS active from CAS precharge
30
35
40
ns
Hold time, OE command
13
15
18
ns
tROH
tWRH
Hold time, RAS referenced to OE
10
10
10
ns
Hold time, write after RAS active (CBR refresh only)
10
10
10
ns
10
10
10
ns
tWTH
Hold time, write command after RAS active (test mode only)
NOTES: 4. With ac parameters, it is assumed that tT = 5 ns.
6. To assure tPC min, tASC should be ≥ tCP .
7. In a read-write cycle, tRWD and tRWL must be observed.
8. In a read-write cycle, tCWD and tCWL must be observed.
9. Referenced to the later of CAS or W in write operations
10. Either tRRH or tRCH must be satisfied for a read cycle.
12
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DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
ac timing requirements (see Note 4) (continued)
’41x400A - 50
MIN
MAX
’41x400A - 60
MIN
’41x400A - 70
MAX
MIN
MAX
UNIT
Delay time, column address to write command
(read-write operation only)
48
55
63
ns
tCHR
tCRP
Delay time, CAS referenced to RAS (CBR refresh only)
10
10
10
ns
5
5
5
ns
tCSH
tCSR
Delay time, RAS active to CAS precharge
50
60
70
ns
5
5
5
ns
tCWD
tOED
Delay time, CAS to write command (read-write operation only)
36
40
46
ns
Delay time, OE to data in
13
tRAD
tRAL
Delay time, RAS to column address (see Note 11)
13
Delay time, column address to RAS precharge
25
tCAL
tRCD
Delay time, column address to CAS precharge
25
Delay time, RAS to CAS (see Note 11)
18
tRPC
tRSH
Delay time, RAS precharge to CAS active
5
5
5
ns
Delay time, CAS active to RAS precharge
13
15
18
ns
tRWD
tCPW
Delay time, RAS to write command (read-write operation only)
73
85
98
ns
Delay time, CAS precharge to write command (read-write only)
53
60
68
ns
tTAA
tTCPA
Access time from address (test mode)
30
35
40
ns
Access time from column precharge (test mode)
35
40
45
ns
tTRAC
Access time from RAS (test mode)
55
65
75
tAWD
tREF
Delay time, CAS precharge to RAS
Delay time, CAS referenced to RAS (CBR refresh only)
Refresh time interval
15
25
15
18
30
15
30
35
30
37
20
ns
35
ns
35
45
20
ns
52
64
64
64
’417400A
32
32
32
2
30
2
30
2
ns
ns
’416400A
tT
Transition time
NOTES: 4. With ac parameters, it is assumed that tT = 5 ns.
11. The maximum value is specified only to ensure access time.
ns
30
ms
ns
PARAMETER MEASUREMENT INFORMATION
VTH
VCC
RL
R1
Output Under Test
Output Under Test
R2
CL = 100 pF
(see Note A)
CL = 100 pF
(see Note A)
(a) LOAD CIRCUIT
(b) ALTERNATE LOAD CIRCUIT
NOTE A: CL includes probe and fixture capacitance.
DEVICE
’41x400A
VCC ( V )
5
R1 (Ω )
R2 (Ω )
828
295
VTH ( V )
1.31
RL (Ω )
218
Figure 2. Load Circuits for Timing Parameters
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DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tRP
tT
tCSH
tRCD
tRSH
tCRP
tCAS
tASR
CAS
tCP
tRAD
tASC
tRAH
tCAL
tRAL
Address
Row
Column
Don’t Care
tRCS
W
tRRH
tRCH
tCAH
Don’t Care
Don’t Care
tCAC
tOFF
tOH
tAA
DQ1 – DQ4
Hi-Z
Valid Data Out
See Note A
tCLZ
tRAC
tOHO
tOEA
tOEZ
tROH
OE
Don’t Care
Don’t Care
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 3. Read-Cycle Timing
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DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
tWC
tRAS
tCAL
RAS
tRP
tT
tRSH
tRCD
tCAS
tCRP
tCSH
tASR
tASC
CAS
tCP
tRAL
tRAH
Address
tCAH
Row
tCWL
tRWL
tWCH
tRAD
W
Don’t Care
Column
Don’t Care
Don’t Care
tWCS
tDH
tDS
DQ1 – DQ4
Don’t Care
Valid Data
Don’t Care
OE
Figure 4. Early-Write-Cycle Timing
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SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tRP
tT
tRSH
tRCD
tCRP
tCAS
tCSH
tASR
tASC
CAS
tCP
tRAL
tCAL
tRAH
tCAH
Address
Row
Don’t Care
Column
tCWL
tRAD
W
tDS
tRWL
Don’t Care
Don’t Care
tWP
tCLZ
tDH
Valid Data In
DQ1 – DQ4
Don’t Care
Invalid Data Out
tOED
OE
tOEH
Don’t Care
Don’t Care
Figure 5. Write-Cycle Timing
16
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SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
tRWC
tRAS
RAS
tRP
tT
tCRP
tRCD
tCAS
tASR
CAS
tCP
tRAH
tCAH
tRAD
Address
tT
tASC
Row
Don’t Care
Column
tCWL
tRCS
tRWL
tRWD
tWP
tCAC
tCLZ
DQ1 – DQ4
tDH
Data
Out
See Note A
tOEA
tDS
tAA
tRAC
OE
Don’t Care
tAWD
tCWD
W
tOHO
Data
In
tOEZ
Don’t Care
tOEH
tOED
Don’t Care
Don’t Care
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 6. Read-Write-Cycle Timing
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SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
tRHCP
RAS
tRCD
tPC
tCSH
tCAS
CAS
tRAH
tASR
Address
tCRP
tRSH
tCP
tASC
Row
tCAL
tCAH
tRAL
Don’t Care
Column
Column
tAA†
tRRH
tRCH
tRCS
W
tCAC†
tRAD
tCPA†
tCAC
tAA
tOFF
tOH
tRAC
tCLZ
DQ1 – DQ4
Valid
Out
Valid
Out
See Note A
tOHO
tOEZ
OE
tOEA
Don’t Care
tOEA
tOHO
tOEZ
† Access time is tCPA-, tCAC-, or tAA-dependent.
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 7. Enhanced-Page-Mode Read-Cycle Timing
18
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DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
tRHCP
RAS
tCSH
tPC
tCRP
tRSH
tRCD
tCAL
tCAS
tASC
CAS
tRAH
tCP
Address
tRAL
tCAH
tASR
Row
tRAD
tCWL
tCWL
tRWL
tWP
tDS
W
Don’t Care
Don’t Care
Don’t Care
Don’t Care
tOEH
tDH
DQ1 – DQ4
Don’t Care
Column
Column
tCLZ
Valid
In
Valid Data In
Don’t Care
Invalid Data out
tOEH
tOED
Don’t Care
OE
Don’t Care
NOTE A: A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not violated.
Figure 8. Enhanced-Page-Mode Write-Cycle Timing
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DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tRHCP
tCSH
tRSH
tPRWC
tRCD
CAS
tCRP
tCP
tCAS
tASR
tASC
tRAD
tCAH
Row
Address
Don’t Care
Column
Column
tRAH
tCWL
tCWD
tAWD
tRWD
tCPW
tRWL
tWP
W
tCPA
tRCS
tDH
tAA
tRAC
tDS
Valid Out†
tCAC
Valid
In
Valid
In
DQ1 – DQ4
tCLZ
tOEH
Valid Out
tOEZ
tOEA
tOED
tOEH
OE
tOHO
† Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
NOTE A: A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.
Figure 9. Enhanced-Page-Mode Read-Write-Cycle Timing
20
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SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tCRP
tRP
tT
tRPC
Don’t Care
CAS
tASR
tRAH
Don’t Care
Address
Row
W
Don’t Care
DQ1 – DQ4
Don’t Care
OE
Don’t Care
Don’t Care
Row
Figure 10. RAS-Only Refresh Timing
tRC
tRP
tRAS
RAS
tCSR
tRPC
tCHR
tT
CAS
tWRP
W
tWRH
Don’t Care
Don’t Care
Address
Don’t Care
OE
Don’t Care
DQ1 – DQ4
Hi-Z
Figure 11. Automatic-CBR-Refresh-Cycle Timing
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DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Refresh Cycle
Memory Cycle
tRP
tRP
tRAS
tRAS
RAS
tCHR
tCAS
CAS
tCAH
tASC
tRAH
tASR
Address
Row
Col
Don’t Care
tWRH
tRRH
tWRH
tWRH
tWRP
tWRP
tRCS
tWRP
W
tRAC
tCAC
tAA
tOFF
Valid Data Out
DQ1 – DQ4
tCLZ
tOEZ
tOEA
OE
Figure 12. Hidden-Refresh-Cycle (Read) Timing
22
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DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Memory Cycle
Refresh Cycle
tRP
tRAS
tRP
tRAS
RAS
tCHR
tCAS
CAS
tCAH
tASC
tRAH
tASR
Row
Address
Don’t Care
Col
tWRH
tWCS
tWRP
tWP
W
tWCH
tDH
tDS
DQ1 – DQ4
Don’t Care
Valid Data
Don’t Care
OE
Figure 13. Hidden-Refresh-Cycle ( Write) Timing
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DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
tRC
tRP
tRAS
RAS
tCSR
tCHR
tRPC
tT
CAS
tWTH
tWTS
Don’t Care
W
Address
Don’t Care
OE
Don’t Care
DQ1 – DQ4
Hi-Z
Figure 14. Test-Mode-Entry-Cycle Timing
tRC
tRP
tRAS
RAS
tCSR
tRPC
tCHR
tT
CAS
tWRP
W
Don’t Care
Don’t Care
tWRH
Address
Don’t Care
tOFF
DQ1 – DQ4
Hi-Z
Don’t Care
Figure 15. Test-Mode-Exit-Cycle CBR-Refresh-Cycle Timing
24
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DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
MECHANICAL DATA
DJ (R-PDSO-J24/26)
PLASTIC SMALL-OUTLINE J-LEAD PACKAGE
0.680 (17,27)
0.670 (17,02)
26
21
19
14
0.340 (8,64)
0.330 (8,38)
0.305 (7,75)
0.295 (7,49)
1
6
8
13
0.032 (0,81)
0.026 (0,66)
0.106 (2,69) TYP
0.148 (3,76)
0.128 (3,25)
0.008 (0,20) NOM
Seating Plane
0.004 (0,10)
0.020 (0,51)
0.016 (0,41)
0.007 (0,18) M
0.275 (6,99)
0.260 (6,60)
0.050 (1,27)
40400A92-3 / B 10/94
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.005 (0,125).
device symbolization (TMS416400A illustrated)
TI
-SS
Speed ( - 50, - 60, - 70)
TMS416400A DJ
Package Code
W
E
Y
M LLLL P
Assembly Site Code
Lot Traceability Code
Month Code
Year Code
Die Revision Code
Wafer Fab Code
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26
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