NTE3880 Integrated Circuit NMOS, 8–Bit Microprocessor (MPU), 4MHz Description: The NTE3880 is a third generation single chip microprocessor with unrivaled computational power. This increased computational power results in higher system through–put and more efficient memory utilization when compared to second generation microprocessors. In addition it is very easy to implement into a system because of it’s single voltage requirement plus all output signals are fully decoded and timed to control standard memory or peripheral circuits. The circuit is implemented using an N– channel, ion implanted, silicon gate MOS process. This device has an internal register configuration which contains 208 bits of Read/Write memory that are accessible to the programmer. The registers include two sets of six general purpose registers that may be used individually as 8–bit registers or as 16–bit register pairs. There are also two sets of accumulator and flag registers. The programmer has access to either set of main or alternate registers through a group of exchange instructions. This alternate set allows foreground/background mode of operation or may be reserved for very fast interrupt response. The NTE3880 also contains a 16–bit stack pointer which permits simple implementation of multiple level interrupts, unlimited subroutine nesting and simplification of many types of data handling. The two 16–bit index registers allow tabular data manipulation and easy implementation of relocatable code. The Refresh register provides for automatic, totally transparent refresh of external dynamic memories. The I register is used in a powerful interrupt response mode to form the upper 8 bits of a pointer to a interrupt service address table, while the interrupting device supplies the lower 8 bits of the pointer. An indirect call is then made to this service address. Features: D Single Chip, N–Channel Silicon Gate D 158 Instructions – Includes all 78 of the 8080A Instructions with Total Software Compatibility. New Instructions Include 4–, 8– and 16–Bit Operations with more useful Addressing Modes such as Indexed, Bit and Relative D 17 Internal Registers D Three Modes of Fast Interrupt Response plus a Non–Maskable Interrupt D Directly Interfaces Standard Speed Static or Dynamic Memories with Virtually No External Logic D 1.0µs Instruction Execution Speed D Single 5VDC Supply and Single–Phase 5V Clock D Out–Performs any other Single–Phase 5V Clock D All Pins TTL Compatible D Built–In Dynamic RAM Refresh Circuitry Absolute Maximum Ratings: Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° to +70°C Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65° to +150°C Voltage On Any Pin With Respect to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5W Note 1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics: (TA = 0° to 70°C, VCC = 5V ±5% unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Clock Input Low Voltage VILC –0.3 – 0.80 V Clock Input High Voltage VIHC VCC–0.6 – VCC+3 V Input Low Voltage VIL –0.3 – 0.8 V Input High Voltage VIH 2.0 – VCC V Output Low Voltage VOL IOL = 1.8mA – – 0.4 V Output High Voltage VOH IOH = –250µA 2.4 – – V Power Supply Current ICC – 90 200 mA Input Leakage Current IL1 VIN = 0 to VCC – – 10 µA Tri–State Output Leakage Current in Float ILOH VOUT = 2.4 to VCC – – 10 µA Tri–State Output Leakage Current in Float ILOL VOUT = 0.4V – – –10 µA Data Bus Leakage Current in Input Mode ILD 0 ≤ VIN ≤ VCC – – ±10 µA Capacitance: (TA = +25°C, f = 1MHz, unmeasured pins to GND unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Clock Capacitance Cφ – – 35 pF Input Capacitance CIN – – 5 pF COUT – – 10 pF Output Capacitance AC Characteristics: (TA = 0°C to +70°C, VCC = +15V ± 5% unless otherwise specified) Parameter Symbol Signal Test Conditions φ Min Typ Max Unit 25 – Note 2 µs 110 – Note 3 ns Clock Period Clock Pulse Width, Clock High tc tw (φH) Clock Pulse Width, Clock Low tw (φL) 110 – 2000 ns tr, tf – – 30 ns – – 110 ns Clock Rise and Fall Time Address Output Delay tD (AD) Data to Float tF (AD) – – 90 ns Address Stable Prior to MRFQ (Memory Cycle) tacm Note 4 – – ns Address Stable Prior to IOFQ, RD or WR (I/O Cycle) taci Note 5 – – ns Address Stable from RD, WR, IORQ, or MREQ tca Note 6 – – ns Address Stable from RD or WR During Float tcaf Note 7 – – ns Note Note Note Note Note Note 2. 3. 4. 5. 6. 7. A0–15 CL = 50pF tc = tw (φH) + tw (φL) + tr + tf. Although static by design, testing guarantees tw (φH) of 200µs maximum. tacm = tw (φH) + tf–65. taci = tc–70. tca = tw (φL) + tr–50. tcaf = tw (φL) + tr–45. AC Characteristics (Cont’d): (TA = 0°C to +70°C, VCC = +15V ± 5% unless otherwise specified) Parameter Symbol Signal Data Output Delay Delay to Float During Write Cycle tD (D) tF (D) D0–7 Data Setup Time to Rising Edge of Clock During M1 Cycle tSφ (D) Test Conditions CL = 50pF Data Setup Time to falling Edge of Clock During M2 to M5 Min Typ Max Unit – – 150 ns – – 90 ns 35 – – ns 50 – – ns Data Stable Prior to WR (Memory Cycle) tdcm Note 8 – – ns Data Stable Prior to WR (I/O Cycle) tdci Note 9 – – ns Data Stable From WR tcdf Note 10 – – ns Any Hold Time for Setup Time tH – – 0 ns – – 85 ns – – 85 ns – – 85 ns MREQ Delay From Falling Edge of Clock, MREQ Low tDLφ (MR) MREQ Delay From Rising Edge of Clock, MREQ High tDHφ (MR) MREQ CL = 50pF MREQ Delay From Falling Edge of Clock, MREQ High Pulse Width, MREQ Low tw (MRL) Note 11 – – ns Pulse Width, MREQ High tw (MRH) Note 12 – – ns IORQ Delay From Rising Edge of Clock IORQ Low tDLφ (IR) – – 75 ns – – 85 ns – – 85 ns – – 85 ns – – 85 ns – – 95 ns – – 85 ns – – 85 ns – – 65 ns – – 80 ns IORQ CL = 50pF IORQ Delay From Falling Edge of Clock IORQ Low IORQ Delay From Rising Edge of Clock IORQ High tDHφ (IR) IORQ Delay From Falling Edge of Clock IORQ High RD Delay From Rising Edge of Clock, RD Low tDLφ (RD) RD CL = 50pF RD Delay From Falling Edge of Clock, RD Low RD Delay From Rising Edge of Clock, RD High tDHφ (RD) RD Delay From Falling Edge of Clock, RD High WR Delay From Rising Edge of Clock, WR Low tDLφ (WR) WR Delay From Falling Edge of Clock, WR Low WR CL = 50pF WR Delay From Falling Edge of Clock, WR High tDHφ (WR) – – 80 ns Pulse Width, WR Low tw (WRL) Note 13 – – ns Note 8. Note 9. Note10. Note 11. Note12. Note13. tdcm = tc–170. tdci = tw (φL) + tr–170. tcdf = tw (φL) + tr–70. tw (MRL) = tc–30. tw (MRH) = tw (φH) + tr–20. tw (WRL) = tc–30. AC Characteristics (Cont’d): (TA = 0°C to +70°C, VCC = +15V ± 5% unless otherwise specified) Parameter M1 Delay From Rising Edge of Clock, M1 Low M1 Delay From Rising Edge of Clock, M1 High Symbol Signal tDL (M1) M1 CL = 50pF tDH (M1) RFSH Delay From Rising Edge of Clock, RFSH Low tDL (RF) RFSH Delay From Rising Edge of Clock, RFSH High tDH (RF) WAIT Setup Time to Falling Edge of Clock ts (WT) WAIT HALT Delay Time From Falling Edge of Clock tD (HT) HALT INT Setup Time to Rising Edge of Clock Test Conditions RFSH CL = 50pF CL = 50pF Min Typ Max Unit – – 100 ns – – 100 ns – – 130 ns – – 120 ns 70 – – ns – – 300 ns ts (IT) INT 80 – – ns tw (NML) NM1 80 – – ns BUSRQ Setup Time to Rising Edge of Clock ts (BQ) BUSRQ 50 – – ns BUSAK Delay From Rising Edge of Clock, BUSAK Low tDL (BA) BUSAK CL = 50pF – – 100 ns BUSAK Delay From Rising Edge of Clock, BUSAK High tDH (BA) – – 100 ns RESET Setup Time to Rising Edge of Clock ts (RS) 60 – – ns Delay to Float (MREQ, IORQ, RD and WR) tF (C) – – 80 ns tmr Note 14 – – ns Pulse Width, NM1 Low M1 Stable Prior to IORQ (Interrupt Ack.) RESET Note14. tmr = 2tc + tw (φH) + tf–65. Note15. Data should be enabled onto the CPU data bus when RD is active. During interrupt acknowledge data should be enabled when M1 and IORQ are both active. Note16. All control signals are internally synchronized, so they may be totally asynchronous with respect to the clock. Note17. The RESET signal must be active for a minimum of 3 clock cycles. Note18. Output Delay vs. Loaded Capacitance VCC = 5V ±5% TA = +70°C Add 10ns delay for each 50pf increase in load up to maximum of 200pF for data bus and 100pF for address & control lines. Pin Connection Diagram 40 A10 A11 1 39 A9 A12 2 38 A8 A13 3 A14 4 37 A7 A15 5 36 A6 System Clock Input 6 35 A5 34 A4 D4 7 33 A3 D3 8 D5 9 32 A2 D6 10 31 A1 30 A0 (+) 5V 11 29 GND D2 12 D7 13 28 RFSH 27 M1 D0 14 D1 15 26 RESET 25 BUSRQ INT 16 NMI 17 24 WAIT HALT 18 23 BUSAK MREQ 19 22 WD IORQ 20 21 RD 40 21 1 20 2.055 (52.2) .550 (13.9) Max .155 (3.9) .100 (2.54) .019 (0.5) .137 (3.5) .650 (16.5)