NTE3882 Integrated Circuit NMOS, Counter Timer Control (CTC) Description: The NTE3882 Counter Timer Circuit (CTC) is a programmable, four channel device in a 28–Lead DIP type package that provides counting and timing functions for the NTE3880. The NTE3880 configures the NTE3882’s four independent channels to operate under various modes and conditions as required. The internal structure of the NTE3882 consists of an NTE3880 bus interface, internal control logic, four counter channels, and interrupt control logic. Each channel has an interrupt vector for automatic interrupt vectoring, and interrupt priority is determined by channel number with channel ∅ having the highest priority. The channel logic is composed of 2 registers, 2 counters and control logic. The registers include and 8–bit time constant register and an 8–bit channel control register. The counters include as 8–bit readable down counter and an 8–bit prescaler. The prescaler may be programmed to divide the system clock by either 16 or 256. Structure: D N–Channel Silicon Gate Depletion Load Technology D Single 5V Supply D Single Phase 5V Clock D Four Independent Programmable 8–Bit Counter/16–Bit Timer Channels Features: D Each Channel may be Selected to Operate in Either a Counter Mode or Timer Mode D Programmable Interrupts on Counter or Timer States D A Time Constant Register Automatically Reloads, the Down Counter at Zero and the Cycle is Repeated D Readable Down Counter Indicates Number of Counts–to–Go until Zero D Selectable 16 or 256 Clock Prescaler for Each Timer Channel D Selectable Positive or Negative Trigger may Initiate Timer Operation D Three Channels have Zero Count/Timeout Outputs capable of Driving Darlington Transistors D Daisy Chain Priority Interrupt Logic Included to Provide for Automatic Interrupt Vectoring without External Logic D All Inputs and Outputs Fully TTL Compatible Absolute Maximum Ratings: Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° to +70°C Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65° to +150°C Voltage On Any Pin With Respect to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8W Note 1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics: (TA = 0° to 70°C, VCC = 5V ±5% unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Clock Input Low Voltage VILC –0.3 – 0.45 V Clock Input High Voltage VIHC VCC–0.6 – VCC+3 V Input Low Voltage VIL –0.3 – 0.8 V Input High Voltage VIH 2.0 – VCC V Output Low Voltage VOL IOL = 2mA – – 0.4 V Output High Voltage VOH IOH = –250µA 2.4 – – V Power Supply Current ICC TC = 250ns – – 120 mA Input Leakage Current IL1 VIN = 0 to VCC – – 10 µA Tri–State Output Leakage Current in Float ILOH VOUT = 2.4 to VCC – – 10 µA Tri–State Output Leakage Current in Float ILOL VOUT = 0.4V – – –10 µA Darlington Drive Current IOHD VOH = 1.5V, REXT = 390Ω –1.5 – – mA Min Typ Max Unit – – 20 pF – – 5 pF – – 10 pF Min Typ Max Unit Capacitance: (TA = +25°C, f = 1MHz unless otherwise specified) Parameter Symbol Clock Capacitance Cφ Input Capacitance CIN Output Capacitance Test Conditions Unmeasured Pins Returned to GND COUT AC Characteristics: (TA = 0° to 70°C, VCC = 5V ±5% unless otherwise specified) Parameter Symbol Test Conditions Clock Cycle Time TcC 400 – Note 2 ns Clock Width (High) TwCH 170 – 2000 ns Clock Width (Low) TwCL 170 – 2000 ns Clock Fall Time TfC – – 30 ns Clock Rise Time TrC – – 30 ns All Hold Times Th 0 – – ns CS to Clock ↑ Setup Time TsCS(C) 250 – – ns CE to Clock ↑ Setup Time TsCE(C) 200 – – ns IORQ ↓ to Clock ↑ Setup Time TsIO(C) 250 – – ns RD to Clock ↑ Setup Time TsRD(C) 240 – – ns Note 2. TcC = TwCH + TwCL + TcC + TrC. AC Characteristics (Cont’d): (TA = 0° to 70°C, VCC = 5V ±5% unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Clock ↓ to Data Out Delay TdC(DO) Note 3 – – 240 ns Clock ↑ to Data Out Float Delay TdC(DOz) – – 230 ns Data In to Clock ↑ Setup Time TsDI(C) 60 – M1 to Clock ↑ Setup Time (INTA or M1 Cycle) TsM1(C) 210 – – ns ns M1 ↓ to IEO ↓ Delay (Interrupt Immediately Preceding M1) TdM1(IEO) Note 4, Note 5 – – 300 ns IORQ ↓ to Data Out Delay (INTA Cycle) TdIO(DOT) Note 3 – – 340 ns IEI ↓ to IEO ↓ Delay TdIEI(IEOf) Note 4 – – 190 ns IEI ↑ to IEO ↑ Delay (After ED Decode) TdIEI(IEOr) Note 4 – – 220 ns Timer Mode – – TcT + 220 ns – – TcC + 230 ns – – 2TcC + 530 ns 2TcC – – ns Clock ↑ to INT ↓ Delay TdC(INT) CLR/TRG ↑ to INT ↓ (TsCTR(C) Satisfied) CLR/TRG ↑ to INT ↓ (TsCTR(C) Not Satisfied) TdCTK(INT) Counter Mode CLK Cycle Time TcCTR Counter Mode CLK/TRG Rise Time TrCTR – – 50 ns CLK/TRG Fall Time TfCTR – – 50 ns CLK/TRG Width (Low) TwCTRL 200 – – ns CLK/TRG Width (High) TwCTRH 200 – – ns CLK ↑ to Clock ↑ Setup Time for Immediate Count TsCTR(Cc) Counter Mode 300 – – ns TRG ↑ to Clock ↑ Setup Time for Enabling of Prescaler on Following Clock ↑ TsCTR(Ct) Timer Mode 210 – – ns 260 – – ns 190 – – ns Clock ↑ to ZC/TO ↑ Delay TdC(ZCTOr) Clock ↓ to ZC/TO ↓ Delay Note 3. Increase delay by 10ns for each 50pF increase in loading, 200pF maximum for data lines and 100pF for control lines. Note 4. Increase delay by 10ns for each 10pF increase in loading, 100pF maximum. Note 5. 2.5 TcC > (N–2) TdIEI(IEOF) + TdIM1(IEO) + TsIEI(IO). Note 6. RESET must be active for a minimum of 3 clock cycles. Pin Connection Diagram D4 1 D5 2 D6 3 D7 4 GND 5 RD 6 7 ZC/TO0 ZC/TO1 8 ZC/TO2 9 IORQ 10 IEO 11 INT 12 IEI 13 M1 14 28 D3 27 D2 26 D1 25 D0 24 (+) 5V 23 CLK/TRG0 22 CLK/TRG1 21 CLK/TRG2 20 CLK/TRG3 19 CS1 18 CS0 17 RESET 16 CE 15 System Clock Input 14 1 15 28 1.469 (37.32) Max .540 (13.7) .250 (6.35) .100 (2.54) 1.300 (33.02) .122 (3.1) Min .600 (15.24)