TI SN65LVPE502CPRGET

SN65LVPE502CP
SLLSE79A – MARCH 2011 – REVISED SEPTEMBER 2011
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Dual Channel USB3.0 Redriver/Equalizer
Check for Samples: SN65LVPE502CP
FEATURES
•
1
•
•
•
•
•
•
•
•
Single Lane USB 3.0 Equalizer/Redriver
Selectable Equalization, De-Emphasis and
Output Swing Control
Integrated Termination
Hot-Plug Capable
Low Active Power (U0 state)
– 315 mW (TYP), VCC = 3.3V
USB 3.0 Low Power Support
– 7 mW (TYP) When no Connection Detected
– 70 mW (TYP) When Link in U2/U3 Mode
Excellent Jitter and Loss Compensation
Capability:
– >40" of Total 4 mil Stripline on FR4
Small Foot Print – 24 Pin (4mm x 4mm) QFN
Package
High Protection Against ESD Transient
– HBM: 5,000 V
– CDM: 1,500 V
– MM: 200 V
APPLICATIONS
•
Notebooks, Desktops, Docking Stations,
Active Cable, Backplane and Active Cable
DESCRIPTION
The SN65LVPE502CP is a dual channel, single lane
USB 3.0 redriver and signal conditioner supporting
data rates of 5.0Gbps. The device complies with USB
3.0 spec revision 1.0, supporting electrical idle
condition and low frequency periodic signals (LFPS)
for USB 3.0 power management modes.
SPACER
Main PCB
Redriver
USB Host
USB
Connector
20"
Main PCB
USB Host
Connector
Device PCB
Device
Redriver
20"
3m USB
3.0 Cable
1"-6"
Figure 1. Typical Application
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
SN65LVPE502CP
SLLSE79A – MARCH 2011 – REVISED SEPTEMBER 2011
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
EN_RXD
RX1+
RX1-
Dual Termination
Detect
TX1+
Receiver/
Equalizer
CHANNEL 1
Driver
TX1-
EQ1
EQ
CNTRL
EQ2
DE1
VTX_CM_DC
DEMP
CNTRL
DE2
CHANNEL 2
Driver
Dual Termination
TX2+
Receiver/
Equalizer
TX2-
Detect
VTX_CM_DC
OS
Cntrl.
RX2+
RX2-
EN_RXD
OS1 OS2
Figure 2. Data Flow Block Diagram
ORDERING INFORMATION (1)
(1)
2
PART NUMBER
PART MARKING
PACKAGE
SN65LVPE502CPRGER
502CP
24-pin RGE Reel (Large)
SN65LVPE502CPRGET
502CP
24-pin RGE Reel (Small)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
Supply voltage range (2)
Voltage range
MAX
VCC
–0.5
4
V
Differential I/O
–0.5
4
V
Control I/O
–0.5
VCC + 0.5
V
(3)
±5000
V
Charged-device model (4)
±1500
V
Machine model (5)
±200
V
Human body model
Electrostatic discharge
Continuous power
dissipation
(1)
(2)
(3)
(4)
(5)
UNIT
MIN
See Thermal Table
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-B
Tested in accordance with JEDEC Standard 22, Test Method C101-A
Tested in accordance with JEDEC Standard 22, Test Method A115-A
THERMAL INFORMATION
SN65LVPE502CP
THERMAL METRIC (1)
RGE PACKAGE
UNITS
24 PINS
θJA
Junction-to-ambient thermal resistance
46
θJCtop
Junction-to-case (top) thermal resistance
42
θJB
Junction-to-board thermal resistance
13
θJCbot
Junction-to-case (bottom) thermal resistance
4
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
THERMAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX (1)
UNIT
PD
Device power dissipation
RSVD, EN_RXD, EQ cntrl pins = NC,
K28.5 pattern at 5 Gbps, VID = 1000mVp-p
330
450
mW
PSlp
Device power dissipation in sleep mode
EN_RXD= GND
0.3
1
mW
(1)
The maximum rating is simulated under 3.6V VCC.
Device Power
The SN65LVPE502CP is designed to operate from a single 3.3V supply.
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RECOMMENDED OPERATING CONDITIONS
PARAMETER
VCC
Supply voltage
CCOUPLING
AC Coupling capacitor
CONDITIONS
MIN
3
Operating free-air
temperature
TYP MAX UNITS
3.6
V
75
3.3
200
nF
0
85
°C
DEVICE PARAMETERS
EN_RXD, RSVD, EQ cntrl = NC,
K28.5 pattern at 5 Gbps, VID = 1000mVp-p
ICC
ICCRx.Detect
Supply current
ICCsleep
100
In Rx.Detect mode
EN_RXD = GND
ICCU2-U3
Link in USB low power state
120
2
5
0.01
0.1
21
Maximum data rate
5
tENB
Device enable time
Sleep mode exit time EN_RXD L → H
With Rx termination present
tDIS
Device disable time
Sleep mode entry time EN_RXD H → L
TRX.DETECT
Rx.Detect start event
Power-up time
mA
Gbps
100
µs
2
µs
100
µs
CONTROL LOGIC
VIH
High level input voltage
1.4
VCC
V
VIL
Low level input voltage
–0.3
0.5
V
VHYS
Input hysteresis
150
OSx, EQx, DEx = VCC
IIH
High level input current
EN_RXD = VCC
1
RSVD = VCC
IIL
Low level input current
4
–30
EN_RXD = GND
–30
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µA
30
OSx, EQx, DEx = GND
RSVD = GND
mV
30
µA
–1
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ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
1200
mVp-p
RECEIVER AC/DC
Vindiff_p-p
RX1, RX2 input voltage swing
VCM_RX
RX1, RX2 common mode voltage
AC coupled differential RX peak to peak signal
100
VinCOM_P
RX1, RX2 AC peak common mode
voltage
ZDC_RX
DC common mode impedance
18
Zdiff_RX
DC differential input impedance
72
50
85
3.3
Measured at Rx pins with termination enabled
ZRX_High_IMP+
DC Input high impedance
Device in sleep mode Rx termination not powered
measured with respect to GND over 500mV max
VRX-LFPS-DETpp
Low voltage periodic signaling (LFPS)
detect threshold
Measured at receiver pin, below minimum output is
squelched, above max input signal is passed to output
RLRX-DIFF
Differential return loss
RLRX-CM
Common mode return loss
V
150
mVP
26
30
Ω
80
120
Ω
100
kΩ
300
50 MHz – 1.25 GHz
10
11
1.25 GH – 2.5 GHz
6
7
50 MHz– 2.5 GHz
11
13
800
1042
mVpp
dB
dB
TRANSMITTER AC/DC
RL = 100 Ω ±1%, DEx, OSx = NC,
Transition Bit
VTXDIFF_TB_P-P
Differential peak-to-peak output voltage
(VID = 800, 1200 mVpp, 5Gbps)
VTXDIFF_NTB_P-P
RL = 100 Ω ±1%, DEx = NC, OSx = GND
Transition Bit
908
RL = 100 Ω ±1%, DEx = NC, OSx = VCC
Transition Bit
1127
RL = 100 Ω ±1%, DEx=NC, OSx = 0,1,NC
Non-Transition Bit
1042
RL = 100 Ω ±1%, DEx=0 OSx = 0,1,NC
Non-Transition Bit
661
RL = 100 Ω ±1%, DEx=1 OSx = 0,1,NC
Non-Transition Bit
507
DE1/DE2 = NC
DE
De-emphasis level OS1,2 = NC (for OS1,
2 = 1 and 0 see Table 2)
De-emphasis width
Zdiff_TX
DC differential impedance
ZCM_TX
DC common mode impedance
mV
mV
0
–3.0
DE1/DE2 = 0
–3.5
–4.0
dB
–6.0
DE1/DE2 = 1
TDE
1200
0.85
UI
72
90
120
Ω
18
23
30
Ω
f = 50 MHz – 1.25 GHz
9
10
f = 1.25 GHz – 2.5 GHz
6
7
11
12
Measured w.r.t to AC ground over 0-500mV
RLdiff_TX
Differential return loss
dB
RLCM_TX
Common mode return loss
f = 50 MHz – 2.5 GHz
ITX_SC
TX short circuit current
TX± shorted to GND
VTX_CM_DC
Transmitter DC common-mode voltage
VTX_CM_AC_Active
TX AC common mode voltage active
VTX_idle_diff-AC-pp
Electrical idle differential peak to peak
output voltage
VTX_CM_DeltaU1-U0
Absolute delta of DC CM voltage during
active and idle states
VTX_idle_diff-DC
DC Electrical idle differential output
voltage
Voltage must be low pass filtered to remove any AC
component
Vdetect
Voltage change to allow receiver detect
Positive voltage to sense receiver termination
tR, tF
Output rise/fall time
20%–80% of differential voltage measured 1" from the
output pin
tRF_MM
Output rise/fall time mismatch
20%–80% of differential voltage measured 1" from the
output pin
1.5
20
ps
Tdiff_LH, Tdiff_HL
Differential propagation delay
De-Emphasis = –3.5 dB (CH 0 and CH 1). Propagation
delay between 50%
level at input and output
305
370
ps
tidleEntry, tidleExit
Idle entry and exit times
See Figure 4
4
6
CTX
Tx input capacitance to GND
At 2.5 GHz
dB
60
2.0
HPF to remove DC
2.6
3.0
V
30
100
mVpp
10
mVpp
200
mV
10
mV
600
mV
0
35
0
30
65
ps
1.25
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mA
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pF
5
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ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
0.23
0.5
0.14
0.3
Random jitter (Rj)
0.08
0.2
Total jitter (Tj) at point B
0.15
0.5
0.07
0.3
0.08
0.2
UNITS
EQUALIZATION
TTX-EYE
(1) (2)
DJTX
(2)
RJTX
(2) (4)
TTX-EYE
Total jitter (Tj) at point A
(1) (2)
DJTX (2)
Deterministic jitter (Dj)
RJTX (2) (4)
Random jitter (Rj)
(1)
(2)
(3)
(4)
Device setting: OS1 = L,
DE1 = –6 dB, EQ1 = 7 dB
Deterministic jitter (Dj)
Device setting: OS2 = H,
DE2 = –6 dB, EQ2 = 7dB
UI (3)p-p
UI (3)p-p
Includes RJ at 10-12 BER
Determininstic jitter measured with K28.5 pattern, Random jitter measured with K28.5 pattern at the ends of reference channel in
Figure 6, VID=1000mVpp, 5Gbps, –3.5dB DE from source
UI = 200ps
Rj calculated as 14.069 times the RMS random jitter for 10-12 BER
IN
Tdiff_HL
Tdiff_LH
OUT
Figure 3. Propagation Delay
IN+
VEID_TH
Vcm
INtidleEntry
tidleExit
OUT +
Vcm
OUT -
Figure 4. Electrical Idle Mode Exit and Entry Delay
80%
20%
tr
tf
Figure 5. Ouput Rise and Fall Times
6
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Jitter
Measurement
CH1
SN65LVPE502CP
A
1
2
AWG*
CH1
Up to 3 m
(30 AWG)
20"
4"
1"-6"
B
AWG*
CH2
Jitter
Measurement
CH2
Figure 6. Jitter Measurement Setup
1-bit
1 to N bits
tDE
DEx = 0dB
1-bit
1 to N bits
-3.5dB
-6dB
Vcm
VTXDIFF_NTB_P-P
VTXDIFF_TB_P-P
tDE
Figure 7. Output De-Emphasis Levels OSx = NC
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DEVICE INFORMATION
VCC EQ1 DE1 OS1 EN_RXD GND
1
6
NC
SN65LVPE502CP
24
7 NC
TX1-
RX1CH1
RX1+
TX1+
Thermal Pad
(must be soldered to GND plane)
GND
GND
RX2-
TX2CH2
12 TX2+
RX2+ 19
13
18
GND EQ2 DE2 OS2 RSVD VCC
Bottom View
GND EN_RXD OS1 DE1 EQ1 VCC
6
NC
1
SN65LVPE502CP
7
24 NC
TX1-
RX1CH1
RX1+
TX1+
Thermal Pad
(must be soldered to GND plane)
GND
TX2-
GND
RX2-
CH2
CH2
CH2
TX2+ 12
19 RX2+
18
13
VCC RSVD OS2 DE2 EQ2 GND
Top View
Figure 8. Flow-Through Pin-Out
Table 1. Pin Functions
PIN
Number
Name
I/O Type
Description
HIGH SPEED DIFFERENTIAL I/O PINS
8
8
RX1–
I, CML
9
RX1+
I, CML
20
RX2–
I, CML
19
RX2+
I, CML
Non-inverting and inverting CML differential input for CH 1 and CH 2. These pins are tied to an
internal voltage bias by dual termination resistor circuit
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Table 1. Pin Functions (continued)
PIN
I/O Type
Number
Name
23
TX1–
O, CML
22
TX1+
O, CML
11
TX2–
O, CML
12
TX2+
O, CML
Description
Non-inverting and inverting CML differential output for CH 1 and CH 2. These pins are internally
tied to voltage bias by termination resistors
DEVICE CONTROL PIN
5
EN_RXD
14
7, 24
I, LVCMOS
Sets device operation modes per Table 2. Internally pulled to VCC
RSVD
I, LVCMOS
RSVD, internally pulled to GND. Can be left as No-connect.
NC
No-connect
Pads are not internally connected
EQ CONTROL PINS (1)
3, 16
DE1, DE2
I, LVCMOS
Selects de-emphasis settings for CH 1 and CH 2 per Table 2. Internally tied to Vcc/2
2, 17
EQ1, EQ2
I, LVCMOS
Selects equalization settings for CH 1 and CH 2 per Table 2. Internally tied to Vcc/2
4, 15
OS1, OS2
I, LVCMOS
Selects output amplitude for CH 1 and CH 2 per Table 2. Internally tied to Vcc/2
POWER PINS
VCC
Power
Positive supply should be 3.3V ± 10%
6, 10, 18, 21 GND
Power
Supply ground
1,13
(1)
Internally biased to Vcc/2 with >200kΩ pull-up/pull-down. When pins are left as NC board leakage at this pin pad must be < 1 µA
otherwise drive to Vcc/2 to assert mid-level state
Table 2. Signal Control Pin Setting
OUTPUT SWING AND EQ CONTROL (at 2.5 GHz)
OSx (1)
TRANSISTION BIT AMPLITUDE
(TYP mVpp)
EQx (1)
EQUALIZATION
(dB)
NC (default)
1042
NC (default)
0
0
908
0
7
1127
1
15
1
OUTPUT DE CONTROL (at 2.5 GHz)
DEx (1)
OSx (1) = NC
OSx (1) = 0
OSx (1) = 1
NC (default)
0 dB
0 dB
0 dB
0
–3.5 dB
–2.2 dB
–4.4 dB
1
–6.0 dB
–5.2 dB
–6.0 dB
CONTROL PINS SETTINGS
(1)
EN_RXD
DEVICE FUNCTION
1 (default)
Normal Operation
0
Sleep Mode
Where x = Channel 1 or Channel 2
USB Host
USB Device
SN65LVPE502CP
Device PCB
8"-20"
2"-6"
Up to 3 m
(30 AWG )
1 "-6 "
NOTE: For more detailed placement example of redriver see typical eye diagrams and jitter plots at end of data sheet.
Figure 9. Redriver Placement Example
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DETAILED DESCRIPTION
Programmable EQ, De-Emphasis and Amplitude Swing
The SN65LVPE502CP is designed to minimize signal degradation effects such as crosstalk and inter-symbol
interference (ISI) that limits the interconnect distance between two devices. The input stage of each channel
offers selectable equalization settings that can be programmed to match loss in the channel. The differential
outputs provide selectable de-emphasis to compensate for the anticipated distortion USB 3.0 signal will
experience. Level of de-emphasis will depend on the length of interconnect and its characteristics. The
SN65LVPE502CP provides a unique way to tailor output de-emphasis on a per channel basis with use of DE and
OS pins. All Rx and Tx equalization settings supported by the device are programmed by six 3-state pins as
shown in Table 2.
Low Power Modes
Device supports three low power modes as described below
1. Sleep Mode
Initiated anytime EN_RXD undergoes a high to low transition and stays low or when device powers up with
EN_RXD set low. In sleep mode both input and output terminations are held at HiZ and device ceases
operation to conserve power. Sleep mode max power consumption is 1mW, entry time is 2µs, device exits
sleep mode to Rx.Detect mode after EN_RXD is driven to Vcc, exit time is 100µs max.
2. RX Detect Mode--When no remote device is connected
Anytime LVPE502CP detects a break in link (i.e. when upstream device is disconnected) or after power-up
fails to find a remote device, LVPE502CP goes to Rx Detect mode and conserves power by shutting down
majority of its internal circuitry. In this mode input termination for both channels are driven to Hi-Z. In Rx
Detect mode device power is <10mW (TYP) or less than 5% of its normal operating power . This feature is
very useful in saving system power in mobile applications like notebook PC where battery life is critical.
Anytime an upstream device gets reconnected the redriver automatically senses the connection and goes to
normal operating mode. This operation requires no setting to the device.
3. U2/U3 Mode
With the help of internal timers the device tracks when link enters USB 3.0 low power modes U2 and U3; in
these modes link is in electrical idle state. LVPE502CP will selectively turn-off internal circuitry to save on
power. Typical power saving is about 75% lower than normal operating mode. The device will automatically
revert to active mode when signal activity (LFPS) is detected.
Receiver Detection
At Power Up or Reset
After power-up or anytime EN_RXD is toggled, RX.Detect cycle is performed by first setting Rx termination for
each channel to Hi-Z, device then starts sensing for receiver termination that may be attached at the other end of
each TX.
If receiver is detected on both channel
• The TX and RX terminations are switched to ZDIFF_TX, ZDIFF_RX respectively.
If
•
•
•
no receiver is detected on one or both channels
The transmitter is pulled to Hi-Z
The channel is put in low power mode
Device attempts to detect Rx termination in 12 ms (TYP) interval until termination is found or device is put in
sleep mode
During U2/U3 Link State
Rx detection is also performed periodically when link is in U2/U3 states. However in these states during Rx
detection, input termination is not automatically disabled before performing Rx.Detect. If termination is found
device goes back to its low power state if termination is not found then device disables its input termination and
then jumps to power-up RX.Detect state.
10
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Electrical Idle Support
Electrical idle support is needed for low frequency periodic signaling (LFPS) used in USB 3.0 side band
communication. A link is in an electrical idle state when the TX± voltage is held at a steady constant value like
the common mode voltage. LVPE502CP detects an electrical idle state when RX± voltage at the device pin falls
below VRX_LFPS_DIFFp-p min. After detection of an idle state in a given channel the device asserts electrical
idle state in its corresponding TX. When RX± voltage exceeds VRX_LFPS_DIFFp-p max normal operation is
restored and output start passing input signal. Electrical idle exit and entry time is speccified at < 6ns.
TYPICAL EYE DIAGRAM AND PERFORMANCE CURVES
Measurement equipment details:
• Generator (source) LeCroy PERT3,
• Signal: 5Gbps, 1000mVp-p, 3.5 dB De-Emphasis
• Tj and Dj measurements based on CP0 (USB 3 compliance pattern) which is D0.0 or logical idle with SKP
sequences removed
• Rj measurements based on CP1 or D10.2 symbol containing alternating 0s and 1s at Nyquist frequency
• Oscilloscope (Sink) LeCroy 25GHz Real Time Oscilloscope
• LeCroy QualiPHY software used to measure jitter and collect compliance eye diagrams
Device Operating Conditions: VCC = 3.3 V, Temp = 25°C, EQx/DEx/OSx set to their default value when not
mentioned
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PLOT #1 FIXED OUTPUT TRACE +3m USB 3 CABLE WITH VARIABLE INPUT TRACE
LVPE 502CP
Input
Output = 4"
4mil
4 mil
3m
LeCroy 25 GHz
Realtime Scope
USB 3.0 Source
EQ
Output Deterministic Jitter - ps - (pk-pk)
140
Output Deterministic Jitter (Post Compliance Cable Channel and CTLE)
versus Input Trace Length ( output trace fixed at 4")
120
100
Dj Max Limit per USB 3.0 Spec
80
EQ = 0 dB
EQ = 7 dB
60
40
EQ = 15 dB
20
0
0
12
DE = 0dB
5
10
15
20
25
30
35
Input Trace Length (inches)
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40
45
50
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PLOT #2 FIXED INPUT TRACE WITH VARIABLE OUTPUT TRACE and +3m USB 3.0 CABLE
LVPE502CP
Input = 12"
Output
4mil
4 mil
3m
LeCroy 25 GHz
Realtime Scope
USB 3.0 Source
EQ = 7dB
DE = 0dB
Output Deterministic Jitter (Post Compliance Cable Channel and CTLE)
versus Output Trace Length--Measured with Device DE Fixed @0dB
90
Dj Max Limit per USB 3.0 Spec
Output Deterministic Jitter - ps - (pk-pk)
80
70
60
50
Input Trace = 12 inches
40
30
20
10
0
0
2
4
6
8
10
12
14
16
18
20
Output Trace Length (inches)
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PLOT #3 FIXED INPUT TRACE WITH VARIABLE OUTPUT TRACE and (No Cable)
LVPE 502CP
Input = 12"
Output
4mil
4 mil
LeCroy 25 GHz
Realtime Scope
USB 3.0 Source
EQ = 7dB
DE
Output Deterministic Jitter (Post CTLE) versus Output Trace Length
Input Trace Fixed at 12"
90
Output Deterministic Jitter - ps - (pk-pk)
80
Dj Max Limit per USB 3.0 Spec
70
DE = 0 dB
60
DE = -3.5 dB
50
DE = -6 dB
40
30
20
10
0
14
0
5
10
15
20
25
30
35
Input Trace Length (inches)
Submit Documentation Feedback
40
45
50
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s) :SN65LVPE502CP
SN65LVPE502CP
SLLSE79A – MARCH 2011 – REVISED SEPTEMBER 2011
www.ti.com
USB 3.0 MASK EYE DIAGRAM TEST
CASE I FIXED OUTPUT AND VARIABLE INPUT TRACE
DE= 0dB, EQ = 0dB, Input = 4" , Output = 4" + 3m Cable
DE= 0dB, EQ = 0dB, Input = 8” , Output = 4” + 3m Cable
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15
SN65LVPE502CP
SLLSE79A – MARCH 2011 – REVISED SEPTEMBER 2011
www.ti.com
DE= 0dB, EQ = 0dB, Input = 12” , Output = 4” + 3m Cable
DE= 0dB, EQ = 0dB, Input = 16” , Output = 4” + 3m Cable
DE= 0dB, EQ = 0dB, Input = 20” , Output = 4” + 3m Cable
16
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SN65LVPE502CP
SLLSE79A – MARCH 2011 – REVISED SEPTEMBER 2011
www.ti.com
DE= 0dB, EQ = 7dB, Input = 24” , Output = 4” + 3m Cable
DE= 0dB, EQ = 7dB, Input = 32” , Output = 4” + 3m Cable
DE= 0dB, EQ = 7dB, Input = 36” , Output = 4” + 3m Cable
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17
SN65LVPE502CP
SLLSE79A – MARCH 2011 – REVISED SEPTEMBER 2011
www.ti.com
DE= 0dB, EQ = 15dB, Input = 36” , Output = 4” + 3m Cable
DE= 0dB, EQ = 15dB, Input = 48” , Output = 4” + 3m Cable
CASE II FIXED INPUT AND VARIABLE OUTPUT TRACE+ 3m CABLE
DE= 0dB, EQ = 7dB, Input = 12” , Output = 4” + 3m Cable
18
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SN65LVPE502CP
SLLSE79A – MARCH 2011 – REVISED SEPTEMBER 2011
www.ti.com
DE= 0dB, EQ = 7dB, Input = 12” , Output = 8” + 3m Cable
DE= 0dB, EQ = 7dB, Input = 12” , Output = 12” + 3m Cable
DE= 0dB, EQ = 7dB, Input = 12” , Output = 16” + 3m Cable
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Copyright © 2011, Texas Instruments Incorporated
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19
SN65LVPE502CP
SLLSE79A – MARCH 2011 – REVISED SEPTEMBER 2011
www.ti.com
DE= 0dB, EQ = 7dB, Input = 12” , Output = 20” + 3m Cable
CASE III FIXED INPUT AND VARIABLE OUTPUT TRACE (No Cable)
DE= 0dB, EQ = 7dB, Input = 12” , Output = 8”
DE= 0dB, EQ = 7dB, Input = 12” , Output = 32”
20
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Copyright © 2011, Texas Instruments Incorporated
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SN65LVPE502CP
SLLSE79A – MARCH 2011 – REVISED SEPTEMBER 2011
www.ti.com
DE= 0dB, EQ = 7dB, Input = 12” , Output = 36”
DE= -3.5dB, EQ = 7dB, Input = 12” , Output = 36”
DE= -6.0dB, EQ = 7dB, Input = 12” , Output = 40”
DE= -6.0dB, EQ = 7dB, Input = 12” , Output = 44”
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SN65LVPE502CP
SLLSE79A – MARCH 2011 – REVISED SEPTEMBER 2011
www.ti.com
REVISION HISTORY
Changes from Original (March 2011) to Revision A
Page
•
Changed the Block Diagram label From: CM/EN_RXD To: EN_RXD ................................................................................. 2
•
Changed From: CM To: RSVD in the THERMAL CHARACTERISTICS table Test Conditions ........................................... 3
•
Changed From: CM To: RSVD in the RECOMMENDED OPERATING CONDITIONS table Test Conditions .................... 4
•
Changed pin name From: CM To: RSVD in the Flow-Through Pin-Out illustration ............................................................. 8
•
Changed pin name and description From: CM To: RSVD in the Pin Functions table .......................................................... 9
•
Deleted CM and Device Functions columns from the Control Pins Settings of Table 2 ...................................................... 9
•
Deleted the USB Compliance Mode section ...................................................................................................................... 11
22
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PACKAGE OPTION ADDENDUM
www.ti.com
20-Sep-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
SN65LVPE502CPRGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
SN65LVPE502CPRGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Sep-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN65LVPE502CPRGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
SN65LVPE502CPRGET
VQFN
RGE
24
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Sep-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65LVPE502CPRGER
VQFN
RGE
24
3000
346.0
346.0
29.0
SN65LVPE502CPRGET
VQFN
RGE
24
250
190.5
212.7
31.8
Pack Materials-Page 2
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