TPD4E002 QUAD LOW-CAPACITANCE ARRAY WITH ±15-kV ESD PROTECTION www.ti.com SLVS615B – JULY 2006 – REVISED MARCH 2007 FEATURES APPLICATIONS • • • • • • • • Four Unidirectional Voltage Suppression Diodes for use in ESD Protection I/O Breakdown Voltage, VBR = 6.1 V Min Low I/O Capacitance (11 pF at 0 V) Low I/O Leakage Current <100 nA No Power Supply Routing is Required since there is no VDD Pin Very Small Printed Circuit Board (PCB) Area <2.6 mm2 ESD Protection Exceeds – ±15-kV Human Body Model (HBM) – ±15-kV IEC 61000-4-2 Contact Discharge Where Transient Overvoltage Protection in ESD-Sensitive Equipment is Required, Such as: – Computers – Printers – Communication Systems and Cellular Phones – Video Equipment BENEFITS • • • High ESD Protection Level High Integration Suitable for High-Density Boards DRL PACKAGE (TOP VIEW) IO1 1 5 IO4 GND 2 IO2 3 4 IO3 DESCRIPTION/ORDERING INFORMATION The TPD4E002 is a monolithic array designed to protect up to four lines against ESD transients. Monolithic circuit design allows superior matching between the channels and reduced crosstalk. This device is ideal for applications where both reduced line capacitance and board space-saving are required. ORDERING INFORMATION PACKAGE (1) TA –40°C to 125°C (1) 1.6 × 1.6 DRL ORDERABLE PART NUMBER Reel of 4000 TPD4E002DRLR TOP-SIDE MARKING 28S For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Absolute Maximum Ratings MIN VPP ESD discharge TJ Junction temperature Tstg Storage temperature range Top Operating temperature range MAX Human Body Model (HBM) ±15 IEC 61000-4-2 Contact Discharge ±15 UNIT kV 125 °C –55 150 °C –40 125 °C Thermal Resistance PARAMETER RθJA Junction to ambient on printed circuit on recommended pad layout VALUE UNIT 220 °C/W Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2007, Texas Instruments Incorporated TPD4E002 QUAD LOW-CAPACITANCE ARRAY WITH ±15-kV ESD PROTECTION www.ti.com SLVS615B – JULY 2006 – REVISED MARCH 2007 Electrical Characteristics Tamb = 25°C PARAMETER TEST CONDITIONS MIN 6.1 MAX UNIT I/O Breakdown voltage IR = 1 mA IRM I/O Leakage current VRM = 3 V αT Voltage temperature coefficient 45 10–4/°C C I/O Capacitance per line 11 pF Rd Dynamic resistance (1) 2 Ω (1) Rd is measured under reverse breakdown condition with inrush current in the range 1Amps using pulse technique TYPICAL CHARACTERISTICS 12.0 Capacitance (pF) 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 –40 0 25 70 85 125 Temperature (ºC) Figure 1. I/O Capacitance vs Temperature 12.0 Capacitance (pF) 11.5 11.0 10.5 10.0 9.5 9.0 1 2 3 4 5 6 7 8 9 Frequency (Mhz) Figure 2. I/O Capacitance vs Frequency (Typical Values) 2 TYP VBR Submit Documentation Feedback 10 7.2 V 0.1 µA TPD4E002 QUAD LOW-CAPACITANCE ARRAY WITH ±15-kV ESD PROTECTION www.ti.com SLVS615B – JULY 2006 – REVISED MARCH 2007 TYPICAL CHARACTERISTICS (continued) –110.0 –100.0 –90.0 –80.0 –70.0 –60.0 –50.0 –40.0 –30.0 IIN (mA) –20.0 –10.0 0.00 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0 100.0 110.0 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 500m 0 –500m –1.0 –1.5 VIN (V) Voltage (20 V/div) Figure 3. Diode Current Across I/O Voltage (Typical Values) Time (50 ns/div) Figure 4. ESD Clamp Voltage At I/O Pins: IEC6100-4-2 15 kV Contact Discharge Submit Documentation Feedback 3 PACKAGE OPTION ADDENDUM www.ti.com 17-May-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPD4E002DRLR ACTIVE SOT-553 DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPD4E002DRLRG4 ACTIVE SOT-553 DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 7-May-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device TPD4E002DRLR 7-May-2007 Package Pins DRL 5 Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) HNT 180 9 1.78 1.78 0.69 4 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) TPD4E002DRLR DRL 5 HNT 201.0 192.0 26.0 Pack Materials-Page 2 W Pin1 (mm) Quadrant 8 Q3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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