NTE6821 Integrated Circuit Peripheral Interface Adapter (PIA), NMOS, 1MHz Description: The NTE6821 is a peripheral interface adapter (PIA) in a 40–Lead DIP type package capable of interfacing the Microprocessing Unit (MPU) to peripherals through two 8–Bit bidirectional peripheral data buses and four control lines. No external logic is required for interfacing to most peripheral devices. The functional configuration of the PIA is programmed by the MPU during system initialization. Each of the peripheral data lines can be programmed to act as an input or output, and each of the four control/interrupt lines may be programmed for one of several control modes. This allows a high degree of flexibility in the over–all operation of the interface. Features: D 8–Bit Bidirectional Data Bus for Communication with the MPU D Two Bidirectional 8–Bit Buses for Interface to Peripherals D Two Programmed Control Registers D Two Programmed Data Direction Registers D Four Individually–Controlled Interrupt Input Lines; Two Usable as Peripheral Control Outputs D Handshake Control Logic for Input and Output Peripheral Operation D High–Impedance 3–State and Direct Transistor Drive Peripheral Lines D Program Controlled Interrupt and Interrupt Disable Capability D CMOS Drive Capability on Side A Peripheral Lines D Two TTL Drive Capability on All A and B Side Buffers D TTL Compatible D Static Operation Absolute Maximum Ratings: (Note 1) Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to +7V Input Voltage, Vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to +7V Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° to +70°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55° to +150°C Thermal Resistance, Junction to Ambient, RΘJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.5°C/W Note 1. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance. Electrical Characteristics: (VCC = 5V ±5%, VSS = 0, TA = 0° to +70⁄C unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Bus Control Inputs (R/W, Enable, Reset, RS0, RS1, CS0, CS1, CS2) Input High Voltage VIH VSS +2.0 – VCC V Input Low Voltage VIL VSS –0.3 – VSS +0.8 V Input Leakage Current Iin Vin = 0 to 5.25V – 1.0 2.5 µA Capacitance Cin Vin = 0, TA = +25°C, f = 1MHz – – 7.5 pF Output Low Voltage VOL ILoad = 3.2mA – – VSS +0.4 V Output Leakage Current (Off State) ILOH VOH = 2.4V – 1.0 10 µA Capacitance Cout Vin = 0, TA = +25°C, f = 1MHz – – 5.0 pF Interrupt Outputs (IRQA, IRQB) Data Bus (D0 – D7) Input High Voltage VIH VSS +2.0 – VCC V Input Low Voltage VIL VSS –0.3 – VSS +0.8 V Three–State (Off State) Input Current ITSI Vin = 0.4 to 2.4V – 2.0 10 µA Output High Voltage VOH ILoad = –205µA VSS +2.4 – – V Output Low Voltage VOL ILoad = 1.6mA – – VSS +0.4 V Capacitance Cin Vin = 0, TA = +25°C, f = 1MHz – – 12.5 pF Vin = 0 to 5.25V – 1.0 2.5 µA Vin = 0.4 to 2.4V – 2.0 10 µA VIH = 2.4V –200 –400 – µA VO = 1.5V –1.0 – –10 mA VIL = 0.4V – –1.3 –2.4 mA ILoad = –200µA VSS +2.4 – – V ILoad = 10µA VCC –1.0 – – V Peripheral Bus (PA0 – PA7, PB0 – PB7, CA1, CA2, CB1, CB2) Input Leakage Current R/W, Reset, RS0, RS1, CS0, CS1, CS2, CA1, CB1, Enable Iin Three–State (Off State) Input Current PB0 – PB7, CB2 ITSI Input High Current PA0 – PA7, CA2 IIH Darlington Drive Current PB0 – PB7, CB2 IOH Input Low Current PA0 – PA7, CA2 IIL Output High Voltage PA0 – PA7, PB0 – PB7, CA2, CB2 VOH PA0 – PA7, CA2 Output Low Voltage VOL ILoad = 3.2mA – – VSS +0.4 V Capacitance Cin Vin = 0, TA = +25°C, f = 1MHz – – 10 pF – – 550 mW Power Requirements Power Dissipation PD Bus Timing Characteristics: (VCC = 5V ±5%, VSS = 0, TA = 0° to +70°C unless otherwise specified) Parameter Min Typ Max Unit tcycE 1000 – – ns Enable Pulse Width, High PWEH 450 – – ns Enable Pulse Width, Low PWEL 430 – – ns Enable Pulse Rise and Fall Times tEr, tEf – – 25 ns Enable Cycle Time Symbol Test Conditions Bus Timing Characteristics (Cont’d): (VCC = 5V ±5%, VSS = 0, TA = 0° to +70°C unless otherwise specified) Parameter Symbol Setup Time, Address and R/W Valid to Enable Positive Transition Min Typ Max Unit tAS 160 – – ns Address Hold Time tAH 10 – – ns Data Delay Time, Read tDDR – – 320 ns Data Hold Time, Read tDHR 10 – – ns Data Setup Time, Write tDSW 195 – – ns data Hold Time, Write tDHW 10 – – ns Peripheral Timing Characteristics: Test Conditions (VCC = 5V ±5%, VSS = 0, TA = 0° to +70°C unless otherwise specified) Parameter Symbol Min Max Unit Peripheral Data Setup Time tPDSU 200 – ns Peripheral Data Hold Time tPDH 0 – ns Delay Time, Enable negative transition to CA2 negative transition tCA2 – 1.0 µs Delay Time, Enable negative transition to CA2 positive transition tRS1 – 1.0 µs Rise and fall Times for CA1 and CA2 input signals tr, tf – 1.0 µs Delay Time from CA1 active transition to CA2 positive transition tRS2 – 2.0 µs Delay Time, Enable negative transition to Peripheral Data Valid tPDW – 1.0 µs Delay Time, Enable negative transition to Peripheral CMOS Data Valid PA0 – PA7, CA2 tCMOS – 2.0 µs Delay Time, Enable positive transition to CB2 negative transition tCB2 – 1.0 µs Delay Time, Peripheral Data Valid to CB2 negative transition tDC 20 – ns Delay Time, Enable positive transition to CB2 postivie transition tRS1 – 1.0 µs Peripheral Control Output Pulse Width, CA2/CB2 PWCT 550 – ns Rise and Fall Time for CB1 and CB2 input signals tr, tf – 1.0 µs Delay Time, CB1 active transition to CB2 positive transition tRS2 – 2.0 µs tIR – 2.0 µs Interrupt Response Time tRS3 – 1.0 µs Interrupt Input Pulse Width PWI 500 – ns Reset Low Time (Note 2) tRL 1.0 – µs Interrupt Release Time, IRQA and IRQB Note 2. The Reset line must be high a minimum of 1.0µs before addressing the PIA. Expanded Block Diagram D0 D1 D2 D3 D4 D5 D6 D7 38 33 32 31 30 29 28 27 26 Interrupt Status Control A Control Register A (CRA) VCC = PIN20 VSS = PIN1 CS0 CS1 CS2 RS0 RS1 R/W Enable Reset 22 24 23 36 35 21 25 34 Peripheral Interface A 2 3 4 5 6 7 8 9 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 Peripheral Interface B 10 11 12 13 14 15 16 17 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 Output Register B (ORB) Chip Select and R/W Control Data Direction Register B (DDRB) Control Register B (CRB) IRQB 39 CA2 Output Bus Output Register A (ORA) Bus Input Register (BIR) 40 CA1 Data Direction Register A (DDRA) Data Bus Buffers (DBB) Input Bus IRQA Interrupt Status Control B 37 Pin Connection Diagram VSS 1 40 CA1 PA0 2 39 CA2 PA1 3 38 IRQA PA2 4 37 IRQB PA3 5 36 RS0 PA4 6 PA5 7 35 RS1 34 RESET PA6 8 33 D0 PA7 9 32 D1 PB0 10 31 D2 PB1 11 PB2 12 30 D3 PB3 13 PB4 14 28 D5 27 D6 PB5 15 26 D7 PB6 16 25 E PB7 17 24 CS1 CB1 18 CB2 19 23 CS2 22 CS0 VCC 20 21 R/W 29 D4 18 CB1 19 CB2 40 21 1 20 .550 (13.9) Max 2.055 (52.2) .155 (3.9) .100 (2.54) .019 (0.5) .137 (3.5) .650 (16.5)