E2G0146-18-11 ¡ Semiconductor MD51V65165 ¡ Semiconductor This version:MD51V65165 Mar. 1998 4,194,304-Word ¥ 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO DESCRIPTION The MD51V65165 is a 4,194,304-word ¥ 16-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MD51V65165 achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MD51V65165 is available in a 50-pin plastic SOJ or 50-pin plastic TSOP. FEATURES • 4,194,304-word ¥ 16-bit configuration • Single 3.3 V power supply, ±0.3 V tolerance • Input : LVTTL compatible, low input capacitance • Output : LVTTL compatible, 3-state • Refresh : RAS-only refresh : 4096 cycles/64 ms CAS before RAS refresh, hidden refresh : 4096 cycles/64 ms • Fast page mode with EDO, read modify write capability • CAS before RAS refresh, hidden refresh, RAS-only refresh capability • Package options: 50-pin 400 mil plastic SOJ (SOJ50-P-400-0.80) (Product : MD51V65165-xxJA) 50-pin 400 mil plastic TSOP (TSOPII50-P-400-0.80-1K) (Product : MD51V65165-xxTA) xx indicates speed rank. PRODUCT FAMILY Family Access Time (Max.) tRAC tAA tCAC tOEA Cycle Time Power Dissipation (Min.) Operating (Max.) Standby (Max.) MD51V65165-50 50 ns 25 ns 13 ns 13 ns 84 ns 504 mW MD51V65165-60 60 ns 30 ns 15 ns 15 ns 104 ns 432 mW 1.8 mW 1/16 ¡ Semiconductor MD51V65165 PIN CONFIGURATION (TOP VIEW) VCC 1 DQ1 2 DQ2 3 DQ3 4 DQ4 5 VCC 6 DQ5 7 DQ6 8 DQ7 9 DQ8 10 NC 11 VCC 12 WE 13 50 VSS DQ1 2 49 DQ16 48 DQ15 DQ2 3 48 DQ15 47 DQ14 DQ3 4 47 DQ14 46 DQ13 DQ4 5 46 DQ13 VCC 6 45 VSS 44 DQ12 DQ5 7 44 DQ12 43 DQ11 DQ6 8 43 DQ11 42 DQ10 DQ7 9 42 DQ10 41 DQ9 DQ8 10 41 DQ9 40 NC NC 11 40 NC 39 VSS VCC 12 39 VSS 38 LCAS WE 13 38 LCAS 37 UCAS RAS 14 37 UCAS NC 15 36 OE NC 15 36 OE NC 16 35 NC NC 16 35 NC NC 17 34 NC NC 17 34 NC NC 18 33 NC NC 18 33 NC A0 19 32 A11R A0 19 32 A11R A1 20 31 A10R A1 20 31 A10R A2 21 30 A9 A2 21 30 A9 A3 22 29 A8 A3 22 29 A8 A4 23 28 A7 A4 23 28 A7 A5 24 27 A6 A5 24 27 A6 VCC 25 26 VSS VCC 25 26 VSS 50-Pin Plastic SOJ Pin Name A0 - A9, A10R, A11R RAS 50-Pin Plastic TSOP (K Type) Function Address Input Row Address Strobe LCAS Lower Byte Column Address Strobe UCAS Upper Byte Column Address Strobe DQ1 - DQ16 Note : 50 VSS 49 DQ16 45 VSS RAS 14 VCC 1 Data Input/Data Output OE Output Enable WE Write Enable VCC Power Supply (3.3 V) VSS Ground (0 V) NC No Connection The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 2/16 ¡ Semiconductor MD51V65165 BLOCK DIAGRAM RAS WE Timing Generator I/O Controller LCAS UCAS I/O Controller 10 Column Address Buffers Internal Address Counter A0 - A9 10 A10R, A11R OE 2 10 Refresh Control Clock Row Row Address 12 DecoBuffers ders Word Drivers Output Buffers 8 Input Buffers 8 8 Input Buffers 8 8 Output Buffers 8 DQ1 - DQ8 Column Decoders Sense Amplifiers 8 16 I/O Selector 16 Memory Cells DQ9 - DQ16 8 VCC On Chip VBB Generator On Chip IVCC Generator VSS 3/16 ¡ Semiconductor MD51V65165 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Unit Symbol Rating Voltage on Any Pin Relative to VSS VT –0.5 to 4.6 V Short Circuit Output Current IOS 50 mA Power Dissipation PD* 1 W Operating Temperature Topr 0 to 70 °C Storage Temperature Tstg –55 to 150 °C *: Ta = 25°C Recommended Operating Conditions Parameter Power Supply Voltage (Ta = 0°C to 70°C) Symbol Min. Typ. Max. Unit VCC 3.0 3.3 3.6 V VSS 0 0 0 V Input High Voltage VIH 2.0 — VCC + 0.3 V Input Low Voltage VIL –0.3 — 0.8 V Capacitance (VCC = 3.3 V ±0.3 V, Ta = 25°C, f = 1 MHz) Symbol Typ. Max. Unit Input Capacitance (A0 - A9, A10R, A11R) CIN1 — 5 pF Input Capacitance (RAS, LCAS, UCAS, WE, OE) CIN2 — 7 pF Output Capacitance (DQ1 - DQ16) CI/O — 7 pF Parameter 4/16 ¡ Semiconductor MD51V65165 DC Characteristics Parameter (VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C) Symbol Condition MD51V65165 -50 MD51V65165 -60 Min. Max. Min. Max. Unit Note Output High Voltage VOH IOH = –2.0 mA 2.4 VCC 2.4 VCC V Output Low Voltage VOL IOL = 2.0 mA 0 0.4 0 0.4 V Input Leakage Current ILI –10 10 –10 10 mA –10 10 –10 10 mA — 140 — 120 mA 1, 2 — 1 — 1 — 0.5 — 0.5 — 140 — 120 — 5 — 5 — 140 — 120 mA 1, 2 — 140 — 120 mA 1, 3 0 V £ VI £ VCC + 0.3 V; All other pins not under test = 0 V Output Leakage Current ILO Average Power Supply Current ICC1 (Operating) Power Supply Current (Standby) Current (Standby) (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) tRC = Min. ≥ VCC –0.2 V mA 1 RAS cycling, ICC3 CAS = VIH, mA 1, 2 tRC = Min. RAS = VIH, ICC5 CAS = VIL, mA 1 DQ = enable Average Power Supply Current RAS, CAS cycling, ICC2 RAS, CAS (RAS-only Refresh) Power Supply 0 V £ VO £ VCC RAS, CAS = VIH Average Power Supply Current DQ disable ICC6 RAS cycling, CAS before RAS RAS = VIL, ICC7 CAS cycling, tHPC = Min. Notes : 1. ICC Max. is specified as ICC for output open condition. 2. The address can be changed once or less while RAS = VIL. 3. The address can be changed once or less while CAS = VIH. 5/16 ¡ Semiconductor MD51V65165 AC Characteristics (1/2) (VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C) Note 1, 2, 3 Parameter Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Symbol MD51V65165 -50 MD51V65165 -60 Unit Note Min. Max. Min. Max. — — — 104 135 25 — — — ns tRWC tHPC 84 110 20 tHPRWC 58 — 68 — ns tRC ns ns tRAC — 50 — 60 ns 4, 5, 6 Access Time from CAS tCAC — 13 — 15 ns 4, 5 Access Time from Column Address Access Time from CAS Precharge tAA tCPA — — 25 30 — — 30 35 ns ns 4, 6 4, 13 Access Time from OE Output Low Impedance Time from CAS tOEA tCLZ — 0 13 — — 0 15 — ns ns 4 4 Data Output Hold After CAS Low tDOH 5 — 5 — ns CAS to Data Output Buffer Turn-off Delay Time tCEZ RAS to Data Output Buffer Turn-off Delay Time tREZ 0 13 0 13 0 15 15 ns 0 ns 7, 8 7, 8 OE to Data Output Buffer Turn-off Delay Time tOEZ WE to Data Output Buffer Turn-off Delay Time tWEZ 0 0 13 13 0 0 15 15 ns ns 7 7 Transition Time Refresh Period tT tREF 1 — 50 64 1 — 50 64 ns ms 3 RAS Precharge Time tRP 30 — 40 — ns RAS Pulse Width tRAS 50 10,000 60 10,000 ns RAS Pulse Width (Fast Page Mode with EDO) tRASP 50 100,000 60 100,000 ns RAS Hold Time RAS Hold Time referenced to OE tRSH tROH 7 7 — — 10 — — ns 10 CAS Precharge Time (Fast Page Mode with EDO) tCP 7 — 10 — ns ns 15 CAS Pulse Width tCAS 7 10,000 10 10,000 ns CAS Hold Time CAS to RAS Precharge Time tCSH tCRP 35 5 — — 40 5 — — ns ns RAS Hold Time from CAS Precharge tRHCP — — 35 5 — — ns ns 13 5 6 13 OE Hold Time from CAS (DQ Disable) tCHO 30 5 RAS to CAS Delay Time RAS to Column Address Delay Time tRCD tRAD 11 9 37 25 14 12 45 30 ns ns Row Address Set-up Time tASR 0 — 0 — ns Row Address Hold Time tRAH 7 — 10 — ns Column Address Set-up Time tASC 0 — 0 — ns 12 Column Address Hold Time Column Address to RAS Lead Time tCAH tRAL 7 25 — — 10 30 — — ns ns 12 6/16 ¡ Semiconductor MD51V65165 AC Characteristics (2/2) (VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C) Note 1, 2, 3 Parameter Symbol MD51V65165 -50 MD51V65165 -60 Unit Note Min. Max. Min. Max. Read Command Set-up Time tRCS 0 — 0 — ns 12 Read Command Hold Time Read Command Hold Time referenced to RAS tRCH tRRH 0 0 — — 0 0 — — ns ns 9, 12 9 Write Command Set-up Time tWCS 0 — 0 — ns 10, 12 Write Command Hold Time tWCH 7 — 10 — ns 12 Write Command Pulse Width tWP 7 — 10 — ns WE Pulse Width (DQ Disable) tWPE 7 — 10 — ns OE Command Hold Time tOEH — — 10 10 — — ns OE Precharge Time tOEP 7 7 OE Command Hold Time tOCH 7 — 10 — ns Write Command to RAS Lead Time tRWL Write Command to CAS Lead Time tCWL 7 7 — — 10 10 — — ns ns ns ns ns 11, 12 11, 12 ns ns ns 10 10 10 tDS 0 — 0 — Data-in Hold Time OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time tDH tOED tCWD tAWD RAS to WE Delay Time tRWD 7 13 30 42 67 — — — — — 10 15 34 49 79 — — — — — CAS Precharge WE Delay Time Data-in Set-up Time ns 14 tCPWD 47 — 54 — ns 10 CAS Active Delay Time from RAS Precharge tRPC 5 — 5 — ns 12 RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) WE to RAS Precharge Time (CAS before RAS) WE Hold Time from RAS (CAS before RAS) tCSR tCHR tWRP tWRH 5 10 10 10 — — — — 5 10 10 10 — — — — ns ns ns 12 13 ns 7/16 ¡ Semiconductor Notes: MD51V65165 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 2 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 1 TTL load and 100 pF. The output timing reference levels are VOH = 2.0 V and VOL = 0.8 V. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tCEZ (Max.), tREZ (Max.), tWEZ (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tCEZ and tREZ must be satisfied for open circuit condition. 9. tRCH or tRRH must be satisfied for a read cycle. 10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to the UCAS and LCAS, leading edges in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 12. These parameters are determined by the falling edge of either UCAS or LCAS, whichever is earlier. 13. These parameters are determined by the rising edge of either UCAS or LCAS, whichever is later. 14. tCWL should be satisfied by both UCAS and LCAS. 15. tCP is determined by the time both UCAS and LCAS are high. 8/16 E2G0115-17-41S , ,, , , ,, ¡ Semiconductor MD51V65165 TIMING WAVEFORM Read Cycle tRC tRP tRAS VIH – RAS VIL – tCRP tCSH tCRP tRCD VIH – CAS VIL – tRAD tASR Address VIH – VIL – tRSH tCAS tRAH tASC tRAL tCAH Column Row tRCS WE OE VIH – VIL – tAA tROH tREZ tOEA VIH – VIL – tCAC tRAC DQ VOH – tOEZ Open VOL – tRCH tRRH tCEZ Valid Data-out tCLZ "H" or "L" Write Cycle (Early Write) tRC tRP tRAS RAS VIH – VIL – tCRP tCRP CAS VIH – VIL – VIH – VIL – tASC Row tCAS tCAH tRAL Column tWCS WE tRSH tRAD tRAH tASR Address tCSH tRCD VIH – tWCH tWP tCWL VIL – tRWL OE VIH – VIL – tDS DQ VIH – VIL – tDH Valid Data-in Open "H" or "L" 9/16 ¡ Semiconductor MD51V65165 Read Modify Write Cycle tRWC tRAS VIH – RAS VIL – tCRP tCSH tCRP CAS tRP tRCD tRSH tCAS VIH – VIL – , tASR Address VIH – VIL – WE VIH – VIL – OE VIH – VIL – tRAH tASC tCAH Column Row tRAD tRWD tAA tAWD tRCS tOEA tOED tCAC tRAC DQ VI/OH– VI/OL– tCWL tRWL tWP tCWD tCLZ tOEZ Valid Data-out tOEH tDS tDH Valid Data-in "H" or "L" 10/16 ,, ,, , , ¡ Semiconductor MD51V65165 Fast Page Mode Read Cycle (Part-1) tRASP RAS VIH – VIL – tRHCP tCRP CAS WE tHPC tRCD tCP tCP tCAS VIH – VIL – tCAS tCAS tRAD tASR Address tRP VIH – VIL – tASC tRAH Row tCSH tCAH tASC Column tASC tCAH tCAH Column Column tRCS tRRH VIH – VIL – tCHO tAA OE DQ tOCH tRAC tOEP tCPA tOEA tCAC VOH – VOL – tDOH tOEA tOEA tCAC tOEZ tCAC Valid Data-out Valid Data-out tCLZ tOEP tAA tAA VIH – VIL – tOEZ Valid* Data-out * : Same Data, tREZ Valid* Data-out "H" or "L" Fast Page Mode Read Cycle (Part-2) tRASP RAS VIH – VIL – tRHCP VIH VIL VIH – VIL – WE VIH – VIL – OE DQ tCP tRAH tCSH tASC tCAH Row tASC Column tCAH Column tRCS tCAS tASC tCAH Column tRCS tRAC tAA VIH – VIL – VOH – VOL – tCP tCAS tRAD tASR Address tRCD tCAS – – tCRP tHPC tCRP CAS tRP tRCH tWPE tAA tAA tCPA tOEA tCAC tCLZ tCAC tWEZ Valid Data-out tCAC tDOH Valid Data-out tCEZ Valid Data-out "H" or "L" 11/16 ,,, , , ¡ Semiconductor MD51V65165 Fast Page Mode Write Cycle (Early Write) tRP tRASP RAS VIH – VIL – tCRP CAS tRAD tRAH tASR VIH – VIL – WE VIH – VIL – OE VIH – VIL – tASC Column tWCS VIH – VIL – tCAS tCAH tASC Column tWCH tDS DQ tCP tCAS tCSH tASC tCAH Row tHPC tCP tCAS VIH – VIL – Address tHPC tRCD tWCS tDH Valid Data-in Column tWCH tDS tRSH tCAH tDH Valid Data-in tWCS tWCH tDS tDH Valid Data-in "H" or "L" Fast Page Mode Read Modify Write Cycle tRASP RAS tRWD VIH – VIL – tCRP CAS VIH – VIL – VIH – VIL – tCWD tRAD tASR Address tCP tRCD Row tCWL tCAH tRCS tAWD VIH – VIL – tAWD tDS tWP VIH – VIL – tCAC VI/OH – VI/OL – tOED tOEZ Valid Data-out tCLZ tRWL tCWD tRAC tOEA DQ tCPA tCAH Column tAA OE tASC Column tRCS WE tCPWD tHPRWC tRAH tASC tAA tOEH tDS tOED tOEA tCAC tDH Valid Data-in tOEZ Valid Data-out tCLZ tWP tOEH tDH Valid Data-in "H" or "L" 12/16 \] , ¡ Semiconductor MD51V65165 RAS-Only Refresh Cycle tRC RAS CAS Address VIH – VIL – VIH – VIL – tRP tRAS tCRP tRPC tASR VIH – tRAH Row VIL – tCEZ DQ VOH – Open VOL – Note: WE, OE = "H" or "L" "H" or "L" CAS before RAS Refresh Cycle tRC t RP RAS tRP tRAS VIH – VIL – t RPC tRPC tCP CAS tCSR tCHR VIH – VIL – tWRP WE VIH – VIL – DQ VOH – VOL – tWRP tWRH t CEZ Open Note: OE, Address = "H" or "L" "H" or "L" 13/16 ¡ Semiconductor MD51V65165 ,,, ,, , , ,, Hidden Refresh Read Cycle tRC tRAS RAS CAS VIH – VIL – tCRP VIH – VIL – tASR Address WE OE VIH – VIL – tRSH tRCD tRAD tASC Row tCHR Column tRCS tRRH tRAL VIH – VIL – tAA tROH tOEA VIH – VIL – VOH – VOL – tRP tCAH tRAH tRAC DQ tRC tRAS tRP tWRP tWRH tCEZ tCAC tCLZ tOEZ Open tREZ Valid Data-out "H" or "L" Hidden Refresh Write Cycle tRC tRAS RAS CAS Address VIH – VIL – VIH – VIL – VIH – VIL – tCRP tASR tRCD tRAD tASC tRAH VIH – VIL – OE VIH – VIL – DQ VIH – VIL – tRSH tCAH tRP tCHR tRAL Column Row tWCS WE tRC tRAS tRP tRWL tWCH tWP tDS tDH Valid Data-in "H" or "L" 14/16 ¡ Semiconductor MD51V65165 PACKAGE DIMENSIONS (Unit : mm) SOJ50-P-400-0.80 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 15/16 ¡ Semiconductor MD51V65165 (Unit : mm) TSOPII50-P-400-0.80-1K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.61 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 16/16