DATA SHEET O K I A S I C P R O D U C T S MG113P/114P/115P/73P/74P/75P 0.25µm Sea of Gates and Customer Structured Arrays November 1999 ■ ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– Oki Semiconductor MG113P/114P/115P/73P/74P/75P 0.25µm Sea of Gates and Customer Structured Arrays DESCRIPTION Oki’s 0.25µm Application-Specific Integrated Circuit (ASIC) products are available in both Sea Of Gates (SOG) and Customer Structured Array (CSA) architectures. Both the SOG-based MG115P series and the CSA-based MG75P series use a five-layer metal process on 0.25µm drawn (0.18µm L-effective) CMOS technology. The SOG MG113P/114P series uses the same SOG base-array architecture as the MG115P series, but offers four and three metal layers, respectively. The MG73P/74P CSA series uses three and four metal layers, respectively. The semiconductor process is adapted from Oki’s production-proven 64Mbit DRAM manufacturing process. The 0.25µm family provides significant performance, density, and power improvement over previous 0.30 and 0.35µm technologies. An innovative 4-transistor cell structure, licensed from In-Chip Systems, Inc., provides 30 to 50% less power and 30 to 50% more usable gates than traditional cell designs. The Oki 0.25µm family operates using 2.5-V VDD core with optimized 3-V I/O buffers. The 3-, 4-, and 5-layer metal MG113P/114P/115P SOG series contains 4 array bases, offering up to 588 I/O pads and over 2.4M raw gates. The 3-, 4-, and 5-layer metal MG73P/74P/75P CSA series contains 21 array bases, offering up to 868 I/O pads and over 5.4M raw gates. These SOG and CSA array sizes are designed to fit the most popular quad flat pack (QFP), low profile QFPs (LQFPs), thin QFPs (TQFPs), and plastic ball grid array (PBGA) packages. The MG113P/114P/115P series SOG architecture allows rapid prototyping turnaround times (TATs), additionally offering the most cost-effective solution for pad-limited circuits (particularly the 3-layer metal MG113P series). The 3-layer-metal MG73P, 4-layer-metal MG74P and 5-layer-metal MG75P CSA series contains 21 array bases, offering a wider span of gate and I/O counts than the SOG series. Oki uses the Artisan Components memory compiler which provides high performance, embedded synchronous single- and dual-port RAM macrocells for CSA designs. As such, the MG73P/74P/75P series is suited to memory-intensive ASICs and high-volume designs where fine tuning of package size produces significant cost or real-estate savings. Oki Semiconductor 1 ■ MG113P/114P/115P/73P/74P/75P ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– FEATURES • • • • • • • • • 2 0.25µm drawn 3-, 4-, and 5-layer metal CMOS Optimized 2.5-V core Optimized 3-V I/O SOG and CSA architecture availability 77-ps typical gate propagation delay (for a 4xdrive inverter gate with a fanout of 2 and 0 mm of wire, operating at 2.5 V) Over 5.4M raw gates and 868 I/O pads using 60µ staggered I/O User-configurable I/O with VSS, VDD, TTL, 3-state, and 1- to 24-mA options Slew-rate-controlled outputs for low-radiated noise H-clock tree cells which reduces the maximum skew for clock signals Oki Semiconductor • Low 0.2µW/MHz/gate power dissipation • User-configurable single- and dual-port memories • Specialized IP cores and macrocells including 32-bit ARM7TDMI CPU, phase-locked loop (PLL), and peripheral component interconnect (PCI) cells • Floorplanning for front-end simulation, backend layout controls, and link to synthesis • Joint Test Action Group (JTAG) boundary scan and scan path Automatic Test Pattern Generation (ATPG) • Support for popular CAE systems including Cadence, IKOS, Mentor Graphics, Model Technology, Inc. (MTI), Synopsys, and Viewlogic ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ MG113P/114P/115P/73P/74P/75P ■ MG113P/114P/115P/73P/74P/75P FAMILY LISTING 60µm Staggered PAD products SOG Base Array MG11xP14 MG11xP18 MG11xP22 MG11xP28 EA Base Array No. of Pads No. of Rows No. of Columns No. of Raw Gates MG113P/73P Family 3LM Usable Gates MG114P/74P Family 4LM Usable Gates MG115P/75P Family 5LM Usable Gates 22,344 MG7xPB02 68 84 280 23,520 22,344 MG7xPB04 108 144 480 69,120 65,664 65,664 MG7xPB06 148 204 680 138,720 131,784 131,784 MG7xPB08 188 264 880 232,320 218,381 220,704 MG7xPB10 228 324 1,080 349,920 311,429 332,424 MG7xPB12 268 384 1,280 491,520 412,877 466,944 MG7xPB14 308 444 1,480 657,120 MG7xPB16 348 504 1,680 846,720 MG7xPB18 388 564 1,880 1,060,320 MG7xPB20 428 624 2,080 1,297,920 MG7xPB22 468 684 2,280 1,559,920 MG7xPB24 508 744 2,480 1,845,120 MG7xPB26 548 804 2,680 2,154,720 MG7xPB28 588 864 2,880 2,488,320 MG7xPB30 628 924 3,080 MG7xPB32 668 984 MG7xPB34 708 1,044 MG7xPB36 748 MG7xPB38 387,701 572,573 732,974 1,094,861 519,125 611,122 635,040 745,114 763,430 901,272 882,586 1,025,357 982,498 1,154,045 1,107,072 1,310,035 1,249,738 1,465,210 1,393,459 1,642,291 2,845,920 1,536,797 1,821,389 3,280 3,227,520 1,678,310 2,001,062 3,480 3,633,120 1,816,560 2,179,872 1,104 3,680 4,062,720 1,950,106 2,356,378 788 1,164 3,880 4,516,320 2,077,507 2,529,139 MG7xPB40 828 1,224 4,080 4,993,920 2,197,325 2,696,717 MG7xPB42 868 1,284 4,280 5,495,520 2,308,118 2,857,670 ARRAY ARCHITECTURE The primary components of a 0.25µm MG113P/114P/115P circuit include: • • • • • • • • • I/O base cells 60µm pad pitch Configurable I/O pads for VDD, VSS, or I/O (optimized 3-V I/O) VDD and VSS pads dedicated to wafer probing Separate power bus for output buffers Separate power bus for internal core logic and input buffers Core base cells containing N-channel and P-channel pairs, arranged in column of gates Isolated gate structure for reduced input capacitance and increased routing flexibility Innovative 4-transistor core cell architecture, licensed from In-Chip Systems, Inc Each array has 24 dedicated corner pads for power and ground use during wafer probing, with four pads per corner. The arrays also have separate power rings for the internal core functions (VDDC and VSSC) and output drive transistors (VDDO and VSSO). Oki Semiconductor 3 ■ MG113P/114P/115P/73P/74P/75P ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– I/O base cells Separate power bus (VDDC, VSSC) for internal core logic (2nd metal/3rd metal) Configurable I/O pads for VDD, VSS, or I/O 1, 2, 3, 4, or 5 layer metal interconnection in core area Core base cell with 4 transistors VDD, VSS pads (4) in each corner for wafer probing only Separate power bus (VDDO, VSSO) over I/O cell for output buffers (2nd metal/3rd metal) Figure 7. MG115P Array Architecture MG73P/74P/75P CSA Layout Methodology The procedure to design, place, and route a CSA follows. 1. Select suitable base array frame from the available predefined sizes. To select an array size: - Identify macrocell functions required and minimum array size to hold macrocell functions. - Add together all the area occupied by the required random logic and macrocells and select the optimum array. 2. Make a floor plan for the design’s megacells. - Oki Design Center engineers verify the master slice and review simulation. - Oki Design Center or customer engineers floorplan the array using Oki’s supported floorplanner or Cadence DP3 or Gambit GFP and customer performance specifications. - Using Oki CAD software, Design Center engineers remove the SOG transistors and replace them with diffused memory macrocells to the customer’s specifications. 4 Oki Semiconductor ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ MG113P/114P/115P/73P/74P/75P ■ Figure 8 shows an array base after placement of the optimized memory macrocells. High-density RAM Mega macrocells Figure 8. Optimized Memory Macrocell Floor Plan 3. Place and route logic into the array transistors. - Oki Design Center engineers use layout software and customer performance specifications to connect the random logic and optimized memory macrocells. Figure 9 marks the area in which placement and routing is performed with cross hatching. Figure 9. Random Logic Place and Route Oki Semiconductor 5 ■ MG113P/114P/115P/73P/74P/75P ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (VSS = 0 V, TJ = 25°C) [1] Symbol Rated Value VDD Core (2.5 V) -0.3 to +3.6 Parameter Power supply voltage VDD I/O (3.3 V) -0.3 to +4.6 Input voltage (Input Buffer) VI -0.3 to VDD +0.3 Output voltage (Output Buffer) VO -0.3 to VDD +0.3 Input current (Input Buffer) II -10 to +10 Output current per I/O (Output Buffer) IO -24 to +24 TSTG -65 to +150 Storage temperature Unit V mA °C 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions in the other specifications of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions (VSS = 0 V) Parameter Power supply voltage Junction temperature 6 Oki Semiconductor Symbol Rated Value VDD Core (2.5 V) +2.25 to +2.75 VDD I/O (3.3 V) +3.0 to +3.6 Tj -40 to +85 Unit V °C ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ MG113P/114P/115P/73P/74P/75P ■ DC Characteristics (VDD Core = 2.25 to 2.75 V, VDD I/O = 3.0 to 3.6 V, VSS = 0 V, Tj = -40° to +85°C) Rated Value Parameter Symbol Conditions Min. Typ. [1] Max. High-level input voltage VIH TTL input (normal), VDD = VDD I/O 2.0 – VDD +0.3 Low-level input voltage VIL TTL input (normal) -0.3 – 0.8 Vt+ TTL input TTL- level Schmitt Trigger input buffer Threshold voltage Vt- – 1.5 2.0 0.7 1.0 – 0.4 0.5 – VDD -0.2 – – 2.4 – – – – 0.2 ∆Vt Vt+ - Vt- High-level output voltage (Output buffer) VOH IOH = -100 µA, VDD = VDD I/O Low-level output voltage (Output buffer) VOL IOL = 100 µA IOL = 1, 2, 4, 6, 8, 12, 24 mA – – 0.4 High-level input current (Input buffer) IIH VIH = VDD – – 10 VIH = VDD (50-kΩ pull-down) 10 66 200 Low-level input current (Normal input buffer) IIL VIL = VSS -10 – 10 VIL = VSS (50-kΩ pull-up) -200 -66 -10 VIL = VSS (3-kΩ pull-up) -3.3 -1.1 -0.3 VOH = VDD -10 – 10 VOH = VDD (50-kΩ pull-down) 10 66 200 VOL = VSS -10 – 10 VOL = VSS (50-kΩ pull-up) -200 -66 -10 VOL = VSS (3-kΩ pull-up) -3.3 -1.1 -0.3 IOH = -1, -2, -4, -6, -8, -12, -24 mA 3-state output leakage current (Normal input buffer) IOZH IOZL Stand-by current [2] IDDQ Output open, VIH = VDD, VIL = VSS Design Dependent Unit V µA mA µA mA µA 1. Typical condition is VDD I/O = 3.3 V, VDD Core = 2.5 V, and Tj = 25°C on a typical process. 2. RAM/ROM should be in powerdown mode. Oki Semiconductor 7 ■ MG113P/114P/115P/73P/74P/75P ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– DC Characteristics (VDD Core = 2.25 to 2.75 V, VDD I/O = 3.0 to 3.6 V, VSS = 0 V, Tj = -40° to +125°C) Rated Value Parameter Conditions Min. High-level input voltage VIH TTL input (normal), VDD=VDD I/O 2.0 – VDD + 0.3 Low-level input voltage VIL TTL input (normal) -0.3 – 0.8 TTL- level Schmitt Trigger input buffer Threshold voltage Vt+ TTL input Vt∆Vt Vt+ - Vt- High-level output voltage (Output buffer) VOH IOH = -100 µA, VDD=VDD I/O Low-level output voltage (Output buffer) VOL High-level input current (Input buffer) IIH Low-level input current (Normal input buffer) IIL IOH = -1, -2, -4, -6, -8, -12, -24 mA 3-state output leakage current (Normal input buffer) IOZH IOZL Stand-by current [2] IDDQ IOL = 100 µA Oki Semiconductor Max. – 1.5 2.0 0.7 1.0 – 0.4 0.5 – VDD - 0.2 – – 2.35 – – – – 0.2 IOL = 1, 2, 4, 6, 8, 12, 24 mA – – 0.45 VIH = VDD – – 50 VIH = VDD (50-kΩ pull-down) 10 66 200 VIL = VSS -50 – 50 VIL = VSS (50-kΩ pull-up) -200 -66 -10 VIL = VSS (3-kΩ pull-up) -3.3 -1.1 -0.3 VOH = VDD -50 – 50 VOH = VDD (50-kΩ pull-down) 10 66 200 VOL = VSS -50 – 50 VOL = VSS (50-kΩ pull-up) -200 -66 -10 VOL = VSS (3-kΩ pull-up) -3.3 -1.1 -0.3 Output open, VIH = VDD, VIL = VSS 1. Typical condition is VDD I/O = 2.5 V, VDD Core = 2.5 V, and Tj = 25°C for a typical process. 2. RAM/ROM should be in powerdown mode. 8 Typ. [1] Symbol Design Dependent Unit V µA mA µA mA µA ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ MG113P/114P/115P/73P/74P/75P ■ DC Characteristics (VDD Core = 2.25 to 2.75 V, VDD I/O = 2.25 to 2.75 V, VSS = 0 V, Tj = -40° to +125°C) Rated Value Parameter Symbol Conditions Min. Typ. [1] Max. High-level input voltage VIH TTL input (normal), VDD=VDD I/O 1.7 - VDD + 0.3 Low-level input voltage VIL TTL input (normal) -0.3 - 0.7 TTL- level Schmitt Trigger input buffer Threshold voltage Vt+ TTL input (normal) Vt- - - 1.7 0.6 - - - 0.4 - VDD - 0.2 - - ∆Vt Vt+ - Vt- High-level output voltage (Output buffer) VOH IOH = -100 µA, VDD=VDD I/O Low-level output voltage (Output buffer) VOL High-level input current (Input buffer) IIH VIH = VDD Low-level input current (Normal input buffer) IIL VIL = VSS 3-state output leakage current (Normal input buffer) IOZH VOH = VDD IOZL VOL = VSS -50 Stand-by current [2] IDDQ IOH = -0.5, -1, -2, -3, -4, -6, -12 mA IOL = 100 µA IOL = -0.5, 1, 2, 3, 4, 6, 12 mA VIL = VSS (3-kΩ pull-up) VOL = VSS (3-kΩ pull-up) Output open, VIH = VDD, VIL = VSS 1.95 - - - - 0.2 - - 0.45 -50 - 50 -50 - 50 - -0.8 - -50 - 50 - 50 -0.8 - - Design Dependent Unit V µA mA µA mA µA 1. Typical condition is VDD I/O = 2.5 V, VDD Core = 2.5 V, and Tj = 25°C for a typical process. 2. RAM/ROM should be in powerdown mode. Oki Semiconductor 9 ■ MG113P/114P/115P/73P/74P/75P ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– AC Characteristics (Core VDD = 2.5 V, VSS = 0 V, Tj = 25°C) Parameter Internal gate propagation delay Driving Type Inverter 2-input NAND Conditions [1] [2] 1X 0.080 2X 0.072 4X 0.061 1X 2X F/O = 2, L = 0 mm VDD = 2.5 V 4X 2-input NOR Inverter 0.094 0.134 0.127 1X 0.204 2X 0.159 2X 0.274 0.183 0.136 1X 0.329 4X 0.219 Toggle frequency ns 0.108 F/O = 2, L = standard wire length VDD = 2.5 V 4X 2-input NOR Unit 0.118 4X 1X [3] 0.102 1X 4X 2-input NAND Rated Value F/O = 1, L = 0 mm 1100 MHz 1. Input transition time in 0.15 ns / 2.5 V. 2. Typical condition is VDD = 2.5 V and Tj = 25oC for a typical process. 3. Rated value is calculated as an average of the L-H and H-L delay times of each macro type on a typical process. AC Characteristics (I/O VDD = 3.3 V, VSS = 0 V, Tj = 25°C) Parameter Rated Value Unit F/O = 2, L = standard wire length Conditions 0.311 ns 4 mA CL = 20 pF 1.783 ns 8 mA CL = 50 pF 2.011 ns 12mA CL = 100 pF 2.562 ns 12 mA CL = 100 pF 3.325 (r) ns 12 mA CL = 100 pF 3.043 (f) ns Input buffer propagation delay Output buffer propagation delay Output buffer transition time [1] Push-pull Normal output buffer Push-pull Normal output buffer 1. Output rising and falling times are both specified over a 10 to 90% range. 10 Oki Semiconductor ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ MG113P/114P/115P/73P/74P/75P ■ MACRO LIBRARY Oki Semiconductor supports a wide range of macrocells and macrofunctions, ranging from simple hard macrocells for basic Boolean operations to large, user-parameterizable macrofunctions. The following figure illustrates the main classes of macrocells and macrofunctions available. Examples Basic Macrocells NANDs NORs Basic Macrocells with Scan Test Flip-Flops EXORs Latches Flip-Flops Combinational Logic Clock Tree Driver Macrocells Macrocells 3-V Output Macrocells MSI Macrocells Mega/Special Macrocells [1] 3-State Outputs Push-Pull Outputs Open Drain Outputs Slew Rate Control Outputs PCI Outputs Counters Shift Registers ARM7TDMI PLL Macro Library 3-V Input Macrocells 3-V Bi-Directional Macrocells Macrofunctions Inputs Inputs with Pull-Downs Inputs with Pull-Ups I/O PCI I/O Oscillator Macrocells Gated Oscillators Memory Macrocells SOG RAMs: Single-Port RAMs Dual-Port RAMs MSI Macrofunctions I/O with Pull-Downs I/O with Pull-Ups Optimized Diffused RAMs: Single-Port RAMs Dual-Port RAMs 4-Bit Register/Latches [1] Under development Figure 10. Oki Macrocell and Macrofunction Library Oki Semiconductor 11 ■ MG113P/114P/115P/73P/74P/75P ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– Macrocells for Driving Clock Trees Oki offers clock-tree drivers that minimize clock skew. The advanced layout software uses dynamic driver placement and sub-trunk allocation to optimize the clock-tree implementation for a particular circuit. Features of the clock-tree driver-macrocells include: • • • • • • • True RC back annotation of the clock network Automatic fan-out balancing Dynamic sub-trunk allocation Single clock tree driver logic symbol Automatic branch length minimization Dynamic driver placement Up to four clock trunks Clock Figure 11. Clock Tree Structure 12 Oki Semiconductor ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ MG113P/114P/115P/73P/74P/75P ■ OKI ADVANCED DESIGN CENTER CAD TOOLS Oki’s advanced design center CAD tools include support for the following: • • • • Floorplanning for front-end simulation and back-end layout control Clock tree structures improve first-time silicon success by eliminating clock skew problems JTAG Boundary scan support Power calculation which predicts circuit power under simulation conditions to accurately model package requirements Platform Operating System [1] Vendor Software/Revision [1] Description Cadence HP9000, 7xx IBM RS6000 Sun® [2] HP-UX AIX SunOS, Solaris Composer™ Verilog™ NC-Verilog™ Veritime™ Verifault™ Concept™ [3] Leapfrog™ Design capture Simulation Simulation Timing analysis Fault grading Design capture VHDL simulation IKOS HP9000, 7xx, Sun [2] HP-UX, SunOS, Solaris NSIM Gemini/Voyager Simulation Mentor Graphics™ HP9000, 7xx Sun [2] HP-UX SunOS, Solaris IDEA™ QuickVHDL QuickSim II™ DFT Advisor Fastscan Design capture VHDL simulation Logic simulation Test synthesis ATPG Model Technology Inc. (MTI) HP9000, 7xx Sun [2] PC HP-UX SunOS, Solaris Win/NT™ V-System VHDL simulation Synopsys (Interface to Mentor Graphics, VIEWLogic) IBM RS6000 HP9000, 7xx Sun [2] AIX HP-UX SunOS, Solaris Design Compiler™ HDL/VHDL Compiler™ Test Compiler™ VSS™ Compilation Design synthesis Test synthesis VHDL simulation PC Sun [2] Windows™, Win/NT™ [4] SunOS, Solaris Powerview™ Fusion HDL Simulation VHDL/Verilog™ Simulation Vendor VIEWLogic 1. 2. 3. 4. Contact Oki Application Engineering for current software versions. Sun or Sun-compatible. Sun and HP platform only. In development. Oki Semiconductor 13 ■ MG113P/114P/115P/73P/74P/75P ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– Design Process The following figure illustrates the overall IC design process, also indicating the three main interface points between external design houses and Oki ASIC Application Engineering. Level 1 [5] VHDL/HDL Description Test Vectors Synthesis CAE Front-End LSF[2] Floorplanning Gate-Level Simulation Level 2 Netlist Conversion (EDIF 200) Test Vector Conversion (Oki TPL [4]) Scan Insertion (Optional) TDC [3] CDC [1] Floorplanning Pre-Layout Simulation (Cadence Verilog) Level 2.5 [5] Layout Fault Simulation [6] Oki Interface Automatic Test Pattern Generation (Synopsys Test Compiler) Verification (Cadence DRACULA) Post-Layout Simulation (Cadence Verilog) Level 3 [5] Manufacturing Prototype Test Program Conversion [1] [2] [3] [4] [5] [6] Oki’s Circuit Data Check program (CDC) verifies logic design rules Oki’s Link to Synthesis Floorplanning toolset (LSF) transfers post-floorplanning timing for resynthesis Oki’s Test Data Check program (TDC) verifies test vector rules Oki’s Test Pattern Language (TPL) Alternate Customer-Oki design interfaces available in addition to standard level 2 Standard design process includes fault simulation Figure 12. Oki’s Design Process 14 Oki Semiconductor ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ MG113P/114P/115P/73P/74P/75P ■ Automatic Test Pattern Generation Oki’s 0.25µm ASIC technologies support ATPG using full scan-path design techniques, including the following: • • • • • • • • • Increases fault coverage ≥ 95% Uses Synopsys Test Compiler Automatically inserts scan structures Connects scan chains Traces and reports scan chains Checks for rule violations Generates complete fault reports Allows multiple scan chains Supports vector compaction ATPG methodology is described in detail in Oki’s 0.25µm Scan Path Application Note. Combinational Logic A FD1AS Scan Data In D C SD SS B FD1AS Q QN D C SD SS Q Scan Data Out QN Scan Select Figure 13. Full Scan Path Configuration Floorplanning Design Flow Oki offers two floorplanning tools for high-density ASIC design: Cadence DP3, and Gambit GFP. The two main purposes for Oki’s floorplanning tools are to: • Ensure conformance of critical circuit performance specifications • Shorten overall design TAT In a traditional design approach with synthesis tools, timing violations after prelayout simulation are fixed by manual editing of the netlist. This process is difficult and time consuming. Also, there is no physical cluster information provided in the synthesis tool, and so it is difficult to synthesize logic using predicted interconnection delay due to wire length. Synthesis tools may therefore create over-optimized results. To minimize these problems, Synopsys proposed a methodology called, “Links to Layout (LTL)”. Based on this methodology, Oki developed an interface between Oki’s Floorplanner and the Synopsys environment, called Link Synopsys to Floorplanner (LSF). As not every Synopsys user has access to the Synopsys Floorplan Management tool, Oki had developed the LSF system to support both users who can access Synopsys Floorplan Management and users who do not have access to Synopsys Floorplan Management. Oki Semiconductor 15 ■ MG113P/114P/115P/73P/74P/75P ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– More information on OKI’s floorplanning capabilities is available in Oki’s Application Note, Using Oki’s Floorplanner: Standalone Operation and Links to Synopsys. Incremental Optimization with Physical Information Initial Synthesis HDL Entry No Constraints Constraints Met? Yes Synthesis Invoke Import on Floorplanner Constraints Met? Gate Level Netlist (EDIF) No Incremental Floorplan Yes PDEF (Synopsis) Gate Level Netlist (EDIF) Initial Floorplan DSPF/Oki RC/ PDEF (Synopsys) Wire Load Model (Synopsys) Net Capacitance (Synopsys Script (Synopsys) Invoke Export on Floorplanner Invoke Delay Delay (SDF) Load Back-Annotation Files Constraints Met? No = In Synopsys DC/DA Yes = In Floorplanner Timing Optimization To Simulation and P&R Figure 14. LSF System Design Flow IEEE JTAG Boundary Scan Support Boundary scan offers efficient board-level and chip-level testing capabilities. Benefits resulting from incorporating boundary-scan logic into a design include: • • • • • • 16 Improved chip-level and board-level testing and failure diagnostic capabilities Support for testing of components with limited probe access Easy-to-maintain testability and system self-test capability with on-board software Capability to fully isolate and test components on the scan path Built-in test logic that can be activated and monitored An optional Boundary Scan Identification (ID) Register Oki Semiconductor ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ MG113P/114P/115P/73P/74P/75P ■ Oki’s boundary scan methodology meets the JTAG Boundary Scan standard, IEEE 1149.1-1990. Oki supports boundary scan on both Sea of Gates (SOG) and Customer Structured Array (CSA) ASIC technologies. Either the customer or Oki can perform boundary-scan insertion. More information is available in Oki’s JTAG Boundary Scan Application Note. (Contact the Oki Application Engineering Department for interface options.) PACKAGE OPTIONS TQFP, LQFP and QFP Package Menu LQFP Base Array Product Name I/O Pads [1] 144 176 TQFP QFP 208 208 240 100 MG7xPB02 68 ● MG7xPB04 108 ● MG7xPB06 148 ● MG7xPB08 188 MG7xPB10 228 MG7xPB12 ● 268 ● ● ● ● ● ● ● MG7xPB14 308 ● ● ● ● ● MG7xPB16 348 ● ● ● ● ● MG7xPB18 388 ● ● ● ● ● MG7xPB20 428 ● ● ● ● ● MG7xPB22 468 ● ● ● ● ● MG7xPB24 508 ● ● ● ● ● MG7xPB26 548 ● ● ● ● MG7xPB28 588 ● ● ● ● ● MG7xPB30 628 ● ● ● ● ● MG7xPB32 668 ● ● ● ● ● MG7xPB34 708 ● ● ● ● ● MG7xPB36 748 ● ● ● ● ● MG7xPB38 788 ● ● ● ● MG7xPB40 828 ● ● ● ● 868 ● ● ● ● Body Size (mm) 20 x 20 24 x 24 28 x 28 28 x 28 32 x 32 14 x 14 Lead Pitch (mm) 0.5 0.5 0.5 0.5 0.5 0.5 MG11xP14 MG11xP18 MG11xP22 MG11xP28 MG7xPB42 ● 1. I/O Pads can be used for input, output, bi-directional, power, or ground. ● = Available now Oki Semiconductor 17 ■ MG113P/114P/115P/73P/74P/75P ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– BGA Package Menu BGA Base Array MG11xP14 MG11xP18 MG11xP22 MG11xP28 Product Name I/O Pads MG7xPB02 68 MG7xPB04 108 MG7xPB06 148 MG7xPB08 188 MG7xPB10 228 MG7xPB12 268 [1] 256 352 420 MG7xPB14 308 ● MG7xPB16 348 ● MG7xPB18 388 ● ● MG7xPB20 428 ● ● 560 MG7xPB22 468 ● ● ● MG7xPB24 508 ● ● ● MG7xPB26 548 ● ● ● MG7xPB28 588 ● ● ● MG7xPB30 628 ● ● ● MG7xPB32 668 ● ● MG7xPB34 708 ● ● MG7xPB36 748 ● ● MG7xPB38 788 ● ● MG7xPB40 828 ● MG7xPB42 868 ● ● ● Body Size (mm) 27x27 35x35 35x35 35x35 Lead Pitch (mm) 1.27 1.27 1.27 1.00 Ball Count 256 352 420 560 Signal I/O 231 304 352 400 Power Ball 12 16 32 80 GND Ball 13 32 36 80 1. I/O Pads can be used for input, output, bi-directional, power, or ground. ● = Available now 18 Oki Semiconductor The information contained herein can change without notice owing to product and/or technical improvements. Please make sure before using the product that the information you are referring to is up-to-date. The outline of action and examples of application circuits described herein have been chosen as an explanation of the standard action and performance of the product. When you actually plan to use the product, please ensure that the outside conditions are reflected in the actual circuit and assembly designs. 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