OKI Semiconductor ML7021 FEDL7021-03 Issue Date: Jun. 1, 2005 Echo Canceler GENERAL DESCRIPTION The ML7021 is an improved version of the MSM7602 with the reduced cancelable echo delay time and additional 2100Hz tone detection function. The ML7021 is a low-power CMOS device for canceling echo (in an acoustic system or telephone line) generated in a speech path. Echo is canceled, in digital signal processing, by estimating the echo path and generating a pseudo echo signal. The ML7021 makes possible a quality conversation by controlling the noise level and preventing howling with howling detector, double talk detector, attenuation function, and a gain control function. The devise also controls the low level noise with a center clipping function. Further, the ML7021 I/O interface supports m-law PCM . The use of a single chip CODEC, such as the MSM7566/7704 (3 V) or MSM7543/7533 (5 V), allows a simplified and efficient echo canceler configuration. FEATURES • Tone disable function • Cancelable echo delay time: For a single chip: 8 ms (max.) • Echo attenuation : 30 dB (typ.) • Clock frequency : 19.2 MHz External input and internal oscillator circuit are provided. • Power supply voltage : 2.7 V to 5.5 V • Package: 28-pin plastic SSOP (SSOP28-P-485-0.65-K) (Product name : ML7021MB) 1 ¡ Semiconductor ML7021 BLOCK DIAGRAM RIN S/P Non–linear/ Linear ATT Howling Detector Double Talk Detector Power Calculator Linear/ Non–linear Gain Adaptive FIR Filter (AFF) P/S ROUT 2100Hz Tone Detector – SOUT P/S Linear/ Non–linear Center Clip ATT + + Non–linear/ Linear S/P RST WDT PWDWN SIN VDD Clock Generator Mode Selector I/O Controller VSS MCKO X1/CLKIN X2 SCKO SYNCO NLP HCL ADP ATT GC HD INT IRLD SCK SYNC 2 ¡ Semiconductor ML7021 PIN CONFIGURATION (TOP VIEW) 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 28-Pin Plastic SSOP Symbol Pin Symbol Pin Symbol 8 SIN 15 VSS 22 SYNCO 9 RIN 16 HD 23 SCKO ADP 10 SCK 17 X1/CLKIN 24 RST 4 VDD 11 SYNC 18 X2 25 WDT 5 ATT 12 SOUT 19 VDD 26 GC 6 INT 13 ROUT 20 PWDWN 27 VDD 7 IRLD 14 VSS 21 VSS 28 MCKO Pin Symbol Pin 1 NLP 2 HCL 3 3 ¡ Semiconductor ML7021 PIN DESCRIPTIONS (1/4) Pin Symbol Type Description 1 NLP I 2 HCL I Control pin for the center clipping function. This pin forces the SOUT output to a minimum value when the SOUT signal is below –54 dBm0. Effective for reducing low-level noise. • Single Chip or Master Chip in a Cascade Connection "H": Center clip ON "L": Center clip OFF • Slave Chip in a Cascade Connection Fixed at "L" This input signal is loaded in synchronization with the falling edge of the INT signal or the rising edge of the RST signal. Through mode control. When this pin is in the through mode, RIN and SIN data is output to ROUT and SOUT. At the same time, the coefficient of the adaptive FIR filter is cleared. • Single Chip or Master Chip in a Cascade Connection "H": Through mode "L": Normal mode (echo canceler operates) • Slave Chip in a Cascade Connection Same as the master chip This input signal is loaded in synchronization with the falling edge of the INT signal or the rising edge of the RST signal. 3 ADP I AFF coefficient control. This pin stops updating of the adaptive FIR filter (AFF) coefficient and sets the coefficient to a fixed value, when this pin is configured to be the coefficient fix mode. This pin is used when holding the AFF coefficient which has been once converged. • Single Chip or Master Chip in a Cascade Connection "H": Coefficient fix mode "L": Normal mode (coefficient update) • Slave Chip in a Cascade Connection Fixed at "L" This input signal is loaded in synchronization with the falling edge of the INT signal or the rising edge of the RST signal. 4 ¡ Semiconductor ML7021 (2/4) Pin Symbol Type Description 5 ATT I Control for the ATT function. This pin prevents howling by attenuators (ATT) for the RIN input and SOUT output. If there is input only to RIN, the ATT for the SOUT output is activated. If there is no input to SIN, or if there is input to both SIN and RIN, the ATT for the RIN input is activated. Either the ATT for the RIN output or the ATT for the SOUT is always activated in all cases, and the attenuation of ATT is 6 dB. • Single Chip or Master Chip in a Cascade Connection "H": ATT OFF "L": ATT ON "L" is recommended if performing echo cancellation. • Slave Chip in a Cascade Connection Fixed at "L" This input signal is loaded in synchronization with the falling edge of the INT signal or the rising edge of the RST signal. 6 INT I Interrupt signal which starts 1 cycle (8 kHz) of the signal processing. Signal processing starts when "H"-to-"L" transition is detected. • Single Chip or Master Chip in a Cascade Connection Connect the IRLD pin. • Slave Chip in a Cascade Connection Connect the IRLD pin of the master chip. INT input is invalid for 100 ms after reset due to initialization. Refer to the control pin connection example. 7 IRLD O Load detection signal output when the SIN and RIN serial input data is loaded in the internal registers. • Single Chip Connect to the INT pin. • Master Chip in a Cascade Connection Connect to the INT pin of the master chip and all the slave chips. • Slave Chip in a Cascade Connection Leave open. Refer to the control pin connection example. 8 SIN I Transmit serial data. Input the PCM signal synchronized to SYNC and SCK. Data is read in at the falling edge of SCK. 9 RIN I Receive serial data. Input the PCM signal synchronized to SYNC and SCK. Data is read in at the falling edge of SCK. 10 SCK I Clock input for transmit/receive serial data. This pin uses the external SCK or the SCKO. Input the PCM CODEC transmit/receive clock (64 to 2048 kHz). 5 ¡ Semiconductor ML7021 (3/4) Pin Symbol Type Description 11 SYNC I Sync signal for transmit/receive serial data. This pin uses the external SYNC or SYNCO. Input the PCM CODEC transmit/receive sync signal (8 kHz). 12 SOUT O Transmit serial data. Outputs the PCM signal synchronized to SYNC and SCK. This pin is in a high impedance state during no data output. 13 ROUT O Receive serial data. Outputs the PCM signal synchronized to SYNC and SCK. This pin is in a high impedance state during no data output. 16 HD I 17 X1/CLKIN I Controls the howling detect function. This pin detets and cancels a howling generated during hand-free talking for acoustic system. This function is used to cancel acoustic echoes. • Single Chip or Master Chip in a Cascade Connection "L": Howling detector ON "H": Howling detector OFF • Slave Chip in a Cascade Connection Fixed at "L" External input for the basic clock (17.5 to 20 MHz) or for the crystal oscillator. When the internal sync signal (SYNCO, SCKO) is used, input the basic clock of 19.2 MHz. 18 X2 O Crystal oscillator output. Used to configure the oscilation circuit. Refer to the internal clock generator circuit example. When inputting the basic clock externally, insert a 5 pF capacitor with excellent high frequency characteristics between X2 and GND. 20 PWDWN I Power-down mode control when powered down. "L": Power-down mode "H": Normal operation mode During power-down mode, all input pins are disabled and output pins are in the following states : High impedance : SOUT, ROUT "L": SYNCO, SCKO, MCKO "H": OF1, OF2, X2 Holds the last state : WDT, IRLD Reset after the power-down mode is released. 6 ¡ Semiconductor ML7021 (4/4) Pin Symbol Type Description 22 SYNCO O 8 kHz sync signal for the PCM CODEC. Connect to the SYNC pin and the PCM CODEC transmit/receive sync pin. Leave it open if using an external SYNC. 23 SCKO O 24 RST I Transmit clock signal (256 kHz) for the PCM CODEC. Connect to the SCK pin and the PCM CODEC transmit/receive clock pin. Leave it open if using an external SCK. Reset signal. "L": Reset mode "H": Normal operation mode Due to initialization, input signals are disabled for 100 ms after reset (after RST is returned from L to H). Input the basic clock during the reset. Output pins during the reset are in the following states : High impedance: SOUT, ROUT "L": WDT "H": OF1, OF2 Not affected: X2, SYNCO, SCKO, IRLD, MCKO After the power is turned on, initialize the LSI's internal registers by your execution of HÆL sequence 1ms later than the master clock starts normal oscilation. This LSI starts a normal operation by releasing this pin to H after the HÆL sequence above. Here, this pin must stay L for 1ms or longer. 25 WDT O 26 GC I 28 MCKO O Test program end signal. This signal is output when one cycle (8kHz) of processing is completed. Leave it open. Input signal by which the gain controller for the RIN input is controlled and the RIN input level is controlled and howling is prevented. The gain controller adjusts the RIN input level when it is –10 dBm0 or above. RIN input levels from –10 to –1.5 dBm0 will be suppressed to –10 dBm0 in the attenuation range from 0 to 8.5 dB. RIN input levels above –1.5 dBm0 will always be attenuated by 8.5 dB. • Single Chip or Master Chip in a Cascade Connection "H": Gain control ON "L": Gain control OFF "H" is recommended for echo cancellation. • Slave Chip in a Cascade Connection Fixed at "L" This pin is loaded in synchronization with the falling edge of the INT signal or the rising edge of RST. Basic clock (19.2 MHz). 7 ¡ Semiconductor ML7021 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Power Supply Voltage VDD Input Voltage VIN Power Dissipation Storage Temperature Condition Rating Unit –0.3 to +7 V Ta = 25˚C –0.3 to VDD + 0.3 V 1 W — –55 to +150 ˚C PD TSTG RECOMMENDED OPERATING CONDITIONS (VDD = 2.7 V to 3.6 V) Symbol Condition Min. Typ. Max. Unit Power Supply Voltage VDD — 2.7 3.3 3.6 V Power Supply Voltage VSS Parameter — 0 — V Pins other than X1 — 2.0 — VDD V X1 pin High Level Input Voltage VIH 2.2 — VDD V Low Level Input Voltage VIL — 0 — 0.5 V Operating Temperature Ta — –40 +25 +85 ˚C Symbol Condition Min. Typ. Max. Unit Power Supply Voltage VDD — 4.5 5 5.5 V Power Supply Voltage VSS — — 0 — V High Level Input Voltage VIH Pins other than X1, SCK 2.4 — VDD V X1, SCK pins 3.5 — VDD V Low Level Input Voltage VIL — 0 — 0.8 V Operating Temperature Ta — –40 +25 +85 ˚C (VDD = 4.5 V to 5.5 V) Parameter ELECTRICAL CHARACTERISTICS DC Characteristics (VDD = 2.7 V to 3.6 V, Ta = –40˚C to +85˚C) Parameter Symbol Condition Min. Typ. Max. Unit High Level Output Voltage VOH IOH = 40 mA 2.2 — VDD V Low Level Output Voltage VOL IOL = 1.6 mA 0 — 0.4 V High Level Input Current IIH VIH = VDD — 0.1 1 mA Low Level Input Current IIL VIL = VSS –1 –0.1 — mA High Level Output Leakage Current Low Level Output Leakage Current IOZH IOZL VOH = VDD VOL = VSS — 0.1 1 mA –1 –0.1 — mA Power Supply Current (Operating) IDDO — 20 30 mA Power Supply Current (Stand-by) IDDS Input Capacitance Output Load Capacitance — PWDWN = "L" — 10 50 mA CI — — — 15 pF CLOAD — — — 20 pF 8 ¡ Semiconductor ML7021 Parameter Symbol High Level Output Voltage VOH Low Level Output Voltage High Level Input Current Condition IOH = 40 mA (VDD = 4.5 V to 5.5 V, Ta = –40˚C to +85˚C) Typ. Min. Max. Unit 4.2 — VDD V VOL IIH IOL = 1.6 mA 0 — 0.4 V VIH = VDD — 0.1 10 mA IIL VIL = VSS –10 –0.1 — mA IOZH VOH = VDD — 0.1 10 mA Low Level Output Leakage Current IOZL VOL = VSS –10 –0.1 — mA Power Supply Current (Operating) IDDO — 30 45 mA Power Supply Current (Stand-by) IDDS Low Level Input Current High Level Output Leakage Current PWDWN = "L" — 10 50 mA CI — — — 15 pF CLOAD — — — 20 pF Min. Typ. Max. Unit — 30 — dB — — 8 ms Min. Typ. Max. Unit Input Capacitance Output Load Capacitance — Echo Canceler Characteristics (Refer to Characteristic Diagram) Parameter Symbol Condition RIN = –10 dBm0 (5 kHz band white noise) Echo Attenuation LRES E. R. L. (echo return loss) = 6 dB TD = 8 ms ATT, GC, NLP: OFF RIN = –10 dBm0 Cancelable Echo Delay Time TD (5 kHz band white noise) E. R. L. = 6 dB ATT, GC, NLP: OFF Tone Disable Characteristics Parameter Detection Frequency 2075 2100 2125 Hz Tone Detection Detection Level –32 — — dBm0 Detection Time 380 — — ms Release Detection Level — — –32 dBm0 9 1Semiconductor ML7021 AC Characteristics (Ta = –40˚C to +85˚C) Parameter Symbol VDD = 2.7 V to 3.6 V VDD = 4.5 V to 5.5 V Unit Min. Typ. Max. Min. Typ. Max. — 19.2 — — 19.2 — 17.5 — 20 17.5 — 20 — 52.08 — — 52.08 — 50 — 57.14 50 — 57.14 tDMC 40 — 60 40 — 60 ns tMCH 20.8 — 31.3 20.8 — 31.3 ns tMCL 20.8 — 31.3 20.8 — 31.3 ns Clock Rise Time tr — — 5 — — 5 ns Clock Fall Time tf — — 5 — — 5 ns tDCM — — 30 — — 30 ns Internal Sync Clock Frequency fCO — 256 — — 256 — kHz Internal Sync Clock Output Cycle Time tCO — 3.9 — — 3.9 — ms Internal Sync Clock Duty Ratio tDCO — 50 — — 50 — % Internal Sync Signal Output Delay Time tDCC — — 5 — — 5 ns Internal Sync Signal Period tCYO — 125 — — 125 — ms Internal Sync Signal Output Width tWSO — tCO — — tCO — ms Transmit/receive Operation Clock Frequency fSCK 64 — 2048 64 — 2048 kHz Transmit/receive Sync Clock Cycle Time tSCK 0.488 — 15.6 0.488 — 15.6 ms Transmit/receive Sync Clock Duty Ratio tDSC 40 50 60 40 50 60 % Transmit/receive Sync Signal Period tCYC 123 125 — 123 125 — ms tXS 45 — — 45 — — ns Clock Frequency When Internal Sync Signal is not used Clock Cycle Time When Internal Sync Signal is not used Clock Duty Ratio Clock High Level Pulse Width fc = 19.2 MHz Clock Low Level Pulse Width fc = 19.2 MHz Sync Clock Output Time Sync Timing fC tMCK MHz ns tSX 45 — — ns tSCK — tCYC-tSCK 45 tWSY tSCK — tCYC-tSCK ms Receive Signal Setup Time tDS 45 — — 45 — — ns Receive Signal Hold Time tDH 45 — — 45 — — ns Receive Data Input Time tID — 7tSCK — — 7tSCK — ms IRLD Signal Output Delay Time tDIC — — 138 — — 138 ns IRLD Signal Output Width tWIR — tSCK — — tSCK — ms Sync Signal Width tSD — — 90 — — 90 ns tXD — — 90 — — 90 ns Reset Signal Input Width tWR 1 — — 1 — — ms Reset Start Time tDRS 5 — — 5 — — ns Reset End Time tDRE — — 52 — — 52 ns Processing Operation Start Time tDIT 100 — — 100 — — ms Serial Output Delay Time 10 ¡ Semiconductor ML7021 AC Characteristics (Continued) (Ta = –40˚C to +85˚C) Parameter Symbol VDD = 2.7 V to 3.6 V VDD = 4.5 V to 5.5 V Min. Typ. Max. Min. Typ. Max. Unit Power Down Start Time tDPS — — 111 — — 111 ns Power Down End Time tDPE — — 15 — — 15 ns Control Pin Setup Time (INT) tDTS 20 — — 20 — — ns Control Pin Hold Time (INT) tDTH 120 — — 120 — — ns Control Pin Setup Time (RST) tDSR 20 — — 20 — — ns Control Pin Hold Time (RST) tDHR 10 — — 10 — — ns 11 ¡ Semiconductor ML7021 TIMING DIAGRAM Clock Timing fC, tMCK, tDMC tMCH tr tMCL tf X1/CLKIN tDCM tDCM SCKO tDCO fCO, tCO SCKO tDCC tDCC tCYO SYNCO tWSO Serial Input Timing fSCK, tSCK tDSC SCK tSX tXS tCYC SYNC tWSY tDH tDS SIN RIN MSB 7 6 5 4 3 2 LSB 0 1 MSB 7 tID tDIC tDIC IRLD tWIR 12 ¡ Semiconductor ML7021 Serial Output Timing fSCK, tSCK tDSC SCK tSX tXS tCYC SYNC tWSY tXD tSD tXD SOUT ROUT High-Z MSB 7 tXD 6 5 4 3 2 1 LSB High-Z 0 MSB 7 Operation Timing After Reset tWR *Reset timing can be asynchronous RST tDIT tDRS Internal operaion tDRE Reset Initialization Processing Start Note: INT is invalid in the diagonally shaded interval. Power Down Timing PWDWN tDPS Internal Operation tDPE Power Down Processing Start 13 ¡ Semiconductor ML7021 Control Pin Load-in Timing *tCYC INT(IRLD) tDTH tDTS *For IRLD output timing, refer to Serial Input Timing NLP, HCL, HD, ATT, ADP, GC tWR RST tDSR tDHR NLP, HCL, HD, ATT, ADP, GC 14 ¡ Semiconductor ML7021 HOW TO USE THE ML7021 The ML7021 cancels (based on the RIN signal) the echo which returns to SIN. Connect the base signal to the R side and the echo generated signal to the S side. Connection Methods According to Echos Example 1: Canceling acoustic echo (to handle acoustic echo from line input) ML7021 ROUT Acoustic echo AFF CODEC SIN Example 2: RIN – + + H CODEC Line input SOUT Canceling line echo (to handle line echo from microphone input) ML7021 Microphone input RIN ROUT AFF CODEC SOUT – + H CODEC + SIN Line echo 15 ¡ Semiconductor ML7021 Internal Clock Generator Circuit Example ML7021 X1/CLKIN X2 XTAL : 19.2 MHz R : 1 MW C1 : 27 pF C2 : 27 pF R XTAL C1 C2 GND GND External Clock Input Circuit Example ML7021 X1/CLKIN CLK X2 5pF GND 16 ¡ Semiconductor ML7021 ECHO CANCELER CHARACTERISTIC DIAGRAM RIN input level vs. echo attenuation 40 40 30 30 Echo attenuation [dB] Echo attenuation [dB] ERL vs. echo attenuation 20 10 0 20 10 0 40 30 20 10 0 –10 –50 –40 –30 –20 –10 ERL [dB] Measurement Conditions RIN input = –10 dBm 5 kHz band white noise (0 dBm = 2.2 dBm0) Echo delay time TD = 8 ms ATT, GC, NLP = OFF Power supply voltage 5 V 0 RIN input level [dBm] 0 dBm = 2.2 dBm0 Measurement Conditions RIN input: 5 kHz band white noise Echo delay time TD = 8 ms ERL = 6 dB ATT, GC, NLP = OFF Power supply voltage 5 V Echo delay time vs. echo attenuation Echo attenuation [dB] 40 Measurement Conditions RIN input = –10 dBm 5 kHz band white noise (0 dBm = 2.2 dBm0) 30 20 ERL = 6 dB ATT, GC, NLP = OFF Power supply voltage 5 V 10 0 0 Note: 2 4 6 Echo delay time [ms] 8 10 The characteristics above are for the MSM7543 (VDD 5 V, m-law interface). The MSM7566 (VDD 3 V, m-law interface) provides the same characleristics without input and output levels. Refer to the PCM CODEC data sheet. MSM7543 (for both transmit and receive) 0 dBm0 = 0.6007 Vrms = –2.2 dBm (600 W) MSM7566 (for transmit side) 0 dBm0 = 0.35 Vrms = –6.9 dBm (600 W) (for receive side) 0 dBm0 = 0.5 Vrms = –3.8 dBm (600 W) 17 ¡ Semiconductor ML7021 Measurement System Block Diagram White noise generator MSM7543 L. P. F. RIN 5 kHz A PCM m-law CODEC Level meter A PCM MSM7543 RIN ROUT ML7021 SOUT SIN SOUT Power supply voltage 5 V PCM A m-law CODEC PCM A TD Delay Echo delay time ATT ERL (echo return loss) 18 ¡ Semiconductor ML7021 APPLICATION CIRCUIT Bidirectional Connection Example Use the MSM7704-01GS-VK for PCM CODEC when VDD = 3V. The MSM7533 and MSM7704 are pin compatible. Microphone input C1 2ch CODEC MSM7533VGS-K R1 R2 R3 DV Speaker output 13 12 15 10 16 19 5 6 DV For cancellation of acoustic echo ML7021MB R4 11 10 22 23 6 7 20 24 28 PWDWN RST DV 1 2 3 5 26 16 25 17 R9 18 X2 VSS 14 VSS 15 VSS 21 SYNC NLP HCL ADP ATT GC HD WDT X1 SCK SYNCO SCKO INT IRLD PWDWN RST MCKO 4 VDD 19 V DD 27 V DD + R1 = 20 kW R2 = 20 kW R3 = 2.2 kW R4 = 10 kW R10 = 10 kW DV DV C1 = 1 mF C2 = 10 mF C3 = 0.1 mF C4 = 0.1 mF Line output DV R10 R11 AV + 18 C9 C10 C11 (AG) 9 For cancellation of line echo ML7021MB 12 SOUT 9 RIN 8 SIN 13 ROUT Line input R7 8 VDD 1 SGC AG DV C12 C13 X1 1 2 3 5 26 16 25 17 C14 18 14 15 21 SYNC SCK SYNCO SCKO INT IRLD PWDWN RST NLP HCL ADP ATT GC HD WDT X1 X2 VSS VSS VSS R8 11 10 22 23 6 7 20 24 28 4 VDD VDD 19 VDD 27 C2 C6 C3 C7 R5 = 20 kW R6 = 20 kW R7 = 2.2 kW R8 = 10 kW R11 = 10 kW DV 8 SIN 13 ROUT 12 SOUT 9 RIN DV C5 R6 14 DOUT2 11 DIN2 DOUT1 DIN1 XSYNC RSYNC BCLK A/m PDN CHP DG DV R5 24 AIN2 23 GSX2 2 AOUT2 21 AIN1 22 GSX1 4 AOUT1 C5 = 1 mF C6 = 10 mF C7 = 0.1 mF C8 = 0.1 mF DV + C9 = 0.1 mF C10 = 10 mF C11 = 0.1 mF R9 = 1 MW C12 = 27 pF C13 = 27 pF X1 = 19.2 MHz C14 = 5 pF 19 ¡ Semiconductor ML7021 NOTES ON USE 1. Set echo return loss (ERL) to be attenuated. If the echo return loss is set to be amplified, the echo can not be eliminated. Refer to the characteristic diagram for ERL vs. echo attenuation quantity. 2. Set the level of the analog input so that the PCM CODEC does not overflow. 3. The recommended input level is –10 to –20 dBm0. Refer to the characteristic diagram for the RIN input level vs. echo attenuation quantity. 4. Applying the tone signal to this echo canceler for long duration may decrease echo attenuation. When used with the HD pin "L" (howling detector ON), this echo canceler may operate faultily if, while a signal is input to the RIN pin, a tone signal with a higher level than the signal being input to RIN is input to the SIN pin. A signal should therefore be input either to the RIN pin or to the SIN pin. If, however, the tone signal is input to the SIN pin while a signal is input to the RIN pin, the ADP, HD, or HCL pin must be set to "H". 5. For changes in the echo path (retransmit, circuit switching during transmission, and so on), convergence may be difficult. Perform a reset, to make it converge. If the state of the echo path changes after a reset, convergence may again be difficult. In cases such as a change in the echo path, perform a reset each time. 6. When turning the power ON, set the PWDWN pin to "1" and input the basic clock simultaneously with power ON. If powering down immediately after power ON, be sure fast input 10 or more clocks of the basic clock. 7. After powering ON, be sure to reset. 8. After the power down mode is released (when the PWDWN pin is changed from "L" to "H"), be sure to reset the device. 9. If this canceler is used to cancel acoustic echoes, an echo attenuation may be less than 30 dB. 20 ¡ Semiconductor ML7021 EXPLANATION OF TERMS Attenuating Function : This function prevents howling and controls the noise level with the attenuator for the RIN input and SOUT output. Refer to the explanation of pins (ATT pin). Echo Attenuation : If there is talking (input only to RIN) in the path of a rising echo arises, the echo attenuation refers to the difference in the echo return loss (canceled amount) when the echo canceler is not used and when it is used. Echo attenuation = (SOUT level during through mode operation) – (SOUT level during echo canceler operation) [dB] Echo Delay Time : This is the time from when the signal is output from ROUT until it returns to SIN as an echo. Acoustic Echo : When using a hands free phone, and so on, the signal output from the speaker echoes and is input again to the microphone. The return signal is referred to as acoustic echo. Telephone Line Echo : This is a signal which is delayed midway in a telephone line and returns as an echo, due to reasons such as a hybrid impedance mismatch. Gain Control Function : This function prevents howling and controls the sound level with a gain controller for the RIN input. Refer to the explanation of pins (GC pin). Center Clipping Function : This function forces the SOUT output to a minimum value when the signal is below –54 dBm0. Refer to the explanation of pins (NLP pin). Double Talk Detection : Double talk refers to a state in which the SIN and RIN signals are input simultaneously. In a double talk state, a signal outside the echo signal which is to be canceled can be input to the SIN input, resulting in misoperation. The double talk detector prevents such misoperation of the canceler. Howling Detection : This is the oscillating state caused by the acoustic coupling between the loud speaker and the microphone during hands free talking. Howling not only interferes with talking, but can also cause in misoperation of the echo canceler. The howling detector prevents such misoperation and prevents howling. Echo Return Loss (ERL) : When the signal output from ROUT returns to SIN as an echo, ERL refers to how much loss there is in the signal level during ROUT. ERL = (ROUT level) – (SIN level of the ROUT signal which returns as an echo) [dB] If ERL is positive (ROUT > SIN), the system is an attenuator system. If ERL is negative (ROUT < SIN), the system is an amplifier system. 21 1Semiconductor ML7021 PACKAGE DIMENSIONS (Unit : mm) SSOP28-P-485-0.65-K Mirror finish Oki Electric Industry Co., Ltd. Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (≥5 mm) 0.39 TYP. 3/Dec. 5, 1996 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 22 1Semiconductor ML7021 REVISION HISTORY Document No. Date Page Previous Current Edition Edition Description FEDL7021-02 Nov. 2001 – – Final edition 2 FEDL7021-03 Jun. 1, 2005 10 10 Revised Max. values of “Sync Timing” and “Sync Signal Width” in the Table in the “AC Characteristics” Section. 23 1Semiconductor ML7021 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2005 Oki Electric Industry Co., Ltd. 24