E2B0051-19-22 ¡ Semiconductor ML9060 ¡ Semiconductor Pr el im in This version: Feb. 1999 ML9060 ar y 1/2 DUTY, 160-OUTPUT STATIC LCD DRIVER GENERAL DESCRIPTION The ML9060 consists of a 320-bit shift register, a 320-bit data latch, 160 sets of LCD drivers, and a common signal generator circuit. The LCD display data is input serially to the shift register from the DATA IN pin in synchronization with the CLOCK IN signal, and is stored in the data latch by the LOAD IN signal. The LCD display data stored in the data latch is output via the LCD drivers. A maximum of 160 segments of LCD can be driven in static display mode and a maximum of 320 segments can be driven directly in the 1/2 duty display mode. It is possible to select the mode of using the internal oscillator circuit or the mode of using an external clock for the common signal generator circuit. The ML9060 also outputs the sync signal during the 1/2 duty display mode. FEATURES • Logic power supply : 2.7 to 5.5V • LCD Driving voltage : 4.5 to 16V • Maximum number of segments that can be driven: Static display mode : 160 segments 1/2 Duty display mode : 320 segments • Serial transfer clock : 1 MHz max. • The microcontroller interface consists of the three signals DATA IN, CLOCK IN, and LOAD IN. • An RC oscillator circuit is built in which can use either an external resistor or the internal resistor. • Cascade connection of several ICs is possible. • Built-in common signal generator circuit. • Built-in common output mid-level voltage generator circuit. • Input for turning all segments ON is available (SEG-TEST IN). • Input for turning all segments OFF is available (BLANK IN). • Gold bump chip Product name: ML9060DVWA 1/17 ¡ Semiconductor ML9060 BLOCK DIAGRAM SEG1 SEG2 SEG160 COM A COM B VLCD 1/2VLCD Generator & Common Drivers Segment Drivers SEG-TEST IN BLANK IN SEG-TEST OUT BLANK OUT VDD DS01 DS02 DS0160 Data Selector DSI1a DSI160a L01a L0160a DSI1b DSI160b L01b L0160b Data Latch A Data Latch B LI1a LI1b LI160a LI160b LOAD IN DATA IN LOAD OUT P01a SIa P0160a SOa Shift Register A P01b SIb P0160b SOb Shift Register B CLOCK IN DATA OUT CLOCK OUT Timing Generator COM OUT OSC I/E D/S OSC1 OSCR OSC2 OSC 1/64 or 1/128 1/2 M/S SYNC SYNC GND 2/17 ¡ Semiconductor ML9060 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit Logic power supply voltage V DD Ta = 25°C –0.3 to +6.5 V LCD Driving voltage V LCD Ta = 25°C 0 to 18 V VI Ta = 25°C GND–0.3 to V DD +0.3 V T STG — –55 to +150 °C Input voltage Storage temperature RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Range Unit Logic power supply voltage V DD * — 2.7 to 5.5 V LCD Driving voltage V LCD * — 4.5 to 16 V T op — –40 to +85 °C Operating temperature *: Use with VDD ≤ VLCD Note: Never place a short between an output pin and another output pin or between an output pin and other pins (input pins, I/O pins, or power supply pins). 3/17 ¡ Semiconductor ML9060 ELECTRICAL CHARACTERISTICS DC Characteristics (VDD = 2.7 to 5.5V, VLCD = 4.5 to 16V, Ta = –40 to +85°C) Parameter Symbol Condition VIH1 *1 "H" Input voltage VIH2 *2 VIL1 *1 "L" Input voltage VIL2 *2 Input leakage current 1 IL1 — — VI = VDD or 0V Min. Typ. Max. 0.7VDD — VDD Unit Applicable pin 0.8VDD — VDD GND — 0.3VDD GND — 0.2VDD — — ±1.0 mA — — ±10 mA SYNC DATA IN V CLOCK IN LOAD IN V SEG-TEST IN BLANK IN M/S, D/S OSC1, OSC I/E VI = VDD or 0V Input leakage current 2 IL2 D/S = "H" M/S = "L" Segment VOHS IO = –30mA VLCD–0.2 — — V SEG1 to SEG160 Common VOHC *3 IO = –150mA VLCD–0.2 — — V COM A, COM B DATA OUT CLOCK OUT LOAD OUT "H" Output voltage Logic VOHL1 IO = –100mA 0.9VDD — — V SEG-TEST OUT BLANK OUT COM OUT SYNC IO = –200mA 0.9VDD VOMC *3 IO = ±150mA 1/2VLCD VOHL2 "M" Output voltage Common –0.15 — 1/2VLCD — 1/2VLCD +0.15 V OSC2 V COM A, COM B SEG1 to SEG160 Segment VOLS IO = 30mA — — 0.2 V Common VOLC *3 IO = 150mA — — 0.2 V COM A, COM B DATA OUT CLOCK OUT LOAD OUT "L" Output voltage Logic VOLL1 IO = 100mA — — 0.1VDD V SEG-TEST OUT BLANK OUT COM OUT SYNC VOLL2 IO = 200mA — — 0.1VDD V OSC2 Output Segment RSEG — — 10 kW SEG1 to SEG160 resistance Common RCOM — — 1.5 kW COM A, COM B "M": Middle level 4/17 ¡ Semiconductor Parameter ML9060 Symbol Applicable Min. Typ. Max. Unit IDDS1 D/S = "L" (Static) Fix other input levels at either "H" or "L" Oscillator stopped No load — — TBD mA VDD IDDS2 D/S = "H" (1/2duty) Fix other input levels at either "H" or "L" Oscillator stopped No load — — TBD mA VDD ILCDS1 D/S = "L" (Static) Fix other input levels at either "H" or "L" Oscillator stopped No load — — TBD mA VLCD ILCDS2 D/S = "H" (1/2duty) Fix other input levels at either "H" or "L" Oscillator stopped No load — — TBD mA VLCD IDD1 VDD = 5.5V D/S = "L" (Static) OSC1 is Open OSC2 is connected to OSCR Other inputs are "H" or "L" No load — — TBD mA VDD IDD2 VDD = 5.5V D/S = "H" (1/2duty) OSC1 is Open OSC2 is connected to OSCR Other inputs are "H" or "L" No load — — TBD mA VDD ILCD1 VDD = 5.5V D/S = "L" (Static) OSC1 is Open OSC2 is connected to OSCR Other inputs are "H" or "L" No load — — TBD mA VLCD ILCD2 VDD = 5.5V D/S = "H" (1/2duty) OSC1 is Open OSC2 is connected to OSCR Other inputs are "H" or "L" No load — — TBD mA VLCD Static supply current *4 Dynamic supply current *4 Condition pin *1: Applicable to the DATA IN, LOAD IN, SEG-TEST IN, M/S, D/S, and OSC I/E pins. *2: Applicable to the CLOCK IN, OSC1, and BLANK IN pins. *3: Applicable to the voltage drop when the current flows into or out of one COM pin. *4: The power supply current consumption will be determined finally at the end of sample evaluations. The LCD display data of “0” and “1” are input alternately. 5/17 ¡ Semiconductor ML9060 Switching Characteristics (VDD = 2.7 to 5.5V, VLCD = 4.5 to 16V, Ta = –40 to +85°C) Parameter OSC IN Clock frequency (external input) Clock pulse width (external input) Symbol fCP1 tWCP1 fOSC1 (internal oscillations) Internal Rf clock frequency (with the built-in oscillator) Data clock frequency OSC1 pin. The pins OSC2 and OSCR are left open. OSC I/E = "L" Min. Typ. Max. Unit — — 50 — Applicable pin 25.6 kHz OSC1 — µs OSC1 An Rf of 120k W ±2% is External Rf clock frequency Condition The clock is input to the connected between OSC1 and OSC2. OSCR is left 7.7 12.8 20.5 kHz OSC1, OSC2 7.7 12.8 20.5 kHz open. OSC I/E = 'H" OSC1 open. OSC2 and fOSC2 OSCR shorted. OSC I/E tied to VDD or any "H" level. OSC1, OSCR, OSC2 fCP2 — — 1 tWCP2 100 — — ns CLOCK IN tSU 50 — — ns DATA IN tHD 50 — — ns CLOCK IN tCL 100 — — ns CLOCK IN tLC 100 — — ns LOAD IN LOAD Pulse width tWLD 100 — — ns CLOCK IN to tPLH DATA OUT delay time tPHL Data clock pulse width Data setup time Data hold time CLOCK to LOAD Period LOAD to CLOCK Period CL=15pF — — 50 MHz CLOCK IN ns LOAD IN CLOCK IN DATA OUT CLOCK IN/OUT IN to OUT delay time tDIO No load — — 20 ns LOAD IN/OUT SEG-TEST IN/OUT BLANK IN/OUT COM OUT to SYNC delay time tDCS CL=15pF — — 40 ns COM OUT SYNC Input signal rise time tR — — 50 ns All inputs other than Input signal fall time tF — — 50 ns the OSCR input * : The specifications of the internal Rf clock frequency and the external Rf clock frequency will be determined finally at the end of sample evaluations. 6/17 ¡ Semiconductor ML9060 TIMING DIAGRAM 1/fCP1 tWCP1 VIH OSC1 (External clock) tWCP1 VIH VIL DATA IN VIL VIH VIH VIL VIL tSU tHD tWCP2 CLOCK IN VIH tWCP2 VIH VIL VIH VIL VIL VIL 1/fCP2 tCL tWLD tLC VIH VIH LOAD IN VIL VIL tPLH tPHL VOH DATA OUT VOL CLOCK IN LOAD IN SEG-TEST IN BLANK IN VIH VIL tDIO tDIO CLOCK OUT LOAD OUT SEG-TEST OUT BLANK OUT VOH VOL tR All input signals COM OUT SYNC tF VIH VIL VIH VIL 1/2VDD 1/2VDD tDCS tDCS 1/2VDD 1/2VDD 7/17 ¡ Semiconductor ML9060 FUNCTIONAL DESCRIPTION The ML9060 is an LCD driver LSI with an internal shift register and a set of internal data latches and is capable of driving LCD displays of up to 320 segments either in the static mode or in the 1/2 duty mode. The display data is read into the shift register serially from the DATA IN pin at the rising edge of the CLOCK IN input signal. The display data is transferred internally to the data latches at the High level of the LOAD IN input signal and is output to the segments via the segment drivers in this IC. The display data in the shift register is output via the DATA OUT pin in synchronization with the falling edge of the CLOCK IN input signal. The display data should be input in the sequence of SEG160, SEG159, ... , SEG2, SEG1 for proper display of data. Description of Pin Functions • M/S This is the input pin for selecting either the Master mode or the Slave mode. This LSI goes into the master mode when this pin is High and enters the Slave mode when this pin is Low. • D/S This input pin is for selecting either the dynamic display mode at 1/2 duty (D mode - “H” input) or the static display mode (S mode - “L” input). Note that the internal bias resistor is made ON in the dynamic (D) mode and is turned OFF in the static mode (S). • OSC I/E This is the input pin for selecting whether to use the external clock input mode, or the internal Rf oscillation mode or the external Rf oscillation mode. When this pin is tied to the “H” level, the internal Rf oscillation mode or the external Rf oscillation is used. When this pin is tied to the “L” level, the external clock input is used for the operation of the LSI. In the slave mode of operation of this LSI, any input to this pin will be ignored. Hence, tie this pin to VDD or GND in the slave mode. • OSC1, OSCR, OSC2 These are the pins for the oscillator for generating the common signal. In the Master mode (M/S pin = “H”): It is possible to select from among the three modes - internal Rf oscillation mode, external Rf oscillation mode, and the external clock input mode. During the static display operation mode, a common signal with 1/128th the frequency of the clock oscillator is output via the COM OUT pin. During the 1/2 duty dynamic display operation mode, a common signal with 1/64th the frequency of the clock oscillator is output via the COM OUT pin. • Internal Rf oscillation mode: Tie the OSC I/E pin to “H”, short the pins OSCR and OSC2, and leave the pin OSC1 open. • External Rf oscillation mode: Tie the OSC I/E pin to “L”, connect an external resistor Rf between the pins OSC1 and OSC2, and leave the pin OSCR open. • External clock input mode: Tie the OSC I/E pin to “L”, leave open the pins OSCR and OSC2, and input the external clock signal to the pin OSC1. 8/17 ¡ Semiconductor ML9060 In the Slave mode (M/S pin = “L”): Leave open the pins OSCR and OSC2 and connect the pin OSC1 to the COM OUT pin of the ML9060 which has been set in the master mode. The common signal that is input to the pin OSC1 will be used as the internal common signal and is also output via a buffer from the COM OUT pin. • COM OUT This is the common signal output pin. Connect this pin to the OSC1 pin of the ML9060 that is set in the slave mode. During operation in the master mode (M/S pin = “H”) for static display, a common signal with 1/128th the frequency of the oscillator is output. During operation in the master mode (M/S pin = “H”) for 1/2 duty dynamic display, a common signal with 1/64th the frequency of the oscillator is output. During operation in the slave mode (M/S pin = “L”), the common signal that is input at the pin OSC1 is output from this pin via a buffer. • SYNC This is the I/O pin for common signal synchronization. This pin becomes the synchronization signal output pin during operation in the master mode (M/S pin = “H”) for 1/2 duty dynamic display. This pin becomes the synchronization signal input pin during operation in the slave mode (M/ S pin = “H”) for 1/2 duty dynamic display. For cascade operation in the 1/2 duty display mode, connect the SYNC pins of all ML9060 ICs used together. During operation in the static display mode, this pin is tied to the “L” level inside the IC. Connect this pin either to GND or leave it open. • DATA IN This is the display data input pin. Input the display data in the sequence of SEG160, SEG159, ... , SEG2, SEG1. The segment is turned ON when the display data is “H” and OFF when “L”. • DATA OUT This is the display data output pin. During the static display mode of operation, the data of the 160th stage of the shift register is output from this pin. During the 1/2 duty dynamic display mode, the data of the 320th stage of the shift register is output from this pin. • CLOCK IN This is the input pin for the shift clock of the display data. The display data that is input at the DATA IN pin is input serially to the shift register at the rising edge of the CLOCK IN signal. Also, the display data in the shift register is output from the DATA OUT pin at the falling edge of the CLOCK IN signal. • CLOCK OUT This is the output pin for the shift clock of the display data. The shift clock signal that is input to the CLOCK IN pin is output via a buffer from this pin. • LOAD IN This is the input pin for the display data load signal. The display data in the shift register is output as such to the segment driver when this signal is at the “H” level. When this signal is made “L”, the shift register is isolated from the segment drivers, and the display data of the shift register just before this pin goes “L” is retained in the data latches and transfered to the segment drivers. 9/17 ¡ Semiconductor ML9060 • LOAD OUT This is the output pin for the display data load signal. The load signal that is input to the LOAD IN pin is output from this pin via a buffer. • SEG-TEST IN This is the input pin for making all segments ON. When this pin is “H”, all segment outputs (SEG1 to SEG160) become ON irrespective of the display data and the Blank signal. When this pin is made “L”, each of the segment outputs (SEG1 to SEG160) become ON or OFF according to the display data. • SEG-TEST OUT This is the output pin for making all segments ON. The segment ON signal that is input to at the SEG-TEST IN pin is output via a buffer. • BLANK IN This is the input pin for making all segments OFF. When this pin is “H”, all segment outputs (SEG1 to SEG160) become OFF irrespective of the display data. When this pin is made “L”, each of the segment outputs (SEG1 to SEG160) becomes ON or OFF according to the display data. The BLANK IN is valid when the segment ON signal is "L". • BLANK OUT This is the output pin for making all segments OFF. The segment OFF signal that is input to the BLANK IN pin is output via a buffer. • SEG1 to SEG160 These are the signal outputs for driving the LCD segments and are connected to the corresponding segment pins of the LCD panel. During the Static mode of operation: The SEGn output corresponds to bit n of the display data in the data latch A. The display data in the data latch B becomes invalid. In the segment ON condition, a signal with a phase opposite to that of the COM OUT signal is output from these pins. In the segment OFF condition, a signal with a phase identical to that of the COM OUT signal is output from these pins. During the 1/2 duty dynamic display mode of operation: The SEGn output corresponds to bit n of the display data in the data latch A when COM A has been selected and to bin n of the display data in the data latch B when COM B has been selected. In the segment display ON condition, a signal opposite in phase to that of the selected COM output is output from these pins. In the segment display OFF condition, a signal identical in phase to that of the selected COM output is output from these pins. • COM A, COM B These are the outputs for LCD display and are connected to the common pins of the LCD panel. During the Static mode of operation: COM A and COM B both output a signal with the same phase as that of the COM OUT signal. 10/17 ¡ Semiconductor ML9060 During the 1/2 duty dynamic display mode of operation: COM A and COM B change their states at every cycle of the COM OUT signal and repeat the selected and non-selected modes always opposing each other in phase. A signal with the same phase as that of the COM OUT signal is output in the selected mode. A voltage equal to 1/2VLCD is output in the non-selected mode. When COM A is in the selected mode (that is, COM B is in the non-selected mode), the segment outputs (SEG1 to SEG160) output signals corresponding to the display data in the data latch A. When COM B is in the selected mode (that is, COM A is in the non-selected mode), the segment outputs (SEG1 to SEG160) output signals corresponding to the display data in the data latch B. • VDD This is the power supply input pin for the logic circuits. • VLCD This is the power supply input pin for the LCD drivers. • GND This is the ground pin for all circuits. 11/17 ¡ Semiconductor ML9060 Segment Output and Common Output Waveforms During the 1/2 duty display operation mode: VDD COM OUT GND VDD SYNC GND COM A Selected COM B Selected COM A Selected COM B Selected VLCD 1/2VLCD COM A GND VLCD 1/2VLCD COM B GND VLCD SEGn OFF OFF OFF OFF OFF ON OFF ON ON OFF ON OFF ON ON ON ON Data latch A Data latch B Data latch A Data latch B GND VLCD GND VLCD GND VLCD GND During the static display operation mode: VDD COM OUT GND VLCD COM A GND VLCD COM B GND VLCD SEGn OFF OFF OFF OFF ON ON ON ON GND VLCD GND 12/17 ¡ Semiconductor ML9060 APPLICATION CIRCUIT EXAMPLES When a single ML9060 is used - Static display mode (internal Rf oscillation mode) LCD Panel 160 segments, COM static display SEG1 From the controller SEG160 SEG-TEST IN COM A BLANK IN COM B open SYNC GND or open ML9060 LOAD IN DATA IN CLOCK IN D/S M/S OSC1 OSC2 OSCR OSC I/E VDD open When a single ML9060 is used - 1/2 duty dynamic display mode (external Rf oscillation mode) LCD Panel 320 segments, COM A 1/2 Duty dynamic display COM B SEG1 From the controller SEG160 SEG-TEST IN COM A BLANK IN COM B ML9060 LOAD IN SYNC open DATA IN CLOCK IN D/S M/S OSC1 OSC2 OSCR OSC I/E VDD Rf open 13/17 ¡ Semiconductor ML9060 Cascade Connection - Static display mode (external clock input mode) LCD Panel (160 x n segments) COM Static 160 From the controller SEG-TEST IN BLANK IN LOAD IN DATA IN CLOCK IN D/S M/S ML9060 160 COM A COM B SEG-TEST OUT BLANK OUT LOAD OUT DATA OUT CLOCK OUT COM OUT SYNC open OSC1 OSC2 OSCR OSC I/E VDD SEG-TEST IN BLANK IN LOAD IN DATA IN CLOCK IN D/S M/S open open ML9060 COM A COM B SEG-TEST OUT BLANK OUT LOAD OUT DATA OUT CLOCK OUT COM OUT SYNC open open open OSC1 OSC2 OSCR OSC I/E open open VDD or GND External clock Note: Take care about the resistance and capacitance of wiring for cascade connection. Cascade Connection - 1/2 duty dynamic display mode (internal Rf oscillation mode) LCD Panel (320 x n segments) COM A COM B 1/2 duty dynamic display 160 From the controller VDD SEG-TEST IN BLANK IN LOAD IN DATA IN CLOCK IN D/S M/S ML9060 160 COM A COM A open COM B SEG-TEST OUT BLANK OUT LOAD OUT DATA OUT CLOCK OUT COM OUT SYNC COM B SEG-TEST OUT BLANK OUT LOAD OUT DATA OUT CLOCK OUT COM OUT SYNC open OSC1 OSC2 OSCR OSC I/E open SEG-TEST IN BLANK IN LOAD IN DATA IN CLOCK IN D/S M/S ML9060 open OSC1 OSC2 OSCR OSC I/E open open VDD or GND Note: Take care about the resistance and capacitance of wiring for cascade connection. 14/17 ¡ Semiconductor ML9060 PAD CONFIGURATION Pad layout (Pattern side) Chip size : Chip thickness : Minimum bump pitch : Bump size : Bump height : Bump height inside the chip : Bump hardness : 14.50 ¥ 1.48mm 625mm ± 30mm 80mm 50 ¥ 80µm 15mm ± 5µm max. – min. ≤ 4µm max. 100 (HV: 25 g LOAD) Y 204 37 205 36 X 214 27 1 26 * : The substrate of the chip should either be connected to the GND level or be left open. Pad Coordinates Pad No. Pad name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NC NC SYNC NC COMOUT NC VLCD VLCD VLCD NC GND GND GND D/S OSC I/E M/S VDD VDD VDD NC X-coordinate Y-coordinate (mm) –6680 –6146 –5611 –5077 –4542 –4008 –3474 –2939 –2405 –1870 –1336 –802 –267 267 802 1336 1870 2405 2939 3474 (mm) –561 –561 –561 –561 –561 –561 –561 –561 –561 –561 –561 –561 –561 –561 –561 –561 –561 –561 –561 –561 Pad No. Pad name 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 OSC2 OSCR OSC1 NC NC NC NC NC DATA IN NC CLOCK IN LOAD IN SEG-TEST IN BLANK IN NC NC NC NC NC COMA X-coordinate Y-coordinate (mm) 4008 4542 5077 5611 6146 6680 7121 7121 7121 7121 7121 7121 7121 7121 7121 7121 6680 6600 6520 6440 (mm) –561 –561 –561 –561 –561 –561 –360 –280 –200 –120 –40 40 120 200 280 360 561 561 561 561 NC: No Connection 15/17 ¡ Semiconductor Pad No. Pad name 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 COM B SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 ML9060 X-coordinate Y-coordinate (mm) 6360 6280 6200 6120 6040 5960 5880 5800 5720 5640 5560 5480 5400 5320 5240 5160 5080 5000 4920 4840 4760 4680 4600 4520 4440 4360 4280 4200 4120 4040 3960 3880 3800 3720 3640 3560 3480 3400 3320 3240 3160 3080 3000 2920 2840 (mm) 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 Pad No. Pad name 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 X-coordinate Y-coordinate (mm) 2760 2680 2600 2520 2440 2360 2280 2200 2120 2040 1960 1880 1800 1720 1640 1560 1480 1400 1320 1240 1160 1080 1000 920 840 760 680 600 520 440 360 280 200 120 40 –40 –120 –200 –280 –360 –440 –520 –600 –680 –760 (mm) 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 16/17 ¡ Semiconductor Pad No. Pad name 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 SEG132 SEG133 SEG134 ML9060 X-coordinate Y-coordinate (mm) –840 –920 –1000 –1080 –1160 –1240 –1320 –1400 –1480 –1560 –1640 –1720 –1800 –1880 –1960 –2040 –2120 –2200 –2280 –2360 –2440 –2520 –2600 –2680 –2760 –2840 –2920 –3000 –3080 –3160 –3240 –3320 –3400 –3480 –3560 –3640 –3720 –3800 –3880 –3960 –4040 –4120 –4200 –4280 –4360 (mm) 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 Pad No. Pad name 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 SEG135 SEG136 SEG137 SEG138 SEG139 SEG140 SEG141 SEG142 SEG143 SEG144 SEG145 SEG146 SEG147 SEG148 SEG149 SEG150 SEG151 SEG152 SEG153 SEG154 SEG155 SEG156 SEG157 SEG158 SEG159 SEG160 NC NC NC NC NC BLANKOUT SEG-TESTOUT LOADOUT CLOCKOUT NC DATAOUT NC NC X-coordinate Y-coordinate (mm) –4440 –4520 –4600 –4680 –4760 –4840 –4920 –5000 –5080 –5160 –5240 –5320 –5400 –5480 –5560 –5640 –5720 –5800 –5880 –5960 –6040 –6120 –6200 –6280 –6360 –6440 –6520 –6600 –6680 –7121 –7121 –7121 –7121 –7121 –7121 –7121 –7121 –7121 –7121 (mm) 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 561 360 280 200 120 40 –40 –120 –200 –280 –360 17/17 E2Y0002-29-11 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents cotained herein may be reprinted or reproduced without our prior permission. 9. MS-DOS is a registered trademark of Microsoft Corporation. Copyright 1999 Oki Electric Industry Co., Ltd. Printed in Japan