E2C0017-27-Y2 ¡ Semiconductor MSC1201-xx ¡ Semiconductor This version:MSC1201-xx Nov. 1997 Previous version: Jul. 1996 60-Bit VFD Tube Driver with Digital Dimming and PWM Conversion Function GENERAL DESCRIPTION The MSC1201-xx is a 1/2 duty vacuum fluorescent display tube driver implemented in Bi-CMOS technology. This LSI consists of 64-bit shift registers, 64 latches, PWM conversion circuit, a digital dimming circuit, 30-segment driver and 2-grid driver. As the MSC1201-xx has both a digital dimming circuit and a PWM conversion circuit which converts PWM signal for lamp dimming control to PWM signal for VFD tube dimming control, the dimming control can be realized without any external circuit. The interface with a MCU can be done only with 3 wires (CS, DATA and CLOCK signals). Also, DATA and CLOCK signal lines can be shared with other peripherals because of chip select function by CS signal. For the general purpose code, the code number is -01. (Product name: MSC1201-01GS-2K) For a custom code, the code number will be ordered at any time. FEATURES • Single supply voltage : VDD = 8 V to 18 V (built-in 5 V logic regurator) • Operating temperature range : Ta = –40°C to +85°C • 30-segment driver outputs (IOH = –6 mA at VOH = VDD – 0.8 V) • 2-grid pre-driver outputs (IOH = –30 mA at VOH = VDD – 0.8 V) • Built-in digital dimming circuit (11-bit resolution) • Built-in oscillation circuit (external R and C, fOSC = 2.0 MHz) • Built-in Power-On-Reset circuit. • Lamp PWM signal Æ Buil-in PWM conversion circuit for vacuum fluorescent display tube. • Built-in RC Oscillation (external R and C) • Correspondence between shift register and output segment is settable optionally using built in mask programmable 30 ¥ 30 PLA. • Package : 44-pin plastic QFP (QFP44–P–910-0.80–2K)(Product name: MSC1201-xxGS-2K) xx indicates the code number 1/20 ¡ Semiconductor MSC1201-xx BLOCK DIAGRAM SEG1 SEG30 GRID1 GRID2 5V VDD GND 5 V Reg & POR Circuit POR CS DATA CLOCK 2-Grid Driver 30-Segment Driver 30 ¥ 30 PLA Matrix Control Circuit Multiplexer Latch S1 D CK 64-Bit Shift Register D48-59 R DATA OUT M3 M2 M1 M0 Test Mode Mode Selector POR S1 S2 S3 S4 OSC0 OSC1 RC OSC PWMIN VK Timing Generator R POR PWM Conversion Circuit R S2 S2 INH POR Selector Digital Dimming Circuit R S3 S4 TEST1 POR 2/20 ¡ Semiconductor MSC1201-xx INPUT AND OUTPUT CONFIGURATION • Schematic Diagrams of Logic Portion Input • Schematic Diagrams of Logic Portion Input Circuit 1 Circuit 1 VDD (5V Reg.) VDD (5V Reg.) TEST1 INH INPUT GND GND GND GND • Schematic Diagrams of Logic Portion Output • Schematic Diagrams of Driver Output Circuit Circuit (5V Reg.) (5V Reg.) VDD OUTPUT OUTPUT GND GND VDD GND GND 3/20 ¡ Semiconductor MSC1201-xx 34 SEG11 35 SEG12 36 SEG13 37 SEG14 38 SEG15 39 SEG16 40 SEG17 41 SEG18 42 SEG19 43 SEG20 44 SEG21 PIN CONFIGURATION (TOP VIEW) 28 SEG5 SEG28 7 27 SEG4 SEG29 8 26 SEG3 SEG30 9 25 SEG2 GRID1 10 24 SEG1 GRID2 11 23 DATAOUT PWM IN 22 SEG27 6 INH 21 29 SEG6 DATA 20 SEG26 5 CLOCK 19 30 SEG7 CS 18 SEG25 4 GND 17 31 SEG8 OSC0 16 SEG24 3 OSC1 15 32 SEG9 VK 14 SEG23 2 TEST1 13 33 SEG10 VDD 12 SEG22 1 44-Pin Plastic Package 4/20 ¡ Semiconductor MSC1201-xx PIN DESCRIPTIONS Pin Symbol I/O 1-9 24-44 SEG1-30 O Segment output pin for VFD Description 10, 11 GRID1, 2 O Grid 1 and Grid 2 output pins for VFD 16 OSC0 I 15 OSC1 O RC oscillation pins. Connect a resistor between OSC1 and OSC0 pin and a capacitor between OSC0 and GND pin. 18 CS I Chip select input. Only when the high level is input to this pin, interfacing with a MCU is available through "CLOCK" and "DATA" pins. Therefore, 2-signal lines of "CLOCK" and "DATA" can be shared with other peripherals. 20 DATA I Input which receives display data and digital dimming data from a MCU. Data is shifted in at the rising edge of the shift clock. 19 CLOCK I 23 DATA OUT O Serial clock input. Data that is input through "DATA" pin is input and output by synchronization with the rising edge of the serial clock. Serial data output. Data is shifted out at the rising edge of the serial clock with the delay of 64-bit time. This pin is used for cascading this LSI with other drivers such as a LED driver. 22 PWMIN I PWM signal input. 14 VK I Dimming select input. When the high level is input, daylight-mode output duty cycle is about 100% for each grid time for PWM conversion and digital dimming mode. When the low level is input, the dark-mode output duty cycle is determined by the duty cycle of the PWM signal input to PWM IN and the digital dimming output duty cycle is determined by digital dimming data. 21 INH I 13 TEST1 I 12 17 VDD — Blank Display input with a built-in pull-up resistor. When set to "L", all the drivers output "L". When display duly is not controlled by this signal, leave this pin open. Test signal input pin. As this pin is used for shipping test of the LSI, leave open in the normal operation mode. Power Supply GND — Ground 5/20 ¡ Semiconductor MSC1201-xx ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit VDD — –0.3 to +20 V Input Voltage VIN All inputs –0.3 to +6 V Storage Temperature Range TSTG — –65 to +150 °C PD Ta = 85°C 0.4 W Supply Voltage Power Dissipation RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Min. Typ. Max. Unit Supply Voltage VDD — 8 — 18 V High Level Input Voltage (1) VIH1 All inputs except OSC0, VK 3.8 — 5.5 V High Level Input Voltage (2) VIH2 VK 3.8 — VDD V High Level Input Voltage (3) VIH3 OSC0 4.5 — 5.5 V Low Level Input Voltage (1) VIL1 All inputs except OSC0 0 — 0.8 V Low Level Input Voltage (2) VIL2 OSC0 0 — 0.5 V Clock Frequency fC — — — 250 kHz OSC Frequency fOSC R = 4.7kW, C=22pF — 2 — MHz Frame Frequency FFR fOSC = 2 MHz — 224 — Hz Operating Temperature Range Top — –40 — 85 ˚C 6/20 ¡ Semiconductor MSC1201-xx ELECTRICAL CHARACTERISTICS DC Characteristics (Ta = –40 to +85˚C, VDD = 8 to 18 V) Parameter Symbol Condition Min. Max. Unit Hight Level Input Voltage (1) *1 VIH1 — 3.8 5.5 V Hight Level Input Voltage (2) *9 VIH2 — 3.8 VDD V Hight Level Input Voltage (3) *2 VIH3 — 4.5 5.5 V Low Level Input Voltage (1) *10 VIL1 — 0 0.8 V Low Level Input Voltage (2) *2 VIL2 — 0 0.5 V Hight Level Input Current (1) *3 IIH1 VIH1 = 5.0 V –5 5 mA Hight Level Input Current (2) *4 IIH2 VIH2 = 5.0 V –80 80 mA Hight Level Input Current (3) *5 IIH3 VIH3 = 5.0 V –60 60 mA Low Level Input Current (1) *3 IIL1 VIL1 = 0.0 V –5 5 mA Low Level Input Current (2) *4 IIL2 VIL2 = 0.0 V –0.6 –0.1 Low Level Input Current (3) *5 IIL3 VIL3 = 0.0 V –320 –30 mA mA High Level Output Voltage (1) *6 VOH1 VDD = 9.5 V IOH1 = –6 mA VDD-0.8 — V High Level Output Voltage (2) *7 VOH2 VDD = 9.5 V IOH2 = –30 mA VDD-0.8 — V 4 6 V 4.5 6 V — 2 V — 1 V — 0.3 V — 0.8 V — 20 mA VOH3-1 High Level Output Voltage (3) *8 VOH3-2 VOL1-1 Low Level Output Voltage (1) *6 *7 VOL1-2 VOL1-3 Low Level Output Voltage (2) *8 VOL2 Power Supply Current IDD Notes: *1 *2 *3 *4 *5 *6 *7 *8 *9 *10 VDD = 9.5 V IOH3-1 = –200 mA VDD = 9.5 V Output Open VDD = 9.5 V IOL1-1 = 500 mA VDD = 9.5 V IOL1-2 = 200 mA VDD = 9.5 V IOL1-3 = 2 mA VDD = 9.5 V IOL2 = 200 mA fOSC = 2 MHz, No load Applicable to all input pins (except VK, OSC0 pin) Applicable to OSC0 pin Applicable to CLOCK, DATA, CS, VK, and PWMIN pin Applicable to TEST1 Applicable to INH pin Applicable to pins SEG1 to SEG30 Applicable to GRID1 and GRID2 Applicable to DATA OUT pin Applicable to VK pin Applicable to all input pins (except OSC0 pin) 7/20 ¡ Semiconductor MSC1201-xx AC Characteristics (Ta = –40 to +85°C, VDD = 8 to 18 V) Symbol Condition Min. Max. Unit Oscillation Frequency Parameter fOSC R = 4.7kW, C = 22pF 1.2 2.8 MHz OSC0 Input Frequency fOSCI External input only 1.5 2.5 MHz fC — — 250 kHz Clock Pulse Width tCW — 1.3 — ms Data Set-up Time tDS — 1 — ms Data Hold Time tDH — 200 — ns CS Pulse Width tCSW — 68 — ms CS Off Time tCSL — 30 — ms CS Set-up Time CS-Clock Time tCSS — 2 — ms CS Hold Time Clock-CS Time tCSH — 2 — ms Data Output Delay Clock-Data out Time tPD — — 1 ms SEG & GRID Output Delay from CS tODS CL = 100pF — 8 ms tR CL = 100pF, t = 20% to 80% or 80% to 20% — 5 ms Power-on CS Time tPCS — 300 — ms Power-off Hold Time tPOF When the Unit mounted VDD = 0 V 5 — ms Power-on Rise Time tPRZ When the Unit mounted — 100 ms Frame Frequency FFR — 146 342 Hz Clock Frequency Slew Rate (All Drivers) PWM Conversion Characteristics (Ta = –40 to +85°C, VDD = 8 to 18 V) Parameter Symbol Condition Min. Typ. Max. Unit fPWM — 176 256 336 Hz Input Threshold Voltage vR — 0.8 2.5 3.8 V PWM Input Duty Cycle dU — 20 — 100 % PWM Input Frequency 8/20 ¡ Semiconductor MSC1201-xx TIMING DIAGRAM tCSW CS 3.8V 0.8V tCSL fC tCSS tCW CLOCK tCW 3.8V 0.8V tDS DATA tCSH 3.8V 0.8V tDS tDH VALID tDH VALID Fig. 1 Data Input Timing tCW CLOCK tCW 3.8V 0.8V tPD DATA tPD 3.8V 0.8V Fig. 2 Data Output Timing 9/20 ¡ Semiconductor MSC1201-xx TIMING DIAGRAM (Continued) VDD 8V tPRZ tPOF tPCS CS 3.8V 0.8V Fig. 3 Power-On Timing tCSW CS 3.8V 0.8V tODS tODS tR tR 80% SEG1-30 GRID1, 2 20% Fig. 4 SEG & GRID Driver Output Timing PWM Frequency (fPWM) Input Threshold Voltage A Duty Cycle dU = A/(A+B) B PWMIN Fig. 5 PWM Input Waveform 10/20 ¡ Semiconductor MSC1201-xx FUNCTIONAL DESCRIPTION Power-On-Reset The status of the internal circuit after power-on reset is as follows; 1) Shift registers and latches are reset. 2) PWM conversion mode is selected. DATA Input Data input is available only when the high level is applied to the "CS" pin. Input data is shifted into shift registers through "Data" pin at the rising edge of the shift clock. The data is automatically loaded to latches at the falling edge of "CS" signal. When M0 = "0", input data should include display data (total of 64 bits data should be input.) and when M0 = "1", input data should exclude display data (Total of 16-bit data should be input.) [Data Format] 1) Display Data Input Mode Input Data : 64 bits VF Display Data : 60 bits Mode Select Data : 4 bits First In Bit 64 63 62 D59 D58 D57 Display Data 53 52 51 50 49 48 D48 M3 M2 M1 M0 D47 Mode Data 3 2 1 D2 D1 D0 Display Data 2) Segment outputs/Shift Registers Bit Correspondence Table The content of the table depends on a PLA code. This table is modeled on the general purpose code of -01. Segment output positions can be changed dependent on the PLA code, but the segment-bit correspondence cannot be changed. 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SEGn 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GRID1 Bit 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 GRID2 11/20 ¡ Semiconductor MSC1201-xx 3) Digital Dimming Data Input Mode Input Data : 16 bits Digital Dimming Data : 11 bits Mode Select Data : 4 bits Bit 64 xx 63 11 62 10 61 9 60 8 59 7 58 6 57 5 56 4 55 3 54 2 53 1 MSB 52 M 3 51 M 2 50 M 1 49 M 0 First in LSB Dimming Data (MSB) Mode Data (LSB) DUTY CYCLE X 0 0 0 0 INPUT DATA 0 0 0 0 0 0 0 0/2048 X 0 0 0 0 0 0 0 0 0 0 1 1/2048 X 1 1 1 1 1 1 1 0 0 0 0 2032/2048 X 1 1 1 1 1 1 1 1 1 1 1 2032/2048 4) Function Mode Mode M3 M2 M1 M0 Function S1 0 0 0 0 Display Data Input S2 0 0 0 1 Digital Dimming Data Input S3 0 0 1 0 PWM Conversion Select & Display Data Input S4 0 0 1 1 PWM Conversion Select S5 0 1 0 0 Digital Dimming Select & Display Data Input S6 0 1 0 1 Digital Dimming Select 12/20 ¡ Semiconductor MSC1201-xx PWM Conversion In the PWM conversion mode, "lamp PWM", which is used for dimming control of back-light for instrument clusters or other displays, is used to generate the PWM signal for VFD tube dimming control. The lamp PWM input to "PWM IN" pin is converted to PWM signal for VFD tube with a built-in PWM conversion look-up table (User-Programmable Mask ROM). The duty cycle of the lamp PWM is defined as follows: PWMIN A B 5V PWM Input Frequency = 256 ± 80Hz Duty Cycle = A / (A+B) Note: The duty cycle of the lamp PWM signal is measured with a reference point of 2.5 V typ. As the reference point of 2.5 V is the threshold voltage of "PWM IN" pin, it deviates to some value between 0.8 V and 3.8 V due to process parameter deviation. Therefore, the PWM conversion error increases as the rise/fall time of the lamp PWM increases. GRID/SEG Driver Operation and Digital/Analog Dimming Operation Figure 6 shows an output timing of the GRID and SEG Driver when the VK is "H" level. Output timings of the GRID and SEG drivers are shown in figure 7 for the digital dimming mode operation in figure 8 for the PWM conversion mode operation. (1) GRID and SEG drivers output timings when VK = "H" 1 Frame (4096-bit times) fFR GRID1 16-bit times GRID2 2032-bit times 6-bit times SEG1-30 2038-bit times 10-bit times Fig. 6 GRID and SEG Output Timing (VK = "H") Note: One bit time = 2/fOSC = 1 ms typ. 13/20 ¡ Semiconductor MSC1201-xx (2) GRID and SEG driver output timing when VK = "L" and in Digital Dimming Mode. 1 Frame (4096-bit times) fFR GRID1 16-bit times GRID2 Max. 2032-bit times 6-bit times SEG1-30 Max. 2038-bit times 10-bit times Fig. 7 GRID and SEG Output Timing (digital dimming mode) Notes: • The above indicates the timing for the digital dimming mode with the duty cycle of 2032/2048 at VPARK = "L" level. • The On-times for GRID and SEG are specified with the 11 bits of the digital dimming data. • One bit time = 2/fOSC = 1 ms typ. (3) GRID and SEG driver output timings when VK = "L" and in PWM Conversion Mode 1 Frame (2048-bit times) fFR GRID1 GRID2 8-bit times Max. 256-bit times 3-bit times SEG1-30 Max. 259-bit times Fig. 8 GRID and SEG Driver Output Timing (PWM conversion mode) Notes: • The above indicates the GRID and SEG Drivers Timing when the PWM conversion mode at VK = "L" level is selected. • One bit time = 4/fOSC = 2 ms typ. 14/20 ¡ Semiconductor MSC1201-xx PWM Conversion Table MSC1201-01 STEP No. LAMP PWM DUTY CYCLE VF PWM DUTY CYCLE STEP No. LAMP PWM DUTY CYCLE VF PWM DUTY CYCLE 0 100.00% 12.50% 33 58.75% 6.05% 1 98.75% 12.30% 34 57.50% 5.86% 2 97.50% 12.11% 35 56.25% 5.66% 3 96.25% 11.91% 36 55.00% 5.47% 4 95.00% 11.72% 37 53.75% 5.27% 5 93.75% 11.52% 38 52.50% 5.08% 6 92.50% 11.33% 39 51.25% 4.88% 7 91.25% 11.13% 40 50.00% 4.69% 8 90.00% 10.94% 41 48.75% 4.49% 9 88.75% 10.74% 42 47.50% 4.30% 46.25% 4.10% 3.91% 3.71% 10 87.50% 10.55% 43 11 86.25% 10.35% 44 12 10.16% 9.96% 45 13 85.00% 83.75% 45.00% 43.75% 46 42.50% 3.52% 14 82.50% 9.77% 47 41.25% 3.32% 15 81.25% 9.57% 48 40.00% 3.13% 16 80.00% 9.38% 49 38.75% 2.93% 17 78.75% 9.18% 50 37.50% 2.73% 18 77.50% 8.98% 51 36.25% 2.54% 19 76.25% 8.79% 52 35.00% 2.34% 20 75.00% 8.59% 53 33.75% 2.15% 1.95% 21 73.75% 8.40% 54 32.50% 22 72.50% 8.20% 55 31.25% 1.76% 1.56% 23 71.25% 8.01% 56 30.00% 24 70.00% 7.81% 57 28.75% 1.37% 1.17% 25 68.75% 7.62% 58 27.50% 26 67.50% 7.42% 59 26.25% 0.98% 27 66.25% 7.23% 60 25.00% 0.78% 28 65.00% 7.03% 61 23.75% 0.59% 29 63.75% 6.84% 62 22.50% 0.39% 30 62.50% 6.64% 63 21.25% 0.20% 31 61.25% 6.45% 64 20.00% 0.10% 32 60.00% 6.25% 15/20 ¡ Semiconductor MSC1201-xx PLA Code Table MSC1201-01 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 BIT 1, 31 BIT 2, 32 BIT 3, 33 BIT 4, 34 BIT 5, 35 BIT 6, 36 BIT 7, 37 BIT 8, 38 BIT 9, 39 BIT10, 40 BIT11, 41 BIT12, 42 BIT13, 43 BIT14, 44 BIT15, 45 BIT16, 46 BIT17, 47 BIT18, 48 BIT19, 49 BIT20, 50 BIT21, 51 BIT22, 52 BIT23, 53 BIT24, 54 BIT25, 55 BIT26, 56 BIT27, 57 BIT28, 58 BIT29, 59 BIT30, 60 SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG 16/20 ¡ Semiconductor MSC1201-xx Pin Name Output Pin Name Output SEG1 BIT 1,31 SEG16 BIT 16,46 SEG2 BIT 2,32 SEG17 BIT 17,47 SEG3 BIT 3,33 SEG18 BIT 18,48 SEG4 BIT 4,34 SEG19 BIT 19,49 SEG5 BIT 5,35 SEG20 BIT 20,50 SEG6 BIT 6,36 SEG21 BIT 21,51 SEG7 BIT 7,37 SEG22 BIT 22,52 SEG8 BIT 8,38 SEG23 BIT 23,53 SEG9 BIT 9,39 SEG24 BIT 24,54 SEG10 BIT 10,40 SEG25 BIT 25,55 SEG11 BIT 11,41 SEG26 BIT 26,56 SEG12 BIT 12,42 SEG27 BIT 27,57 SEG13 BIT 13,43 SEG28 BIT 28,58 SEG14 BIT 14,44 SEG29 BIT 29,59 SEG15 BIT 15,45 SEG30 BIT 30,60 17/20 ¡ Semiconductor MSC1201-xx APPLICATION CIRCUITS (1) Digital Dimming Mode 1/2 Duty VF Tube 12 V SEG1 SEG30 G1,G2 VDD GND CS Microcontroller DATA CLOCK MSC1201-xx OSC1 OSC0 VK PWM IN 18/20 ¡ Semiconductor MSC1201-xx (2) PWM Conversion Mode 1/2 Duty VF Display Tube SEG1 SEG30 G1 G2 12 V VDD GND CS Microcontroller DATA MSC1201-xx CLOCK OSC1 OSC0 Daylight Mode "1" Dark Mode "0" Illumination Switch Illumination Lamp 5V VK PWMIN Dashboard Lamp Lamp PWM Signal 19/20 ¡ Semiconductor MSC1201-xx PACKAGE DIMENSIONS (Unit : mm) QFP44-P-910-0.80-2K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Epoxy resin 42 alloy Solder plating 5 mm or more Package weight (g) 0.41 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 20/20