This version: Mar. 3. 1999 Semiconductor MSC2323258D-xxBS4/DS4 2,097,152-word x 32-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE WITH EDO DESCRIPTION The MSC2323258D-xxBS4/DS4 is a fully decoded, 2,097,152-word x 32-bit CMOS dynamic random access memory module composed of four 16Mb DRAMs in SOJ packages mounted with eight decoupling capacitors on a 72-pin glass epoxy single-inline package. This module supports any application where high density and large capacity of storage memory are required. FEATURES · 2,097,152-word x 32-bit organization · 72-pin Single Inline Memory Module MSC2323258D-xxBS4 : Gold tab MSC2323258D-xxDS4 : Solder tab · Single +5V supply ± 10% tolerance · Input : TTL compatible · Output : TTL compatible, 3-state · Refresh : 1024cycles/16ms · /CAS before /RAS refresh, hidden refresh, /RAS only refresh capability · Fast page mode with EDO capability PRODUCT FAMILY Access Time (Max.) Cycle Power Dissipation Time Family tRAC tAA tCAC (Min.) Operating (Max.) MSC2323258D-60BS4/DS4 60ns 30ns 15ns 104ns 1430mW MSC2323258D-70BS4/DS4 70ns 35ns 20ns 124ns 1320mW Standby (Max.) 22mW Semiconductor MSC2323258D MODULE OUTLINE (Unit : mm) MSC2323258D-xxBS4/DS4 9.3Max. 107.95±0.2*1 101.19Typ. 3.38Typ. ( 3.18 19.0±0.2 Typ. Typ. 10.16 6.35 2.03Typ. 6.35Typ. 5.7Min. 1 72 1.27±0.1 R1.57 6.35 1.04Typ. 95.25 *1 The common size difference of the board width 12.5mm of its height is specified as ±0.2. The value above 12.5mm is specified as ±0.5. +0.1 1.27 -0.08 Semiconductor MSC2323258D PIN CONFIGURATION Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 VSS 19 NC 37 NC 55 DQ11 2 DQ0 20 DQ4 38 NC 56 DQ27 3 DQ16 21 DQ20 39 VSS 57 DQ12 4 DQ1 22 DQ5 40 /CAS0 58 DQ28 5 DQ17 23 DQ21 41 /CAS2 59 VCC 6 DQ2 24 DQ6 42 /CAS3 60 DQ29 7 DQ18 25 DQ22 43 /CAS1 61 DQ13 8 DQ3 26 DQ7 44 /RAS0 62 DQ30 9 DQ19 27 DQ23 45 /RAS1 63 DQ14 10 VCC 28 A7 46 NC 64 DQ31 11 NC 29 NC 47 /WE 65 DQ15 12 A0 30 VCC 48 NC 66 NC 13 A1 31 A8 49 DQ8 67 PD1 14 A2 32 A9 50 DQ24 68 PD2 15 A3 33 /RAS3 51 DQ9 69 PD3 16 A4 34 /RAS2 52 DQ25 70 PD4 17 A5 35 NC 53 DQ10 71 NC 18 A6 36 NC 54 DQ26 72 VSS Presence Detect Pins Pin No. Pin Name MSC2323258D -60BS4/DS4 MSC2323258D -70BS4/DS4 67 PD1 NC NC 68 PD2 NC NC 69 PD3 NC VSS 70 PD4 NC NC Semiconductor MSC2323258D BLOCK DIAGRAM A0-A9 /CAS0 /CAS1 /WE A0-A9 /RAS0 /RAS /LCAS /UCAS /WE /OE VSS A0-A9 /RAS2 /RAS /LCAS /UCAS /WE /OE VSS /CAS2 /CAS3 VCC C1-C8 VSS DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 A0-A9 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 VCC DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 VCC /UCAS DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 A0-A9 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 VCC DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 VCC /RAS /RAS1 /LCAS /WE /OE VSS /RAS /LCAS /UCAS /WE /OE VSS /RAS3 Semiconductor MSC2323258D ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Rating Unit VIN, VOUT -1.0 to +7.0 V Voltage on VCC Supply Relative to VSS VCC -1.0 to +7.0 V Short Circuit Output Current IOS 50 mA Power Dissipation PD * 4 W Operating Temperature TOPR 0 to +70 °C Storage Temperature TSTG -40 to +125 °C Voltage on Any Pin Relative to VSS * Ta = 25°C Recommended Operating Conditions ( Ta = 0°C to +70°C ) Parameter Symbol Min. Typ. Max. Unit VCC 4.5 5.0 5.5 V VSS 0 0 0 V Input High Voltage VIH 2.4 - 6.5 V Input Low Voltage VIL -1.0 - 0.8 V Power Supply Voltage Capacitance ( VCC = 5V ± 10%, Ta = 25°C, f = 1 MHz ) Parameter Note: Symbol Typ. Max. Unit Input Capacitance (A0 - A9) CIN1 - 32 pF Input Capacitance (/WE) CIN2 - 35 pF Input Capacitance (/RAS0- /RAS3) CIN3 - 13 pF Input Capacitance (/CAS0- /CAS3) CIN4 - 20 pF I/O Capacitance (DQ0 - DQ31) CDQ - 25 pF Capacitance measured with Boonton Meter. Semiconductor MSC2323258D DC Characteristics (VCC = 5V ± 10%, Ta = 0°C to +70°C ) Parameter Symbo l Condition MSC2323258D -60BS4/DS4 MSC2323258D -70BS4/DS4 Min. Max. Min. Max. Unit Note Input Leakage Current ILI 0V ≤ VIN ≤ 6.5V; All other pins not under test = 0V -40 40 -40 40 µA Output Leakage Current ILO DQ disable 0V ≤ VOUT ≤ 5.5V -20 20 -20 20 µA Output High Voltage VOH IOH = -5.0mA 2.4 VCC 2.4 VCC V Output Low Voltage VOL IOL = 4.2mA 0 0.4 0 0.4 V Average Power Supply Current (Operating) ICC1 /RAS, /CAS cycling, tRC = Min. - 260 - 240 mA 1, 2 /RAS, /CAS = VIH - 8 - 8 mA 1 /RAS, /CAS ≥ VCC -0.2V - 4 - 4 mA 1 Power supply current (Standby) ICC2 Average Power Supply Current (/RAS only refresh) ICC3 /RAS cycling, /CAS = VIH, tRC = Min. - 260 - 240 mA 1, 2 Average Power Supply Current (/CAS before /RAS refresh) ICC6 /RAS cycling, /CAS before /RAS - 260 - 240 mA 1, 2 Average Power Supply Current (Fast Page Mode) ICC7 /RAS = VIL, /CAS cycling, tHPC = Min. - 260 - 240 mA 1, 3 Notes: 1. ICC Max. is specified as ICC for output open condition. 2. Address can be changed once or less while /RAS = VIL. 3. Address can be changed once or less while /CAS = VIH. Semiconductor MSC2323258D AC Characteristics (1/2) (VCC = 5V ± 10%, Ta = 0°C to +70°C ) Note: 1, 2, 3 Parameter Symbol MSC2323258D -60BS4/DS4 MSC2323258D -70BS4/DS4 Min. Max. Min. Max. Unit Note Random Read or Write Cycle Time tRC 104 - 124 - ns Fast Page Mode Cycle Time tHPC 25 - 30 - ns Access Time from /RAS tRAC - 60 - 70 ns 4, 5, 6 Access Time from /CAS tCAC - 15 - 20 ns 4, 5 Access Time from Column Address tAA - 30 - 35 ns 4, 6 Access Time from /CAS Precharge t CPA - 35 - 40 ns 4 Output Low Impedance Time from /CAS tCLZ 0 - 0 - ns 4 Data Output Hold After /CAS Low tDOH 5 - 5 - ns /CAS to Data Output Buffer Turn-off Delay Time tCEZ 0 15 0 20 ns 7, 8 /RAS to Data Output Buffer Turn-off Delay Time tREZ 0 15 0 20 ns 7, 8 /WE to Data Output Buffer Turn-off Delay Time tWEZ 0 15 0 20 ns 7 Transition Time tT 1 50 1 50 ns 3 Refresh Period tREF - 16 - 16 ms /RAS Precharge Time tRP 40 - 50 - ns /RAS Pulse Width tRAS 60 10K 70 10K ns /RAS Pulse Width (Fast Page Mode with EDO) tRASP 60 100K 70 100K ns /RAS Hold Time tRSH 10 - 13 - ns /CAS Precharge Time (Fast Page Mode with EDO) tCP 10 - 10 - ns /CAS Pulse Width tCAS 10 10K 13 10K ns /CAS Hold Time tCSH 40 - 45 - ns /CAS to /RAS Precharge Time tCRP 5 - 5 - ns /RAS Hold Time from /CAS Precharge tRHCP 35 - 40 - ns /RAS to /CAS Delay Time tRCD 14 45 14 50 ns 5 /RAS to Column Address Delay Time tRAD 12 30 12 35 ns 6 Row Address Set-up Time tASR 0 - 0 - ns Row Address Hold Time tRAH 10 - 10 - ns Column Address Set-up Time tASC 0 - 0 - ns Column Address Hold Time tCAH 10 - 13 - ns Column Address to /RAS Lead Time tRAL 30 - 35 - ns Read Command Set-up Time tRCS 0 - 0 - ns Read Command Hold Time tRCH 0 - 0 - ns 9 Read Command Hold Time referenced to /RAS tRRH 0 - 0 - ns 9 Semiconductor MSC2323258D AC Characteristics (2/2) (VCC = 5V ± 10%, Ta = 0°C to +70°C ) Note: 1, 2, 3 Parameter Symbol MSC2323258D -60BS4/DS4 MSC2323258D -70BS4/DS4 Min. Max. Min. Max. Unit Write Command Set-up Time tWCS 0 - 0 - ns Write Command Hold Time tWCH 10 - 13 - ns Write Command Pulse Width tWP 10 - 10 - ns /WE Pulse Width (DQ Disable) tWPE 10 - 10 - ns Write Command to /RAS Lead Time tRWL 10 - 13 - ns Write Command to /CAS Lead Time tCWL 10 - 13 - ns Data-in Set-up Time tDS 0 - 0 - ns Data-in Hold Time tDH 10 - 13 - ns /CAS Active Delay Time from /RAS Precharge tRPC 5 - 5 - ns /RAS to /CAS Set-up Time (/CAS before /RAS) tCSR 5 - 5 - ns /RAS to /CAS Hold Time (/CAS before /RAS) tCHR 10 - 10 - ns Note Semiconductor MSC2323258D Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization cycles (/RAS only refresh or /CAS before /RAS refresh) before proper device operation is achieved. 2. The AC characteristics assumes tT = 2ns. 3. VIH(Min.) and VIL(Max.) are reference levels for measuring input timing signals. Transition time (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2TTL loads and 100pF. 5. Operation within the tRCD(Max.) limit ensures that tRAC(Max.) can be met. tRCD(Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD(Max.) limit ensures that tRAC(Max.) can be met. tRAD(Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(Max.) limit, then the access time is controlled by tAA. 7. tCEZ(Max.), tREZ(Max.) and tWEZ(Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tCEZ and tREZ must be satisfied for open circuit condition. 9. tRCH or tRRH must be satisfied for a read cycle.