¡ Semiconductor MSC23837A-xxBS18/DS18 ¡ Semiconductor MSC23837A-xxBS18/DS18 8,388,608-Word ¥ 36-Bit DRAM MODULE : FAST PAGE MODE TYPE DESCRIPTION The Oki MSC23837A-xxBS18/DS18 is a fully decoded 8,388,608-word ¥ 36-bit CMOS dynamic random access memory composed of eighteen 16-Mb DRAMs (4M ¥ 4) in SOJ packages mounted with decoupling capacitors on a 72-pin glass epoxy SIMM Package. This module is generally used for memory expansion in parity applications such as workstations. FEATURES • 8,388,608-word ¥ 36-bit (ECC) organization • 72-pin SIMM MSC23837A-xxBS18 : Gold tab MSC23837A-xxDS18 : Solder tab • Single 5 V supply ±10% tolerance • Input : TTL compatible • Output : TTL compatible, 3-state • Refresh : 4096 cycles/64 ms • CAS before RAS refresh, CAS before RAS hidden refresh, RAS-only refresh capability • Multi-bit test mode capability • Fast Page Mode capability PRODUCT FAMILY Family Access Time (Max.) tRAC tAA tCAC tOEA Power Dissipation Cycle Time Operating (Max.) Standby (Max.) (Min.) MSC23837A-60BS18/DS18 60 ns 30 ns 15 ns 15 ns 110 ns 5197.5 mW MSC23837A-70BS18/DS18 70 ns 35 ns 20 ns 20 ns 130 ns 4702.5 mW 99 mW 215 MSC23837A-xxBS18/DS18 ¡ Semiconductor PIN CONFIGURATION (Unit : mm) MSC23837A-xxBS18/DS18 *1 107.95 ±0.2 101.19 Typ. 3.38 ±0.2 25.4 ±0.2 9.3 Max. φ 3.18 Typ. Typ. 10.16 6.35 1 72 2.03 Typ. 3.5 Min. R1.57 6.35 Typ. 1.27 ±0.1 6.5 Min. +0.1 1.27 –0.08 1.04 Typ. 6.35 95.25 *1 The common size difference of the board width 12.5 mm of its height is specified as ±0.2. The value above 12.5 mm is specified as ±0.5. Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 VSS 16 A4 31 A8 46 DQ21 61 DQ33 2 DQ0 17 A5 32 A9 47 WE 62 DQ34 3 DQ1 18 A6 33 NC 48 NC 63 DQ35 4 DQ2 19 OE 34 NC 49 DQ22 64 NC 5 DQ3 20 DQ8 35 DQ17 50 DQ23 65 NC 6 DQ4 21 DQ9 36 DQ18 51 DQ24 66 NC 7 DQ5 22 DQ10 37 DQ19 52 DQ25 67 PD1 8 DQ6 23 DQ11 38 DQ20 53 DQ26 68 PD2 9 DQ7 24 DQ12 39 VSS 54 DQ27 69 PD3 10 VCC 25 DQ13 40 CAS0 55 DQ28 70 PD4 11 PD5 26 DQ14 41 A10 56 DQ29 71 NC 12 A0 27 DQ15 42 A11 57 DQ30 72 VSS 13 A1 28 A7 43 CAS1 58 DQ31 14 A2 29 DQ16 44 RAS0 59 VCC 15 A3 30 VCC 45 RAS1 60 DQ32 Presence Detect Pins 216 Pin No. Pin Name MSC23837A -60BS18/DS18 MSC23837A -70BS18/DS18 67 PD1 NC NC 68 PD2 VSS VSS 69 PD3 NC VSS 70 PD4 NC NC 11 PD5 VSS VSS ¡ Semiconductor MSC23837A-xxBS18/DS18 BLOCK DIAGRAM A0 - A11 RAS0 CAS0 WE OE A0 - A11 DQ RAS DQ CAS DQ DQ WE OE VSS VCC DQ0 DQ1 DQ2 DQ3 DQ A0 - A11 RAS DQ CAS DQ WE DQ OE VSS VCC A0 - A11 DQ RAS DQ CAS DQ DQ WE OE VCC VSS DQ20 DQ21 DQ22 DQ23 DQ A0 - A11 RAS DQ CAS DQ WE DQ OE VSS VCC A0 - A11 DQ RAS DQ CAS DQ DQ WE OE VCC VSS DQ4 DQ5 DQ6 DQ7 DQ A0 - A11 RAS DQ CAS DQ WE DQ OE VSS VCC A0 - A11 DQ RAS DQ CAS DQ DQ WE OE VCC VSS DQ24 DQ25 DQ26 DQ27 DQ A0 - A11 RAS DQ CAS DQ WE DQ OE VSS VCC A0 - A11 DQ RAS DQ CAS DQ DQ WE OE VCC VSS DQ8 DQ9 DQ10 DQ11 DQ A0 - A11 RAS DQ CAS DQ WE DQ OE VSS VCC A0 - A11 DQ RAS DQ CAS DQ DQ WE OE VCC VSS DQ28 DQ29 DQ30 DQ31 DQ A0 - A11 RAS DQ CAS DQ WE DQ OE VSS VCC A0 - A11 DQ RAS DQ CAS DQ DQ WE OE VCC VSS DQ12 DQ13 DQ14 DQ15 DQ A0 - A11 RAS DQ CAS DQ WE DQ OE VSS VCC A0 - A11 DQ RAS DQ CAS DQ DQ WE OE VCC VSS DQ32 DQ33 DQ34 DQ35 DQ A0 - A11 RAS DQ CAS DQ WE DQ OE VSS VCC A0 - A11 DQ RAS DQ CAS DQ WE DQ OE VSS VCC DQ16 DQ17 DQ18 DQ19 DQ A0 - A11 RAS DQ CAS DQ WE DQ OE VSS VCC RAS1 CAS1 VCC VSS C1 C18 217 MSC23837A-xxBS18/DS18 ¡ Semiconductor ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Rating Unit Voltage on Any Pin Relative to VSS VIN, VOUT –1.0 to 7.0 V Voltage VCC Supply Relative to VSS VCC –1.0 to 7.0 V Short Circuit Output Current IOS 50 mA Power Dissipation PD 18 W Operating Temperature Topr 0 to 70 °C Storage Temperature Tstg –40 to 125 °C Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions (Ta = 0°C to 70°C) Symbol Min. Typ. Max. Unit VCC 4.5 5.0 5.5 V VSS 0 0 0 V Input High Voltage VIH 2.4 — 6.5 V Input Low Voltage VIL –1.0 — 0.8 V Parameter Power Supply Voltage Capacitance (Ta = 25°C, f = 1 MHz) Symbol Typ. Max. Unit CIN1 — 122 pF CIN2 — 73 pF Input Capacitance (WE, OE) CIN3 — 140 pF I/O Capacitance (DQ0 - DQ35) CDQ — 26 pF Parameter Input Capacitance (A0 - A11) Input Capacitance (RAS0, RAS1, CAS0, CAS1) Note : Capacitance measured with Boonton Meter. 218 ¡ Semiconductor MSC23837A-xxBS18/DS18 DC Characteristics (VCC = 5 V ±10%, Ta = 0°C to 70°C) MSC23837A Parameter Symbol Condition MSC23837A -60BS18/DS18 -70BS18/DS18 Min. Max. Min. Max. –180 180 –180 180 µA –20 20 –20 20 µA Unit Note 0 V £ VI £ 6.5 V; Input Leakage Current ILI All other pins not under test = 0 V DOUT disable Output Leakage Current ILO Output High Voltage VOH IOH = –5.0 mA 2.4 VCC 2.4 VCC V Output Low Voltage VOL IOL = 4.2 mA 0 0.4 0 0.4 V — 945 — 855 mA 1, 2 — 36 — 36 mA 1 — 18 — 18 mA 1 — 945 — 855 mA 1, 2 — 945 — 855 mA 1, 2 — 855 — 765 mA 1, 3 Average Power Supply Current ICC1 (Operating) Power Supply Current (Standby) RAS, CAS cycling, tRC = Min. RAS, CAS = VIH ICC2 RAS, CAS ≥ VCC –0.2 V RAS cycling, Average Power Supply Current 0 V £ VO £ 5.5 V ICC3 CAS = VIH, (RAS-only Refresh) tRC = Min. Average Power RAS cycling, Supply Current ICC6 (CAS before RAS Refresh) tRC = Min. RAS = VIL, Average Power Supply Current (Fast Page Mode) CAS before RAS, ICC7 CAS cycling, tPC = Min. Notes: 1. ICC Max. is specified as ICC for output open condition. 2. Address can be changed once or less while RAS=VIL. 3. Address can be changed once or less while CAS=VIH. 219 MSC23837A-xxBS18/DS18 ¡ Semiconductor AC Characteristics (1/2) Parameter Random Read or Write Cycle Time Read Modify Write Cycle Time (VCC = 5 V ±10%, Ta = 0°C to 70°C) Symbol MSC23837A MSC23837A -60BS18/DS18 -70BS18/DS18 Note 1,2,3,11,12 Unit Note Min. Max. Min. Max. tRC 110 — 130 — ns tRWC 155 — 185 — ns tPC 40 — 45 — ns tPRWC 85 — 100 — ns Access Time from RAS tRAC — 60 — 70 Access Time from CAS tCAC — 15 — 20 ns 4, 5, 6 ns 4, 5 Access Time from Column Address tAA — 30 — 35 ns 4, 6 Access Time from CAS Precharge tCPA — 35 — 40 ns 4 Access Time from OE tOEA — 15 — 20 ns 4 Output Low Impedance Time from CAS tCLZ 0 — 0 — ns 4 Output Buffer Turn-off Delay Time tOFF 0 15 0 20 ns 7 OE to Data Output Buffer Turn-off Delay Time tOEZ 0 15 0 20 ns 7 Transition Time tT 3 50 3 50 ns 3 Refresh Period tREF — 64 — 64 ms RAS Precharge Time tRP 40 — 50 — ns RAS Pulse Width tRAS 60 10k 70 10k ns RAS Pulse Width (Fast Page Mode) tRASP 60 100k 70 100k ns RAS Hold Time tRSH 15 — 20 — ns RAS Hold Time referenced to OE tROH 10 — 10 — ns CAS Precharge Time tCP 10 — 10 — ns CAS Pulse Width tCAS 15 10k 20 10k ns CAS Hold Time tCSH 60 — 70 — ns CAS to RAS Precharge Time tCRP 10 — 10 — ns RAS Hold Time from CAS Precharge tRHCP 35 — 40 — ns RAS to CAS Delay Time tRCD 20 45 20 50 ns 5 RAS to Column Address Delay Time tRAD 15 30 15 35 ns 6 Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Row Address Set-up Time tASR 0 — 0 — ns Row Address Hold Time tRAH 10 — 10 — ns Column Address Set-up Time tASC 0 — 0 — ns Column Address Hold Time tCAH 15 — 15 — ns Column Address Hold Time from RAS tAR 50 — 55 — ns Column Address to RAS Lead Time tRAL 30 — 35 — ns 220 ¡ Semiconductor MSC23837A-xxBS18/DS18 AC Characteristics (2/2) Parameter (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1,2,3,11,12 Symbol MSC23837A MSC23837A -60BS18/DS18 Min. Max. -70BS18/DS18 Min. Max. Unit Note Read Command Set-up Time tRCS 0 — 0 — ns Read Command Hold Time tRCH 0 — 0 — ns 8 Read Command Hold Time referenced to RAS tRRH 0 — 0 — ns 8 Write Command Set-up Time tWCS 0 — 0 — ns 9 Write Command Hold Time tWCH 10 — 15 — ns Write Command Hold Time from RAS tWCR 45 — 55 — ns Write Command Pulse Width tWP 10 — 10 — ns OE Command Hold Time tOEH 15 — 20 — ns Write Command to RAS Lead Time tRWL 15 — 20 — ns Write Command to CAS Lead Time tCWL 15 — 20 — ns Data-in Set-up Time tDS 0 — 0 — ns 10 Data-in Hold Time tDH 15 — 15 — ns 10 Data-in Hold Time from RAS tDHR 50 — 55 — ns OE to Data-in Delay Time tOED 15 — 20 — ns CAS to WE Delay Time tCWD 40 — 50 — ns 9 Column Address to WE Delay Time tAWD 55 — 65 — ns 9 RAS to WE Delay Time tRWD 85 — 100 — ns 9 CAS Precharge to WE Delay Time tCPWD 9 60 — 70 — ns CAS Active Delay Time from RAS Precharge tRPC 10 — 10 — ns RAS to CAS Set-up Time (CAS before RAS) tCSR 10 — 10 — ns RAS to CAS Hold Time (CAS before RAS) tCHR 20 — 20 — ns WE to RAS Precharge Time (CAS before RAS) tWRP 10 — 10 — ns WE Hold Time from RAS (CAS before RAS) tWRH 10 — 10 — ns RAS to WE Set-up Time (Test Mode) tWTS 10 — 10 — ns RAS to WE Hold Time (Test Mode) tWTH 20 — 20 — ns 221 MSC23837A-xxBS18/DS18 Notes: ¡ Semiconductor 1. A start-up delay of 200 µs is required after power-up followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. When using the internal refresh counter, a minimum of eight CAS before RAS initialization cycles is required. 2. AC mesurement assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times are measured between VIH and VIL. 4. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, access time is controlled by tAA. 7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieves an open circuit condition and are not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.) the cycle is an early write cycle and the data output pin will remain in a high impedance state throughout the entire cycle. If tCWD ≥ tCWD (Min.), tRWD ≥ tRWD (Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), the cycle is a read modify write cycle and the data output pin will contain data read from the selected cell. If neither conditions is satisfied, the data output logic state (at access time) is undefined. 10. These parameters are referenced to CAS leading edge in an early write cycle and to WE leading edge in an OE control write cycle or a read modify write cycle. 11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet is a 4-bit parallel test function. CA0 and CA1 are not used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. The 8M ¥ 36 module can be tested as a 2M ¥ 36 module in this test mode. 12. In a test mode read cycle, the access time parameters are delayed by 5 ns. The test mode parameters are obtained by adding 5 ns to the normal read cycle values. See ADDENDUM E for AC Timing Waveforms 222