¡ Semiconductor MSM5117400B ¡ Semiconductor MSM5117400B E2G0035-17-41 4,194,304-Word ¥ 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE DESCRIPTION The MSM5117400B is a 4,194,304-word ¥ 4-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM5117400B achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM5117400B is available in a 26/24-pin plastic SOJ or 26/24-pin plastic TSOP. FEATURES • 4,194,304-word ¥ 4-bit configuration • Single 5 V power supply, ±10% tolerance • Input : TTL compatible, low input capacitance • Output : TTL compatible, 3-state • Refresh : 2048 cycles/32 ms • Fast page mode, read modify write capability • CAS before RAS refresh, hidden refresh, RAS-only refresh capability • Multi-bit test mode capability • Package options: 26/24-pin 300 mil plastic SOJ (SOJ26/24-P-300-1.27) (Product : MSM5117400B-xxSJ) 26/24-pin 300 mil plastic TSOP (TSOPII26/24-P-300-1.27-K) (Product : MSM5117400B-xxTS-K) (TSOPII26/24-P-300-1.27-L) (Product : MSM5117400B-xxTS-L) xx indicates speed rank. PRODUCT FAMILY Family Access Time (Max.) tRAC tAA tCAC tOEA Cycle Time Power Dissipation (Min.) Operating (Max.) Standby (Max.) MSM5117400B-50 50 ns 25 ns 13 ns 13 ns 90 ns 660 mW MSM5117400B-60 60 ns 30 ns 15 ns 15 ns 110 ns 605 mW MSM5117400B-70 70 ns 35 ns 20 ns 20 ns 130 ns 550 mW 5.5 mW 16M 215 , MSM5117400B ¡ Semiconductor PIN CONFIGURATION (TOP VIEW) VCC 1 26 VSS VCC 1 26 VSS VSS 26 1 VCC DQ1 2 25 DQ4 DQ1 2 25 DQ4 DQ4 25 2 DQ1 DQ2 3 24 DQ3 DQ2 3 24 DQ3 DQ3 24 3 DQ2 WE 4 23 CAS WE 4 23 CAS CAS 23 4 WE RAS 5 22 OE RAS 5 22 OE OE 22 5 RAS NC 6 21 A9 NC 6 21 A9 A9 21 6 NC A10 8 19 A8 A10 8 19 A8 A8 19 8 A10 A0 9 18 A7 A0 9 18 A7 A7 18 9 A0 A1 10 17 A6 A1 10 17 A6 A6 17 10 A1 A2 11 16 A5 A2 11 16 A5 A5 16 11 A2 A3 12 15 A4 A3 12 15 A4 A4 15 12 A3 VCC 13 14 VSS VCC 13 14 VSS VSS 14 13 VCC 26/24-Pin Plastic SOJ 26/24-Pin Plastic TSOP (K Type) Pin Name A0 - A10 Note : 16M 216 Function Address Input RAS Row Address Strobe CAS Column Address Strobe DQ1 - DQ4 Data Input/Data Output OE 26/24-Pin Plastic TSOP (L Type) Output Enable WE Write Enable VCC Power Supply (5 V) VSS Ground (0 V) NC No Connection The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. ¡ Semiconductor MSM5117400B BLOCK DIAGRAM RAS Timing Generator Timing Generator CAS 11 Column Address Buffers 11 Write Clock Generator Column Decoders WE OE 4 Internal Address Counter A0 - A10 Refresh Control Clock Sense Amplifiers 4 I/O Selector Row Address Buffers 11 Row Decoders Word Drivers 4 4 4 4 11 Output Buffers Input Buffers DQ1 - DQ4 4 Memory Cells VCC On Chip VBB Generator On Chip IVCC Generator VSS 16M 217 MSM5117400B ¡ Semiconductor ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Symbol Rating Unit Voltage on Any Pin Relative to VSS VIN,VOUT –0.5 to VCC + 0.5 V Voltage on VCC Supply Relative to VSS VCC –0.5 to 7 V Short Circuit Output Current IOS 50 mA Power Dissipation PD* 1 W Operating Temperature Topr 0 to 70 °C Storage Temperature Tstg –55 to 150 °C Parameter *: Ta = 25°C Recommended Operating Conditions (Ta = 0°C to 70°C) Parameter Power Supply Voltage Symbol Min. Typ. Max. Unit VCC 4.5 5.0 5.5 V VSS 0 0 0 V Input High Voltage VIH 2.4 — Input Low Voltage VIL –0.5*2 — VCC + 0.5*1 0.8 V V Notes : *1. The input voltage is VCC + 2.0 V when the pulse width is less than 20 ns (the pulse width is with respect to the point at which VCC is applied). *2. The input voltage is VSS – 2.0 V when the pulse width is less than 20 ns (the pulse width is with respect to the point at which VSS is applied). Capacitance (VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz) Parameter Symbol Typ. Max. Unit Input Capacitance (A0 - A10) CIN1 — 5 pF Input Capacitance (RAS, CAS, WE, OE) CIN2 — 7 pF Output Capacitance (DQ1 - DQ4) CI/O — 7 pF 16M 218 ¡ Semiconductor MSM5117400B DC Characteristics Parameter (VCC = 5 V ±10%, Ta = 0°C to 70°C) Symbol Condition MSM5117400 MSM5117400 MSM5117400 B-50 B-60 B-70 Unit Note Min. Max. Min. Max. Min. Max. Output High Voltage VOH IOH = –5.0 mA 2.4 VCC 2.4 VCC V VOL IOL = 4.2 mA 0 VCC 0.4 2.4 Output Low Voltage 0 0.4 0 0.4 V Input Leakage Current ILI –10 10 –10 10 –10 10 mA –10 10 –10 10 –10 10 mA — 120 — 110 — 100 mA 1, 2 — 2 — 2 — 2 mA 1 — 1 — 1 — 1 — 120 — 110 — 100 mA 1, 2 — 5 — 5 — 5 mA 1 — 120 — 110 — 100 mA 1, 2 — 110 — 100 — 90 mA 1, 3 0 V £ VI £ 6.5 V; All other pins not under test = 0 V Output Leakage Current ILO Average Power Supply Current ICC1 (Operating) Power Supply Current (Standby) ICC2 Current (Standby) (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) tRC = Min. RAS, CAS = VIH RAS, CAS RAS cycling, tRC = Min. RAS = VIH, ICC5 CAS = VIL, DQ = enable Average Power Supply Current RAS, CAS cycling, ICC3 CAS = VIH, (RAS-only Refresh) Power Supply 0 V £ VO £ 5.5 V ≥ VCC –0.2 V Average Power Supply Current DQ disable ICC6 RAS cycling, CAS before RAS RAS = VIL, ICC7 CAS cycling, tPC = Min. Notes : 1. ICC Max. is specified as ICC for output open condition. 2. The address can be changed once or less while RAS = VIL. 3. The address can be changed once or less while CAS = VIH. 16M 219 MSM5117400B ¡ Semiconductor AC Characteristics (1/2) (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 11, 12 Parameter MSM5117400 MSM5117400 MSM5117400 B-50 B-70 B-60 Unit Note Min. Max. Min. Max. Min. Max. 90 131 — — 110 130 — ns 35 — 155 40 — — — 185 45 — — ns ns tPRWC 76 — 85 — 100 — ns tRAC — 50 — 60 — 70 ns 4, 5, 6 Access Time from CAS tCAC Access Time from Column Address Access Time from CAS Precharge tAA tCPA — — 13 25 — — 15 30 — — 20 35 ns ns 4, 5 4, 6 — 30 — 35 — 40 ns 4 Access Time from OE Output Low Impedance Time from CAS tOEA tCLZ — 0 13 — — 0 15 — — 0 20 — ns ns 4 4 CAS to Data Output Buffer Turn-off Delay Time OE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period tOFF tOEZ tT tREF 0 0 3 — 13 13 50 32 0 0 3 — 15 15 50 32 0 0 3 — 20 20 50 32 ns ns ns ms 7 RAS Precharge Time tRP 30 — 40 — 50 — ns RAS Pulse Width tRAS 50 10,000 60 10,000 70 10,000 ns RAS Pulse Width (Fast Page Mode) tRASP 50 100,000 60 100,000 70 100,000 ns RAS Hold Time RAS Hold Time referenced to OE tRSH tROH 13 13 — — 15 15 — — 20 20 — — ns ns CAS Precharge Time (Fast Page Mode) tCP 7 — 10 — 10 — ns CAS Pulse Width tCAS 13 10,000 15 10,000 20 10,000 ns CAS Hold Time CAS to RAS Precharge Time tCSH tCRP 50 5 — 60 5 — ns — 70 5 — — — ns RAS Hold Time from CAS Precharge tRHCP tRCD tRAD 30 17 12 — 37 25 35 20 15 — 45 30 40 20 15 — 50 35 ns ns ns Row Address Set-up Time tASR 0 — 0 — 0 — ns Row Address Hold Time tRAH 7 — 10 — 10 — ns Column Address Set-up Time tASC 0 — 0 — 0 — ns Column Address Hold Time Column Address to RAS Lead Time tCAH tRAL 7 25 — — 15 30 — — 15 35 — — ns ns Read Command Set-up Time tRCS 0 — 0 — 0 — ns Read Command Hold Time tRCH 0 — 0 — 0 — ns 8 Read Command Hold Time referenced to RAS tRRH 0 — 0 — 0 — ns 8 Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS RAS to CAS Delay Time RAS to Column Address Delay Time 16M Symbol 220 tRC tRWC tPC 7 3 5 6 ¡ Semiconductor MSM5117400B AC Characteristics (2/2) (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 11, 12 Parameter Symbol MSM5117400 MSM5117400 MSM5117400 B-50 B-60 B-70 Unit Note Min. Max. Min. Max. Min. Max. Write Command Set-up Time tWCS 0 — 0 — 0 — ns Write Command Hold Time tWCH 7 — 10 — 15 — ns Write Command Pulse Width OE Command Hold Time tWP tOEH 7 13 — — 10 15 — — 10 20 — — ns ns Write Command to RAS Lead Time tRWL tCWL 13 13 — — 15 — ns — 20 20 — 15 — ns tDS 0 7 13 — — — 0 10 15 — — — 0 15 20 — — — 10 10 — — — 40 55 — — 50 65 — — 85 — 100 — ns ns ns ns ns ns 9 Write Command to CAS Lead Time Data-in Set-up Time Data-in Hold Time OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time tCWD tAWD RAS to WE Delay Time tRWD 36 48 73 CAS Precharge WE Delay Time tDH tOED tCPWD 53 — 60 — 70 — ns CAS Active Delay Time from RAS Precharge tRPC 5 — 5 — 5 — ns RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) WE to RAS Precharge Time (CAS before RAS) WE Hold Time from RAS (CAS before RAS) RAS to WE Set-up Time (Test Mode) RAS to WE Hold Time (Test Mode) tCSR tCHR tWRP 10 10 10 10 — — — 10 10 10 10 — — — — 10 10 10 10 — — — ns ns ns ns 10 10 — — 10 10 tWRH tWTS tWTH 10 10 — — — — — — 9 9 9 9 ns ns 16M 221 MSM5117400B Notes: ¡ Semiconductor 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. In a test mode CA0 and CA1 are not used and each DQ pin now accesses 4-bit locations. Since all 4 DQ pins are used, a total of 16 data bits can be written in parallel into the memory array. In a read cycle, if 4 data bits are equal, the DQ pin will indicate a high level. If the 4 data bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. 16M 12. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet. See ADDENDUM F for AC Timing Waveforms 222