OKI MSM5117800D

Semiconductor
This version:Apr.1999
MSM5117800D
2,097,152-Word ´ 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
DESCRIPTION
The MSM5117800D is a 2,097,152-word ´ 8-bit dynamic RAM fabricated in Oki’s silicon-gate CMOS
technology. The MSM5117800D achieves high integration, high-speed operation, and low-power consumption
because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The
MSM5117800D is available in a 28-pin plastic SOJ, 28-pin plastic TSOP.
FEATURES
·
2,097,152-word ´ 8-bit configuration
·
Single 5V power supply, ±10% tolerance
·
Input
: TTL compatible, low input capacitance
·
Output
: TTL compatible, 3-state
·
Refresh
: 2048 cycles/32 ms
·
Fast page mode, read modify write capability
·
CAS before RAS refresh, hidden refresh, RAS-only refresh capability
·
Multi-bit test mode capability
·
Package options:
28-pin 400mil plastic SOJ
(SOJ28-P-400-1.27)
(Product : MSM5117800D-xxJS)
28-pin 400mil plastic TSOP
(TSOPII28-P-400-1.27-K)
(Product : MSM5117800D-xxTS-K)
(TSOPII28-P-400-1.27-L)
(Product : MSM5117800D-xxTS-L)
xx : indicates speed rank.
PRODUCT FAMILY
Family
Access Time (Max.)
Cycle Time
Power Dissipation
tRAC
tAA
tCAC
tOEA
(Min.)
Operating (Max.)
MSM5117800D-50
50ns
25ns
13ns
13ns
90ns
550mW
MSM5117800D-60
60ns
30ns
15ns
15ns
110ns
495mW
MSM5117800D-70
70ns
35ns
20ns
20ns
130ns
440mW
Standby (Max.)
5.5mW
1/14
MSM5117800D
PIN CONFIGRATION (TOP VIEW)
VCC 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
WE 6
RAS 7
NC 8
A10R 9
A0 10
A1 11
A2 12
A3 13
VCC 14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSS
DQ8
DQ7
DQ6
DQ5
CAS
OE
A9
A8
A7
A6
A5
A4
VSS
VCC 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
WE 6
RAS 7
NC 8
A10R 9
A0 10
A1 11
A2 12
A3 13
VCC 14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSS
DQ8
DQ7
DQ6
DQ5
CAS
OE
A9
A8
A7
A6
A5
A4
VSS
VSS
DQ8
DQ7
DQ6
DQ5
CAS
OE
A9
A8
A7
A6
A5
A4
VSS
28-Pin Plastic TSOP
(K Type)
28-Pin Plastic SOJ
Pin Name
Function
A0–A9, A10R
Address Input
RAS
Row Address Strobe
CAS
Column Address Strobe
DQ1–DQ8
Data Input/Data Output
OE
Output Enable
WE
Write Enable
VCC
Power Supply (5V)
VSS
Ground (0V)
NC
No Connection
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VCC
DQ1
DQ2
DQ3
DQ4
WE
RAS
NC
A10R
A0
A1
A2
A3
VCC
28-Pin Plastic TSOP
(L Type)
2/14
MSM5117800D
BLOCK DIAGRAM
Timing
Generator
RAS
WE
OE
I/O
Controller
CAS
8
Output
Buffers
8
DQ1 – DQ8
10
10
Internal
Address
Counter
A0 – A9
10
A10R
Column
Address
Buffers
1
Row
Address
Buffers
Refresh
Control Clock
11
Row
Decoders
Word
Drivers
Column Decoders
Sense Amplifiers
8
8
I/O
Selector
Input
Buffers
8
8
Memory
Cells
VCC
On Chip
VBB Generator
On Chip
IVCC Generator
VSS
3/14
MSM5117800D
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Voltage on Any Pin Relative to VSS
VIN, VOUT
-0.5 to VCC + 0.5
V
Voltage VCC supply Relative to VSS
VCC
0.5 to 7.0
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD*
1
W
Operating Temperature
Topr
0 to 70
°C
Storage Temperature
Tstg
-55 to 150
°C
*: Ta = 25°C
Recommended Operating Conditions
(Ta = 0°C to 70°C)
Parameter
Power Supply Voltage
Input High Voltage
Input Low Voltage
Notes:
Symbol
Min.
Typ.
Max.
Unit
VCC
VSS
VIH
VIL
4.5
5.0
5.5
V
0
0
0
V
2.4
¾
VCC + 0.5*1
V
¾
0.8
V
*2
-0.5
*1. The input voltage is VCC + 2.0V when the pulse width is less than 20ns (the pulse width is with
respect to the point at which VCC is applied).
*2. The input voltage is VSS - 2.0V when the pulse width is less than 20ns (the pulse width respect to
the point at which VSS is applied).
Capacitance
(VCC = 5V ± 10%, Ta = 25°C, f=1MHz)
Parameter
Input Capacitance (A0 – A9, A10R)
Input Capacitance
(RAS, CAS, WE, OE)
Output Capacitance (DQ1 – DQ8)
Symbol
Typ.
Max.
Unit
CIN1
¾
5
pF
CIN2
¾
7
pF
CI/O
¾
7
pF
4/14
MSM5117800D
DC Characteristics
(VCC = 5V ± 10%, Ta = 0°C to 70°C)
Parameter
Symbol
Condition
Max
Min.
Max
Min.
Max
2.4
VCC
2.4
VCC
2.4
VCC
V
0
0.4
0
0.4
0
0.4
V
-10
10
-10
10
-10
10
mA
-10
10
-10
10
-10
10
mA
¾
100
¾
90
¾
80
mA
1,2
RAS, CAS = VIH
¾
2
¾
2
¾
2
RAS, CAS ³
VCC – 0.2V
¾
1
¾
1
¾
1
mA
1
¾
100
¾
90
¾
80
mA
1,2
¾
5
¾
5
¾
5
mA
1
¾
100
¾
90
¾
80
mA
1,2
¾
80
¾
70
¾
60
mA
1,3
VOH
IOH = -5.0mA
Output Low Voltage
VOL
IOL = 4.2mA
0V £ VI £ 6.5V ;
Input Leakage
Current
ILI
Output Leakage
Current
ILO
Average Power
Supply Current
ICC1
(Operating)
ICC2
(Standby)
Average Power
Supply Current
All other pins not
under test = 0V
DQ disable
0V £ VO £ VCC
RAS, CAS cycling,
tRC = Min.
RAS cycling,
ICC3
CAS = VIH,
(RAS-only Refresh)
tRC = Min.
Power Supply
Current
RAS = VIH,
ICC5
(Standby)
CAS = VIL,
DQ = enable
Average Power
Supply Current
(CAS before RAS
Refresh)
Average Power
Supply Current
(Fast Page Mode)
Notes: 1.
Note
Min.
Output High Voltage
Power Supply
Current
MSM5117800 MSM5117800 MSM5117800
D-50
D-60
D-70
Unit
ICC6
RAS = cycling,
CAS before RAS
RAS = VIL,
ICC7
CAS cycling,
tPC = Min.
ICC Max. is specified as ICC for output open condition.
2.
The address can be changed once or less while RAS = VIL.
3.
The address can be changed once or less while CAS = VIH.
5/14
MSM5117800D
AC Characteristic (1/2)
(VCC = 5V ± 10%, Ta = 0°C to 70°C) Note1,2,3,11,12
Parameter
MSM5117800
D-50
Symbol
MSM5117800
D-60
MSM5117800
D-70
Unit
Note
Min.
Max.
Min.
Max.
Min.
Max.
tRC
90
¾
110
¾
130
¾
ns
tRWC
131
¾
155
¾
185
¾
ns
Fast Page Mode Cycle Time
tPC
35
¾
40
¾
45
¾
ns
Fast Page Mode Read Modify
Write Cycle Time
tPRWC
76
¾
85
¾
100
¾
ns
Access Time from RAS
tRAC
¾
50
¾
60
¾
70
ns
4,5,6
Access Time from CAS
tCAC
¾
13
¾
15
¾
20
ns
4,5
Access Time from Column Address
tAA
¾
25
¾
30
¾
35
ns
4,6
Access Time from CAS Precharge
tCPA
¾
30
¾
35
¾
40
ns
4
Access Time from OE
tOEA
¾
13
¾
15
¾
20
ns
4
Output Low Impedance Time from
CAS
tCLZ
0
¾
0
¾
0
¾
ns
4
CAS to Data Output Buffer Turnoff Delay Time
tOFF
0
13
0
15
0
20
ns
7
OE to Data Output Buffer Turn-off
Delay Time
tOEZ
0
13
0
15
0
20
ns
7
Transition Time
tT
3
50
3
50
3
50
ns
3
Refresh Period
tREF
¾
32
¾
32
¾
32
RAS Precharge Time
tRP
30
¾
40
¾
50
¾
m
s
ns
RAS Pulse Width
tRAS
50
10,000
60
10,000
70
10,000
ns
RAS Pulse Width (Fast Page Mode) tRASP
50
100,000
60
100,000
70
100,000
ns
RAS Hold Time
tRSH
13
¾
15
¾
20
¾
ns
RAS Hold Time referenced to OE
tROH
13
¾
15
¾
20
¾
ns
CAS Precharge Time
(Fast Page Mode)
tCP
7
¾
10
¾
10
¾
ns
CAS Pulse Width
tCAS
13
10,000
15
10,000
20
10,000
ns
CAS Hold Time
tCSH
50
¾
60
¾
70
¾
ns
CAS to RAS Precharge Time
tCRP
5
¾
5
¾
5
¾
ns
RAS Hold Time from CAS Precharge tRHCP
30
¾
35
¾
40
¾
ns
RAS to CAS Delay Time
tRCD
17
37
20
45
20
50
ns
5
RAS to Column Address Delay Time
tRAD
12
25
15
30
15
35
ns
6
Row Address Set-up Time
tASR
0
¾
0
¾
0
¾
ns
Row Address Hold Time
tRAH
7
¾
10
¾
10
¾
ns
Column Address Set-up Time
tASC
0
¾
0
¾
0
¾
ns
Random Read or Write Cycle Time
Read Modify Write Cycle Time
6/14
MSM5117800D
AC Characteristic (2/2)
(VCC = 5V ± 10%, Ta = 0°C to 70°C) Note1,2,3,11,12
Parameter
Symbol
MSM5117800
D-50
MSM5117800
D-60
MSM5117800
D-70
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Note
Column Address Hold Time
tCAH
7
¾
15
¾
15
¾
ns
Column Address to RAS Lead Time
tRAL
25
¾
30
¾
35
¾
ns
Read Command Set-up Time
tRCS
0
¾
0
¾
0
¾
ns
Read Command Hold Time
tRCH
0
¾
0
¾
0
¾
ns
8
Read Command Hold Time
referenced to RAS
tRRH
0
¾
0
¾
0
¾
ns
8
Write Command Set-up Time
tWCS
0
¾
0
¾
0
¾
ns
9
Write Command Hold Time
tWCH
7
¾
10
¾
15
¾
ns
Write Command Pulse Width
tWP
7
¾
10
¾
10
¾
ns
OE Command Hold Time
tOEH
13
¾
15
¾
20
¾
ns
Write Command to RAS Lead Time
tRWL
13
¾
15
¾
20
¾
ns
Write Command to CAS Lead Time
tCWL
13
¾
15
¾
20
¾
ns
Data-in Set-up Time
tDS
0
¾
0
¾
0
¾
ns
10
Data-in Hold Time
tDH
7
¾
15
¾
15
¾
ns
10
OE to Data-in Delay Time
tOED
13
¾
15
¾
20
¾
ns
CAS to WE Delay Time
tCWD
36
¾
40
¾
50
¾
ns
9
Column Address to WE Delay Time
tAWD
48
¾
55
¾
65
¾
ns
9
RAS to WE Delay Time
tRWD
73
¾
85
¾
100
¾
ns
9
CAS Precharge WE Delay Time
tCPWD
53
¾
60
¾
70
¾
ns
9
CAS Active Delay Time from RAS
Precharge
tRPC
10
¾
10
¾
10
¾
ns
RAS to CAS Set-up Time
(CAS before RAS)
tCSR
10
¾
10
¾
5
¾
ns
RAS to CAS Hold Time
(CAS before RAS)
tCHR
10
¾
10
¾
10
¾
ns
WE to RAS Precharge Time
(CAS before RAS)
tWRP
10
¾
10
¾
10
¾
ns
WE Hold Time from RAS
(CAS before RAS)
tWRH
10
¾
10
¾
10
¾
ns
RAS to WE Set-up Time (Test Mode)
tWTS
10
¾
10
¾
10
¾
ns
RAS to WE Hold Time (Test Mode)
tWTH
10
¾
10
¾
10
¾
ns
7/14
MSM5117800D
Notes:
1.
A start-up delay of 200ms is required after power-up, followed by a minimum of eight initialization
cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved.
2.
The AC characteristics assume tT = 5ns.
3.
VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times
(tT) are measured between VIH and VIL.
4.
This parameter is measured with a load circuit equivalent to 2 TTL load and 100pF.
5.
Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.
tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.)
limit, then the access time is controlled by tCAC.
6.
Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.
tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.)
limit, then the access time is controlled by tAA.
7.
tOFF (Max.) and tOEZ (Max.) define the time at which the output achieved the open circuit
condition and are not referenced to output voltage levels.
8.
tRCH or tRRH must be satisfied for a read cycle.
9.
tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in
the data sheet as electrical characteristics only. If tWCS ³ tWCS (Min.), then the cycle is an early
write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle.
If tCWD ³ tCWD (Min.), tRWD ³ tRWD(Min.), tAWD ³ tAWD (Min.) and tCPWD ³ tCPWD (Min.), then
the cycle is a read modify write cycle and data out will contain data read from the selected cell; if
neither of the above sets of conditions is satisfied, then the condition of the data out (at access time)
is indeterminate.
10. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE
leading edge in an OE control write cycle, or a read modify write cycle.
11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is
latched and remains in effect until the exit cycle is generated. The test mode specified in this data
sheets is a 2-bit parallel test function, CA0 and CA1 are not used. In a read cycle, if all internal bits
are equal, the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will
indicate a low level. The test mode is cleared and the memory device returned to its normal
operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle.
12. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified
value. These parameters should be specified in test mode cycle by adding the above value to the
specified value in this data sheet.
8/14
MSM5117800D
Timing Chart
·
Read Cycle
RAS
tRC
tRAS
VIH
tRP
VIL
tCSH
tCRP
CAS
tRAD
VIL
WE
OE
VIH
VIL
tCRP
tRSH
tCAS
VIH
tRAL
tASR
Address
tRCD
tRAH
tASC
Row
tCAH
Column
tRCS
tRRH
VIH
tAA
VIL
tRCH
tROH
tOEA
VIH
VIL
tCAC
tRAC
DQ
tOFF
tOEZ
tCLZ
VOH
Valid Data-out
Open
VOL
“H” or “L”
·
Write Cycle (Early Write)
RAS
tRC
tRAS
VIH
tRP
VIL
tCSH
tCRP
CAS
tRCD
VIH
tRAD
VIL
tRAL
tASR
Address
WE
OE
DQ
VIH
VIL
VIH
tCRP
tRSH
tCAS
tRAH
tASC
Row
tCAH
Column
tCWL
tWCS
tWP
tWCH
VIL
tRWL
VIH
VIL
VIH
VIL
tDS
Valid Data-in
tDH
Open
“H” or “L”
9/14
·
MSM5117800D
Read Modify Write Cycle
tRWC
RAS
tRAS
VIH
tRP
VIL
tCSH
tCRP
CAS
tRSH
tCAS
VIH
VIH
VIL
tCRP
tRAD
VIL
tASR
Address
tRCD
tRAH
Row
tASC
tCWL
tRWL
tCAH
Column
tRCS
tCWD
tWP
tRWD
WE
OE
VIH
VIL
tAWD
tAA
tOEH
tOEA
VIH
tOED
VIL
tCAC
tRAC
DQ
VI/OH
VI/OL
tOEZ
tCLZ
Valid
Data-out
tDS
tDH
Valid
Data-in
“H” or “L”
10/14
MSM5117800D
·
Fast Page Mode Cycle
tRASP
RAS
VIH
VIL
tRCD
tCRP
CAS
tCP
VIH
VIL
VIH
VIL
tRAD
tCSH
tRAH tASC
tCP
Row
tASC
Column
tRCH
tASC
tCAH
Column
tRCS
tRCH
tRCS
tRCH
VIH
VIL
tAA
tAA
VIH
VIL
tRAC
tCPA
tOFF
tOEZ
tCLZ
VOH
tAA
tOEA
tCAC
DQ
tCRP
tRAL
tCAH
Column
tOEA
OE
tRSH
tCAS
tCAS
tCAH
tRCS
WE
tRHCP
tCAS
tASR
Address
tRP
tPC
tCPA
tOFF
tCAC
tOEZ
tCLZ
Valid
Data-out
VOL
tRRH
tOEA
tOFF
tCAC
tOEZ
tCLZ
Valid
Data-out
Valid
Data-out
“H” or “L”
·
Fast Page Mode Write Cycle (Early Write)
tRP
tRASP
RAS
CAS
tPC
VIH
VIL
tCRP
tCP
VIL
tCAS
tRAH tASC
Row
tCSH
tCAH
tASC
Column
tWCS
VIH
tWCH
tWP
tCAH
tASC
Column
tRWL
tCWL
tCWL
tWCS
tRAL
tCAH
tWCH
tWP
tWCS
tWP
tWCH
VIL
tDS
DQ
tCRP
tCAS
Column
tCWL
WE
tRSH
tRAD
VIL
VIH
tCP
tCAS
VIH
tASR
Address
tRCD
tRHPC
VIH
VIL
tDH
Valid *
Data-in
tDS
tDH
Valid *
Data-in
tDS
tDH
Valid *
Data-in
Note: OE = “H” or “L”
“H” or “L”
11/14
MSM5117800D
·
Fast Page Mode Read Modify Write Cycle
tRASP
RAS
CAS
tCSH
VIH
VIL
tRCD
VIL
tCAH
tCWL
tASC
Row
tASC
tRAL
tCWL
Column
tCWD
tRCS
tCPWD
tCWD
tAWD
tAWD
tRCS
tPWD
tCWD
tCPWD
tCWL
tRWL
VIH
tAWD
VIL
tWP
tCPA
tDH
VIH
tWP
tDH
tCAC
VI/OH
tOEZ
Out
VI/OL
tCLZ
tCPA
tAA
tOEA
tOED
VIL
In
tDH
tDS
tOEA
tOED
tOEZ
tCAC
tWP
tROH
tDS
tAA
tDS
tOEA
·
tCRP
tCAH
Column
tAA
DQ
tCAS
tASC
C olum n
tRAC
OE
tCP
tCAS
tRAD
VIL
VIH
tRP
tRSH
tCAH
tRCS
WE
tCP
tCAS
VIH
tRAH
tASR
Address
tPRWC
Ou
tOED
tOEZ
tCAC
In
Ou
tCLZ
tCLZ
In
“H” or “L”
RAS-only Refresh Cycle
tRC
RAS
tRAS
VIH
tRP
VIL
tCRP
CAS
Address
DQ
tRPC
VIH
VIL
VIH
VIL
VOH
VOL
tASR
tRAH
Row
tOFF
Open
Note: WE, OE = “H” or
“H” or “L”
12/14
MSM5117800D
·
CAS before RAS Refresh Cycle
tRP
RAS
CAS
tRC
tRAS
VIH
VIL
tRPC
tCP
tRP
tCSR
tRPC
tCHR
VIH
VIL
tOFF
DQ
VOH
Open
VOL
Note: WE, OE, Address = “H” or
·
“H” or “L”
Hidden Refresh Read Cycle
tRC
RAS
CAS
VIH
VIL
tCRP
tRCD
tRSH
tCHR
tRAD
VIL
VIH
VIL
tRAH
tASC
tCAH
Column
Row
tRCS
WE
tRP
tRP
VIH
tASR
Address
tRC
tRAS
tRAS
tCAC
tRRH
VIH
tRAL
VIL
tAA
tROH
OE
DQ
VIH
VIL
VOH
VOL
tOFF
tOEA
tRAC
tOEZ
tCLZ
Open
Valid Data-out
“H” or “L”
13/14
MSM5117800D
Hidden Refresh Write Cycle
tRC
RAS
CAS
VIH
VIL
tCRP
tRAS
tRCD
tRSH
VIH
VIL
tRAH
tRAL
tASC
Row
tCAH
Column
tWCS
WE
OE
DQ
tRP
tRAD
VIL
VIH
tRP
tCHR
tASR
Address
tRC
tRAS
tWCH
VIH
VIL
tWP
VIH
VIL
VIH
VIL
tDS
tDH
Valid Data-in
“H” or “L”
14/14