E2L0031-17-Y1 ¡ Semiconductor MSM514223B ¡ Semiconductor This version: Jan. 1998 MSM514223B Previous version: Dec. 1996 262,263-Word ¥ 4-Bit Field Memory DESCRIRTION The OKI MSM514223B is a high performance 1-Mbit, 256K ¥ 4-bit, Field Memory. It is designed for high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital movies and Multi-media systems. It is a FRAM for wide or low end use as general commodity TVs and VTRs, exclusively. The MSM514223B is not designed for the other use or high end use in medical systems, professional graphics systems which require long term picture, and data storage systems and others. The 1-Mbit capacity fits one field of a conventional NTSC TV screen and cascaded two MSM514223Bs make one frame of the screen: more than two MSM514223Bs can be cascaded directly without any delay devices among the MSM514223Bs. (Cascading of MSM514223B provides larger storage depth or a longer delay). Each of the 4-bit planes has separate serial write and read ports that employ independent control clocks to support asynchronous read and write operations. Different clock rates are also supported that allow alternate data rates between write and read data streams. The MSM514223B provides high speed FIFO, First-In First-Out, operation without external refreshing: it refreshes its DRAM storage cells automatically, so that it appears fully static to the users. Moreover, fully static type memory cells and decoders for serial access enable refresh free serial access operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the power is on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration logic. The MSM514223B's function is simple, and similar to a digital delay device whose delay-bitlength is easily set by reset timing. The delay length, number of read delay clocks between write and read, is determined by externally controlled write and read reset timings. Additional SRAM serial registers, or line buffers for the initial access of 256 ¥ 4-bit enable high speed first-bit-access with no clock delay just after the write or read reset timings. The MSM514223B is similar in operation and functionality to OKI 1-Mbit Field Memory MSM514221B besides direct cascade capability. (As for MSM514221B operation compatible 2Mbit Field Memory, OKI has MSM518221 as a sister device of MSM518222). Additionally, the MSM514223B has write mask function or input enable function (IE), and readdata skipping function or output enable function (OE). The differences between write enable (WE) and input enable (IE), and between read enable (RE) and output enable (OE) are that WE and RE can stop serial write/read address increments but IE and OE can not stop the increment when write/read clocking is continuously applied to MSM514223B. The input enable (IE) function allows the user to write into selected locations of the memory only, leaving the rest of the memory contents unchanged. This facilitate data processing to display a "picture in picture" on a TV screen. 1/14 ¡ Semiconductor MSM514223B FEATURES • Single power supply: 5 V ±10% • 512 Rows ¥ 512 Column ¥ 4 bits • Fast FIFO (First-in First-out) operation • High speed asynchronous serial access Read/Write cycle time 30 ns/40 ns/60 ns Access time 25 ns/30 ns/50 ns • Direct cascading capability • Write mask function (Input enable control) • Data skipping function (Output enable control) • Self refresh (No refresh control is required) • Package: 18-pin 300 mil plastic DIP (DIP18-P-300-2.54-W1) (Product : MSM514223B-xxRS) xx indicates speed rank. PRODUCT FAMILY Access Time (Max.) Cycle Time (Min.) MSM514223B-30RS Family 25 ns 30 ns MSM514223B-40RS 30 ns 40 ns MSM514223B-60RS 50 ns 60 ns Package 300 mil 18-pin DIP 2/14 ¡ Semiconductor MSM514223B PIN CONFIGURATION (TOP VIEW) IE 1 18 VCC WE 2 17 OE RSTW 3 16 RE SWCK 4 15 RSTR DIN0 5 14 SRCK DIN1 6 13 DOUT0 DIN2 7 12 DOUT1 DIN3 8 11 DOUT2 VSS 9 10 DOUT3 18-Pin Plastic DIP Pin Name Function SWCK Serial Write Clock SRCK Serial Read Clock WE Write Enable RE Read Enable IE Input Enable OE Output Enable RSTW Write Reset Clock RSTR Read Reset Clock DIN0 - 3 DOUT0 - 3 Data Input Data Output VCC Power Supply (5 V) VSS Ground (0 V) 3/14 ¡ Semiconductor MSM514223B BLOCK DIAGRAM DOUT (¥ 4) OE RE Data-Out Buffer (¥ 4) Serial Read RSTR SRCK Controller 512 Word Serial Read Register (¥ 4) Read Line Buffer Low-Half (¥ 4) Read Line Buffer High-Half (¥ 4) 256 (¥ 4) 120 Word Sub-Register (¥ 4) 256 (¥ 4) 256K (¥ 4) Memory Array 120 Word Sub-Register (¥ 4) X Decoder 256 (¥ 4) 256 (¥ 4) Read/Write and Refresh Controller Clock Oscillator Write Line Buffer Write Line Buffer Low-Half (¥ 4) High-Half (¥ 4) 512 Word Serial Write Register (¥ 4) Data-In Buffer (¥ 4) DIN (¥ 4) VBB Generator Serial Write IE WE Controller RSTW SWCK 4/14 ¡ Semiconductor MSM514223B OPERATION Write Operation The write operation is controlled by three clocks, SWCK, RSTW, and WE. Write operation is accomplished by cycling SWCK, and holding WE high after the write address pointer reset operation or RSTW. Each write operation, which begins after RSTW, must contain at least 130 active write cycles, i.e. SWCK cycles while WE is high. To transfer the last data to the DRAM array, which at that time is stored in the serial data registers attached to the DRAM array, an RSTW operation is required after the last SWCK cycle. Note that every write timing of MSM514223B is delayed by one clock compared with read timings for easy cascading without any interface delay devices. Write Reset : RSTW The first positive transition of SWCK after RSTW becomes high resets the write address counters to zero. RSTW setup and hold times are referenced to the rising edge of SWCK. Because the write reset function is solely controlled by the SWCK rising edge after the high level of RSTW, the states of WE and IE are ignored in the write reset cycle. Before RSTW may be brought high again for a further reset operation, it must be low for at least two SWCK cycles. Data Inputs : DIN0 - 3 Write Clock : SWCK The SWCK latches the input data on chip when WE is high, and also increments the internal write address pointer. Data-in setup time tDS, and hold time tDH are referenced to the rising edge of SWCK. Write Enable : WE WE is used for data write enable/disable control. WE high level enables the input, and WE low level disables the input and holds the internal write address pointer. There are no WE disable time (low) and WE enable time (high) restrictions, because the MSM514223B is in fully static operation as long as the power is on. Note that WE setup and hold times are referenced to the rising edge of SWCK. Input Enable : IE IE is used to enable/disable writing into memory. IE high level enables writing. The internal write address pointer is always incremented by cycling SWCK regardless of the IE level. Note that IE setup and hold times are referenced to the rising edge of SWCK. 5/14 ¡ Semiconductor MSM514223B Read Operation The read operation is controlled by three clocks, SRCK, RSTR, and RE. Read operation is accomplished by cycling SRCK, and holding RE high after the read address pointer reset operation or RSTR. Each read operation, which begins after RSTR, must contain at least 130 active read cycles, i.e. SRCK cycles while RE is high. Read Reset : RSTR The first positive transition of SRCK after RSTR becomes high resets the read address counters to zero. RSTR setup and hold times are referenced to the rising edge of SRCK. Because the read reset function is solely controlled by the SRCK rising edge after the high level of RSTR, the states of RE and OE are ignored in the read reset cycle. Before RSTR may be brought high again for a further reset operation, it must be low for at least two SRCK cycles. Data Out : DOUT0 - 3 Read Clock : SRCK Data is shifted out of the data registers. It is triggered by the rising edge of SRCK when RE is high during a read operation. The SRCK input increments the internal read address pointer when RE is high. The three-state output buffer provides direct TTL compatibility ( no pullup resistor required). Data out is the same polarity as data in. The output becomes valid after the access time interval tAC that begins with the rising edge of SRCK. There are no output valid time restriction on MSM514223B. Read Enable : RE The function of RE is to gate of the SRCK clock for incrementing the read pointer. When RE is high before the rising edge of SRCK, the read pointer is incremented. When RE is low, the read pointer is not incremented. RE setup times (tRENS and tRDSS) and RE hold times (tRENH and tRDSH) are referenced to the rising edge of the SRCK clock. Output Enable : OE OE is used to enable/disable the outputs. OE high level enables the outputs. The internal read address pointer is always incremented by cycling SRCK regardless of the OE level. Note that OE setup and hold times are referenced to the rising edge of SRCK. 6/14 ¡ Semiconductor MSM514223B Power-up and Initialization On power-up, the device is designed to begin proper operation after at least 100 ms after VCC has stabilized to a value within the range of recommended operating conditions. After this 100 ms stabilization interval, the following initialization sequence must be performed. Because the read and write address counters are not valid after power-up, a minimum of 130 dummy write operations (SWCK cycles) and read operations (SRCK cycles) must be performed, followed by an RSTW operation and an RSTR operation, to properly initialize the write and the read address pointer. Dummy write cycles/RSTW and dummy read cycles/RSTR may occur simultaneously. If these dummy read and write operations start while VCC and/or the substrate voltage has not stabilized, it is necessary to perform an RSTR operation plus a minimum of 130 SRCK cycles plus another RSTR operation, and an RSTW operation plus a minimum of 130 SRCK cycles plus another RSTW operation to properly initialize read and write address pointers. Old/New Data Access There must be a minimum delay of 600 SWCK cycles between writing into memory and reading out from memory. If reading from the first field starts with an RSTR operation, before the start of writing the second field (before the next RSTW operation), then the data just written will be read out. The start of reading out the first field of data may be delayed past the beginning of writing in the second field of data for as many as 119 SWCK cycles. If the RSTR operation for the first field readout occurs less than 119 SWCK cycles after the RSTW operation for the second field write-in, then the internal buffering of the device assures that the first field will still be read out. The first field of data that is read out while the second field of data is written is called “old data”. In order to read out “new data”, i.e., the second field written in, the delay between an RSTW operation and an RSTR operation must be at least 600 SRCK cycles. If the delay between RSTW and RSTR operations is more than 120 but less than 600 cycles, then the data read out will be undetermined. It may be “old data” or “new” data, or a combination of old and new data. Such a timing should be avoided. Cascade Operation The MSM514223B is designed to allow easy cascading of multiple memory devices. This provides higher storage depth, or a longer delay than can be achieved with only one memory device. 7/14 ¡ Semiconductor MSM514223B ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Condition Rating Unit Input Output Voltage VT at Ta = 25°C, VSS –1.0 to 7.0 V Output Current IOS Ta = 25°C 50 mA Power Dissipation PD Ta = 25°C 1 W Operating Temperature Topr — 0 to 70 °C Storage Temperature Tstg — –55 to 150 °C Recommended Operating Conditions Parameter Symbol Min. Typ. Max. Unit Power Supply Voltage VCC 4.5 5.0 5.5 V Power Supply Voltage VSS 0 0 0 V Input High Voltage VIH 2.4 VCC VCC + 1 V Input Low Voltage VIL –1.0 0 0.8 V DC Characteristics Parameter Symbol Condition Min. Max. Unit ILI 0 < VI < VCC + 1, Other Pins Tested at V = 0 V –10 10 mA Output Leakage Current ILO 0 < VO < VCC –10 10 mA Output "H" Level Voltage VOH IOH = –5 mA 2.4 — V Output "L" Level Voltage VOL IOL = 4.2 mA V Input Leakage Current Operating Current Standby Current ICC1 — 0.4 -30 — 50 Minimum Cycle Time, Output Open -40 — 45 -60 — 35 — 10 ICC2 Input Pin = VIH / VIL Capacitance mA mA (Ta = 25°C, f = 1 MHz) Parameter Symbol Max. Unit Input Capacitance (DIN, SWCK, SRCK, RSTW, RSTR, WE, RE, IE, OE) CI 7 pF Output Capacitance (DOUT) CO 7 pF 8/14 ¡ Semiconductor MSM514223B AC Characteristics Parameter (VCC = 5 V ±10%, Ta = 0°C to 70°C) Symbol MSM514223B-30 MSM514223B-40 MSM514223B-60 Min. Max. Min. Max. Min. Max. Unit tAC — 25 — 30 — 50 ns DOUT Hold Time from SRCK tDDCK 6 — 6 — 6 — ns DOUT Enable Time from SRCK tDECK 6 25 6 25 6 25 ns SWCK "H" Pulse Width tWSWH 12 — 17 — 17 — ns SWCK "L" Pulse Width tWSWL 12 — 17 — 17 — ns Input Data Setup Time tDS 5 — 5 — 5 — ns Input Data Hold Time tDH 6 — 6 — 6 — ns WE Enable Setup Time tWENS 0 — 0 — 0 — ns WE Enable Hold Time tWENH 5 — 5 — 5 — ns WE Disable Setup Time tWDSS 0 — 0 — 0 — ns WE Disable Hold Time tWDSH 5 — 5 — 5 — ns IE Enable Setup Time tIENS 0 — 0 — 0 — ns IE Enable Hold Time tIENH 5 — 5 — 5 — ns IE Disable Setup Time tIDSS 0 — 0 — 0 — ns IE Disable Hold Time tIDSH 5 — 5 — 5 — ns WE "H" Pulse Width tWWEH 5 — 10 — 10 — ns WE "L" Pulse Width tWWEL 5 — 10 — 10 — ns IE "H" Pulse Width tWIEH 5 — 10 — 10 — ns IE "L" Pulse Width tWIEL 5 — 10 — 10 — ns RSTW Setup Time tRSTWS 0 — 0 — 0 — ns RSTW Hold Time tRSTWH 10 — 10 — 10 — ns SRCK "H" Pulse Width tWSRH 12 — 17 — 17 — ns SRCK "L" Pulse Width tWSRL 12 — 17 — 17 — ns RE Enable Setup Time tRENS 0 — 0 — 0 — ns RE Enable Hold Time tRENH 5 — 5 — 5 — ns RE Disable Setup Time tRDSS 0 — 0 — 0 — ns RE Disable Hold Time tRDSH 5 — 5 — 5 — ns OE Enable Setup Time tOENS 0 — 0 — 0 — ns OE Enable Hold Time tOENH 5 — 5 — 5 — ns OE Disable Setup Time tODSS 0 — 0 — 0 — ns OE Disable Hold Time tODSH 5 — 5 — 5 — ns RE "H" Pulse Width tWREH 5 — 10 — 10 — ns RE "L" Pulse Width tWREL 5 — 10 — 10 — ns OE "H" Pulse Width tWOEH 5 — 10 — 10 — ns OE "L" Pulse Width tWOEL 5 — 10 — 10 — ns Access Time from SRCK RSTR Setup Time tRSTRS 0 — 0 — 0 — ns RSTR Hold Time tRSTRH 10 — 10 — 10 — ns SWCK Cycle Time tSWC 30 — 40 — 60 — ns SRCK Cycle Time tSRC 30 — 40 — 60 — ns tT 3 30 3 30 3 30 ns Transition Time (Rise and Fall) 9/14 ¡ Semiconductor MSM514223B Notes: 1. Input signal reference levels for the parameter measurement are VIH = 2.4 V and VIL = 0.8 V. The transition time tT is defined to be a transition time that signal transfers between VIH = 2.4 V and VIL = 0.8 V. 2. AC measurements assume tT = 3 ns. 3. Read address must have more than a 600 address delay than write address in every cycle when asynchronous read/write is performed. 4. Read must have more than a 600 address delay than write in order to read the data written in a current series of write cycles which has been started at last write reset cycle: this is called "new data read". When read has less than a 119 address delay than write, the read data are the data written in a previous series of write cycles which had been written before at last write reset cycle: this is called "old data read". 5. When the read address delay is between more than 120 and less than 599, read data will be undetermined. However, normal write is achieved in this address condition. 6. Outputs are measured with a load equivalent to 2 TTL loads and 30 pF. Output reference levels are VOH = 2.4 V and VOL = 0.8 V. 10/14 ¡ Semiconductor MSM514223B TIMING WAVEFORM Write Cycle Timing (Write Reset) n Cycle 0 Cycle SWCK 2 Cycle 1 Cycle – VIH – VIL ,, , tRSTWH tRSTWS tT tWSWH tWSWL tSWC – VIH – VIL RSTW tDS DIN tDH n–1 n 0 1 2 WE – VIH – VIL – VIH – VIL IE – VIH – VIL Write Cycle Timing (Write Enable) n Cycle Disable Cycle Disable Cycle n + 1 Cycle – VIH – VIL SWCK tWDSH tWENH tWDSS tWENS – VIH – VIL WE tWWEH tWWEL DIN n–1 n n+1 – VIH – VIL IE – VIH – VIL RSTW – VIH – VIL 11/14 ,, , ¡ Semiconductor MSM514223B Write Cycle Timing (Input Enable) n Cycle n + 1 Cycle n + 2 Cycle n + 3 Cycle – VIH – VIL SWCK tIDSH tIENH tIDSS tIENS – VIH – VIL IE tWIEH tWIEL n–1 DIN n n+3 – VIH – VIL WE – VIH – VIL RSTW – VIH – VIL Read Cycle Timing (Read Reset) n Cycle SRCK tT RSTR 0 Cycle RE OE n–1 – VIH – VIL tWSRH tRSTRH tRSTRS tWSRL tSRC tAC DOUT 2 Cycle 1 Cycle – VIH – VIL tDDCK n 0 1 2 – VOH – VOL – VIH – VIL – VIH – VIL 12/14 , , ,, ¡ Semiconductor MSM514223B Read Cycle Timing (Read Enable) n Cycle Disable Cycle Disable Cycle n + 1 Cycle – VIH – VIL SRCK tRDSH tRENH tRDSS tRENS – VIH – VIL RE tWREL DOUT tWREH n–1 n+1 n – VOH – VOL OE – VIH – VIL RSTR – VIH – VIL Read Cycle Timing (Output Enable) n Cycle n + 1 Cycle n + 2 Cycle n + 3 Cycle – VIH – VIL SRCK tODSH tOENH tODSS tOENS – VIH – VIL OE tWOEN DOUT n–1 n tWOEH tDECK Hi-Z n+3 – VOH – VOL RE – VIH – VIL RSTR – VIH – VIL 13/14 ¡ Semiconductor MSM514223B PACKAGE DIMENSIONS (Unit : mm) DIP18-P-300-2.54-W1 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.35 TYP. 14/14