E2G0027-17-41 ¡ Semiconductor MSM514265C/CSL ¡ Semiconductor This MSM514265C/CSL version: Jan. 1998 Previous version: May 1997 262,144-Word ¥ 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO DESCRIPTION The MSM514265C/CSL is a 262,144-word ¥ 16-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM514265C/CSL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/ single-layer metal CMOS process. The MSM514265C/CSL is available in a 40-pin plastic SOJ or 44/ 40-pin plastic TSOP. The MSM514265CSL (the self-refresh version) is specially designed for lowerpower applications. FEATURES • 262,144-word ¥ 16-bit configuration • Single 5 V power supply, ±10% tolerance • Input : TTL compatible, low input capacitance • Output : TTL compatible, 3-state • Refresh : 512 cycles/8 ms, 512 cycles/128 ms (SL version) • Fast page mode with EDO, read modify write capability • CAS before RAS refresh, hidden refresh, RAS-only refresh capability • CAS before RAS self-refresh capability (SL version) • Package options: 40-pin 400 mil plastic SOJ (SOJ40-P-400-1.27) (Product : MSM514265C/CSL-xxJS) 44/40-pin 400 mil plastic TSOP (TSOPII44/40-P-400-0.80-K) (Product : MSM514265C/CSL-xxTS-K) xx indicates speed rank. PRODUCT FAMILY Family Access Time (Max.) tRAC tAA tCAC tOEA Power Dissipation Cycle Time (Min.) Operating (Max.) Standby (Max.) MSM514265C/CSL-50 50 ns 25 ns 15 ns 15 ns 90 ns 935 mW MSM514265C/CSL-60 60 ns 30 ns 15 ns 15 ns 110 ns 825 mW MSM514265C/CSL-70 70 ns 35 ns 20 ns 20 ns 130 ns 770 mW 5.5 mW/ 1.1 mW (SL version) 1/17 ¡ Semiconductor MSM514265C/CSL PIN CONFIGURATION (TOP VIEW) VCC 1 40 VSS VCC DQ1 DQ2 DQ3 DQ4 VCC DQ5 DQ6 DQ7 DQ8 1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 39 38 37 36 35 VSS DQ16 DQ15 DQ14 DQ13 VSS DQ12 DQ11 DQ10 DQ9 A2 18 NC NC 30 NC WE 29 LCAS RAS 28 UCAS NC 27 OE A0 26 A8 A1 A2 25 A7 A3 24 A6 VCC 23 A5 13 14 15 16 17 18 19 20 21 22 32 31 30 29 28 27 26 25 24 23 NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS A3 19 22 A4 VCC 20 21 VSS DQ1 2 39 DQ16 DQ2 3 38 DQ15 DQ3 4 37 DQ14 DQ4 5 36 DQ13 VCC 6 35 VSS DQ5 7 34 DQ12 DQ6 8 33 DQ11 DQ7 9 32 DQ10 DQ8 10 31 DQ9 NC 11 NC 12 WE 13 RAS 14 NC 15 A0 16 A1 17 44/40-Pin Plastic TSOP (K Type) 40-Pin Plastic SOJ Pin Name A0 - A8 RAS Function Address Input Row Address Strobe LCAS Lower Byte Column Address Strobe UCAS Upper Byte Column Address Strobe DQ1 - DQ16 Data Input / Data Output OE Output Enable WE Write Enable VCC Power Supply (5 V) VSS Ground (0 V) NC No Connection Note: The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 2/17 ¡ Semiconductor MSM514265C/CSL BLOCK DIAGRAM RAS WE Timing Generator OE I/O Controller LCAS UCAS 8 I/O Controller Column Address Buffers 9 9 Internal Address Counter A0 - A8 Refresh Control Clock Row Address 9 Buffers 9 Row Decoders Output Buffers 8 DQ1 - DQ8 Column Decoders Sense Amplifiers 16 I/O Selector 8 Input Buffers 8 8 Input Buffers 8 16 Memory Cells Word Drivers DQ9 - DQ16 8 Output Buffers 8 VCC On Chip VBB Generator VSS FUNCTION TABLE Input Pin RAS LCAS DQ Pin UCAS WE OE DQ1 - DQ8 DQ9 - DQ16 Function Mode H * * Standby H * * High-Z H * * High-Z L High-Z High-Z Refresh L L H H L High-Z Lower Byte Read L H L H L DOUT High-Z DOUT Upper Byte Read L L L H L DOUT DOUT Word Read L L H L H DIN Don't Care Lower Byte Write L H L L H Don't Care DIN Upper Byte Write L L L L H DIN DIN Word Write L L L H H High-Z High-Z — *: "H" or "L" 3/17 ¡ Semiconductor MSM514265C/CSL ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Rating Unit Voltage on Any Pin Relative to VSS VT –1.0 to 7.0 V Short Circuit Output Current IOS 50 mA Power Dissipation PD* 1 W Operating Temperature Topr 0 to 70 °C Storage Temperature Tstg –55 to 150 °C *: Ta = 25°C Recommended Operating Conditions Parameter Power Supply Voltage (Ta = 0°C to 70°C) Symbol Min. Typ. Max. Unit VCC 4.5 5.0 5.5 V VSS 0 0 0 V Input High Voltage VIH 2.4 — 6.5 V Input Low Voltage VIL –1.0 — 0.8 V Capacitance (VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz) Symbol Typ. Max. Unit Input Capacitance (A0 - A8) CIN1 — 7 pF Input Capacitance (RAS, LCAS, UCAS, WE, OE) CIN2 — 7 pF Output Capacitance (DQ1 - DQ16) CI/O — 10 pF Parameter 4/17 ¡ Semiconductor MSM514265C/CSL DC Characteristics (VCC = 5 V ±10%, Ta = 0°C to 70°C) Parameter Symbol Condition MSM514265 MSM514265 MSM514265 C/CSL-50 C/CSL-60 C/CSL-70 Unit Note Min. Max. Min. Max. Min. Max. Output High Voltage VOH IOH = –2.0 mA 2.4 VCC 2.4 VCC 2.4 VCC V Output Low Voltage VOL IOL = 2.0 mA 0 0.4 0 0.4 0 0.4 V –10 10 –10 10 –10 10 mA –10 10 –10 10 –10 10 mA — 170 — 150 — 140 mA 1, 2 — 2 — 2 — 2 — 1 — 1 — 1 — 200 — 200 — — 170 — 150 — 5 — — 170 — 0 V £ VI £ 6.5 V; Input Leakage Current ILI All other pins not under test = 0 V Output Leakage Current ILO Average Power Supply Current ICC1 (Operating) DQ disable 0 V £ VO £ 5.5 V RAS, CAS cycling, tRC = Min. RAS, CAS = VIH Power Supply Current (Standby) ICC2 RAS, CAS ≥ VCC –0.2 V mA 1 200 mA 1, 5 — 140 mA 1, 2 5 — 5 — 150 — 140 mA 1, 2 170 — 150 — 140 mA 1, 3 — 300 — 300 — 300 mA — 200 — 200 — 200 mA RAS cycling, Average Power ICC3 CAS = VIH, Supply Current (RAS-only Refresh) tRC = Min. RAS = VIH, Power Supply Current (Standby) ICC5 CAS = VIL, 1 DQ = enable Average Power ICC6 Supply Current mA (CAS before RAS Refresh) RAS cycling, CAS before RAS RAS = VIL, Average Power ICC7 CAS cycling, Supply Current (Fast Page Mode) tHPC = Min. Average Power tRC = 125 ms, ICC10 CAS before RAS, Supply Current tRAS £ 1 ms (Battery Backup) 1, 4, 5 Average Power Supply Current (CAS before RAS ICCS RAS £ 0.2 V, CAS £ 0.2 V 1, 5 Self-Refresh) Notes: 1. 2. 3. 4. 5. ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH. VCC – 0.2 V £ VIH £ 6.5 V, –1.0 V £ VIL £ 0.2 V. SL version. 5/17 ¡ Semiconductor MSM514265C/CSL AC Characteristics (1/2) (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3 Parameter Symbol MSM514265 MSM514265 MSM514265 C/CSL-60 C/CSL-70 Unit Note C/CSL-50 Min. Max. Min. Max. Min. Max. 130 180 — 30 — — ns ns ns — 95 — ns — 60 — 70 ns 4, 5, 6 — 15 — 20 ns 4, 5 25 30 — — 30 35 — — 35 40 ns ns 4, 6 4, 13 — 0 15 — — 0 15 — — 0 20 — ns ns 4 4 tDOH 5 — 5 — 5 — ns CAS to Data Output Buffer Turn-off Delay Time tCEZ RAS to Data Output Buffer Turn-off Delay Time tREZ 0 15 15 0 15 0 20 ns 0 0 15 0 20 ns 7, 8 7, 8 OE to Data Output Buffer Turn-off Delay Time tOEZ WE to Data Output Buffer Turn-off Delay Time tWEZ 0 0 15 15 0 0 15 15 0 0 20 20 ns ns 7 7 Transition Time Refresh Period tT tREF 1 — 50 8 1 — 50 8 1 — 50 8 ns ms 3 16 Random Read or Write Cycle Time Read Modify Write Cycle Time tRC 110 — 150 25 — — tRWC 90 130 tHPC 20 — — — tHPRWC 75 — 80 Access Time from RAS tRAC — 50 Access Time from CAS tCAC — 15 Access Time from Column Address Access Time from CAS Precharge tAA tCPA — — Access Time from OE Output Low Impedance Time from CAS tOEA tCLZ Data Output Hold After CAS Low Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Refresh Period (SL version) tREF — 128 — 128 — 128 ms RAS Precharge Time tRP 30 — 40 — 50 — ns RAS Pulse Width ns tRAS 50 10,000 60 10,000 70 10,000 RAS Pulse Width (Fast Page Mode with EDO) tRASP 50 100,000 60 100,000 70 100,000 ns RAS Hold Time RAS Hold Time referenced to OE tROH 15 10 — — 15 15 — — 20 20 CAS Precharge Time (Fast Page Mode with EDO) tCP 7 — 10 — CAS Pulse Width tCAS 7 10,000 10 10,000 CAS Hold Time CAS to RAS Precharge Time tCSH tCRP 50 10 — — 60 10 RAS Hold Time from CAS Precharge tRHCP tCHO 30 — 5 — RAS to CAS Delay Time RAS to Column Address Delay Time tRCD tRAD 18 13 OE Hold Time from CAS (DQ Disable) tRSH — — ns ns 10 — ns 10 10,000 ns — — 70 10 — — ns ns 13 35 — 40 — ns 13 5 — 10 — ns 35 25 20 45 20 50 15 30 15 35 ns ns RAS to Second CAS Delay Time tRSCD 50 — 60 — 70 — ns Row Address Set-up Time tASR 0 — 0 — 0 — ns Row Address Hold Time tRAH 8 — 10 — 10 — ns 15 5 6 Column Address Set-up Time tASC 0 — 0 — 0 — ns 12 Column Address Hold Time tCAH 10 — 10 — 15 — ns 12 Column Address Hold Time from RAS tAR 40 — 50 — 55 — ns Column Address to RAS Lead Time tRAL 25 — 30 — 35 — ns 6/17 ¡ Semiconductor MSM514265C/CSL AC Characteristics (2/2) (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3 Parameter Symbol MSM514265 MSM514265 MSM514265 C/CSL-60 C/CSL-70 Unit Note C/CSL-50 Min. Max. Min. Max. Min. Max. Read Command Set-up Time tRCS 0 — 0 — 0 — ns 12 Read Command Hold Time tRCH 0 — 0 — 0 — ns 9, 12 Read Command Hold Time referenced to RAS tRRH 0 — 0 — 0 — ns 9 Write Command Set-up Time tWCS 0 — 0 — 0 — Write Command Hold Time tWCH — — — 15 50 — tWCR 15 45 — Write Command Hold Time from RAS 10 40 ns 10, 12 12 ns — ns Write Command Pulse Width tWP 10 — 15 — 15 — ns WE Pulse Width (DQ Disable) tWPE 5 — 7 — 7 — ns OE Command Hold Time OE Precharge Time OE Command Hold Time tOEH tOEP tOCH 15 7 7 — — — 15 10 10 — — — 20 10 10 — — — ns ns ns Write Command to RAS Lead Time Write Command to CAS Lead Time tRWL tCWL 15 15 — — 15 15 — — 20 20 — — ns ns Data-in Set-up Time tDS tDH tDHR tOED tCWD tAWD tRWD 0 — 0 — 0 — Data-in Hold Time Data-in Hold Time from RAS OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time 10 40 15 35 45 70 — — — — — — 10 50 15 35 50 80 — — — — — — 15 55 20 45 60 95 — — — — — — ns 11, 12 ns 11, 12 ns ns ns 10 ns 10 ns 10 CAS Precharge WE Delay Time tCPWD 50 — 55 — 65 — ns 10 CAS Active Delay Time from RAS Precharge 14 tRPC 10 — 10 — 10 — ns 12 RAS to CAS Set-up Time (CAS before RAS) tCSR RAS to CAS Hold Time (CAS before RAS) tCHR RAS Pulse Width tRASS (CAS before RAS Self-Refresh) RAS Precharge Time tRPS (CAS before RAS Self-Refresh) 10 15 — — 10 15 — — 10 15 — — ns ns 12 13 100 — 100 — 100 — ms 16 90 — 110 — 130 — ns 16 CAS Hold Time (CAS before RAS Self-Refresh) –30 — –40 — –50 — ns 16 tCHS 7/17 ¡ Semiconductor Notes: MSM514265C/CSL 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 1 TTL load and 50 pF. The output timing reference levels are VOH = 2.0 V (IOH = –2 mA) and VOL = 0.8 V (IOL = 2 mA). 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tCEZ (Max.), tREZ (Max.), tWEZ (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tCEZ and tREZ must be satisfied for open circuit condition. 9. tRCH or tRRH must be satisfied for a read cycle. 10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to the UCAS and LCAS, leading edges in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 12. These parameters are determined by the falling edge of either UCAS or LCAS, whichever is earlier. 13. These parameters are determined by the rising edge of either UCAS or LCAS, whichever is later. 14. tCWL should be satisfied by both UCAS and LCAS. 15. tCP is determined by the time both UCAS and LCAS are high. 16. Only SL version. 8/17 E2G0097-17-41J , ,, , , ,,,, ,, ¡ Semiconductor MSM514265C/CSL TIMING WAVEFORM Read Cycle tRC tRP tRAS VIH – RAS VIL – tAR tCRP tCSH tCRP tRCD VIH – CAS VIL – tRAD tASR Address VIH – VIL – tRSH tCAS tRAH tASC tRAL tCAH Column Row tRCS WE OE VIH – VIL – tAA tROH tREZ tOEA VIH – VIL – tCAC tRAC DQ VOH – tOEZ Open VOL – tRCH tRRH tCEZ Valid Data-out tCLZ "H" or "L" Write Cycle (Early Write) tRC tRP tRAS RAS VIH – VIL – tAR tCRP VIH – CAS VIL – VIH – VIL – tCSH tRCD tRSH tCAS tRAD tRAH tASR Address tCRP tASC Row tCAH tRAL Column tWCS VIH – WE VIL – tWCH tWP tCWL tWCR tRWL VIH – OE VIL – tDS DQ VIH – VIL – tDHR tDH Valid Data-in Open "H" or "L" 9/17 , ,, ¡ Semiconductor MSM514265C/CSL Read Modify Write Cycle tRWC tRAS RAS VIH – VIL – tRP tAR tCRP tCSH tCRP tRCD tRSH tCAS VIH – CAS VIL – tASR VIH – Address VIL – WE VIH – VIL – OE VIH – VIL – tRAH tASC tCAH Column Row tRAD tRWD tAA tAWD tRCS tOEA tOED tCAC tRAC DQ VI/OH– VI/OL– tCWL tRWL tWP tCWD tCLZ tOEZ Valid Data-out tOEH tDS tDH Valid Data-in "H" or "L" 10/17 ,,,, , , ¡ Semiconductor MSM514265C/CSL Fast Page Mode Read Cycle (Part-1) tRASP RAS VIH – VIL – tAR tCRP CAS WE tRHCP tHPC tRCD tCP tCP tCAS VIH – VIL – tCAS tCAS tRAD tASR Address tRP tRSCD VIH – VIL – tRAH tASC Row tCSH tCAH tASC Column tASC tCAH Column Column tRCS tRRH VIH – VIL – tCHO DQ tOCH tRAC tAA OE tCAH tOEP tCPA tOEA tCAC VOH – VOL – tOEZ tCAC Valid Data-out Valid Data-out tCLZ tOEA tOEA tCAC tDOH tOEP tAA tAA VIH – VIL – tOEZ Valid* Data-out * : Same Data, tREZ Valid* Data-out "H" or "L" Fast Page Mode Read Cycle (Part-2) tRASP RAS VIH – VIL – tAR VIH – VIL – WE OE DQ VIH – VIL – VIH – VIL – tRCD tCP tCAS tCAS tRAD tRAH tCSH tASC tCAH Row tASC Column tCAH Column tRCS tASC tCAH Column tRCS tRAC tAA VIH – VIL – VOH – VOL – tCRP tCP tCAS tASR Address tRHCP tHPC tCRP CAS tRP tRSCD tRCH tWPE tAA tAA tCPA tOEA tCAC tCLZ tWEZ Valid Data-out tCAC tDOH tCAC Valid Data-out tCEZ Valid Data-out "H" or "L" 11/17 , ,, , , ¡ Semiconductor MSM514265C/CSL Fast Page Mode Write Cycle (Early Write) tRP tRASP tRSCD RAS VIH – VIL – tAR CAS tRAD VIH – VIL – Row VIH – VIL – OE VIH – VIL – DQ tASC Column tWCS WE tCP tCAS tCSH tASC tCAH tRAH tDHR tCAS tCAH tASC Column tWCH tDS VIH – VIL – tHPC tCP tCAS VIH – VIL – tASR Address tHPC tRCD tCRP tWCS tDH Valid Data-in Column tWCH tDS tRSH tCAH tDH Valid Data-in tWCS tWCH tDS tDH Valid Data-in "H" or "L" Fast Page Mode Read Modify Write Cycle tRASP tRSCD RAS tRWD VIH – VIL – tAR tCRP CAS VIH – VIL – VIH – VIL – tCWD tRAD tASR Address tCP tRCD Row tCWL tCAH tRCS tAWD VIH – VIL – tAWD tDS tWP tOED tOEA tCAC DQ tOEZ Valid Data-out tCLZ tRWL tCWD tRAC VIH – VIL – VI/OH – VI/OL – tCPA tCAH Column tAA OE tASC Column tRCS WE tCPWD tHPRWC tRAH tASC tAA tOEH tDS tOED tOEA tCAC tDH Valid Data-in tOEZ Valid Data-out tCLZ tWP tOEH tDH Valid Data-in "H" or "L" 12/17 , ¡ Semiconductor MSM514265C/CSL RAS-Only Refresh Cycle tRC RAS VIH – VIL – CAS Address VIH – VIL – tRP tRAS tCRP tRPC tASR VIH – tRAH Row VIL – tCEZ DQ VOH – Open VOL – Note: WE, OE = "H" or "L" "H" or "L" CAS before RAS Refresh Cycle tRC tRP RAS VIH – VIL – DQ VIH – VIL – VOH – VOL – tRP tRPC tRPC tCP CAS tRAS tCSR tCHR tCEZ Open Note: WE, OE, Address = "H" or "L" 13/17 , ,, ,, , ,, ¡ Semiconductor MSM514265C/CSL Hidden Refresh Read Cycle tRC tRAS RAS CAS VIH – VIL – tCRP WE OE tRSH tRCD VIH – VIL – VIH – VIL – tRAD tASC Row Column tRCS tRRH tRAL tAA tROH tOEA VIH – VIL – tCAC tCLZ tRAC DQ tCHR tCAH tRAH VIH – VIL – VOH – VOL – tRP tAR tASR Address tRC tRAS tRP tOEZ Open Valid Data-out "H" or "L" Hidden Refresh Write Cycle tRC tRAS RAS CAS Address VIH – VIL – VIH – VIL – VIH – VIL – VIH – VIL – OE VIH – VIL – DQ VIH – VIL – tRP tAR tCRP tASR tRCD tRSH tRAD tASC tCAH tRAH tCHR tRAL Column Row tRWL tWCH tWCS WE tRC tRAS tRP tWP tWCR tDS tDH Valid Data-in tDHR "H" or "L" 14/17 ¡ Semiconductor CAS before RAS Self-Refresh Cycle tRASS tRP RAS VIH – VIL – tRPC tCP CAS VIH – VIL – VOH – VOL – tRPS tRPC tCHS tCSR tCEZ DQ , MSM514265C/CSL Open Note: WE, OE, Address = "H" or "L" Only SL version "H" or "L" 15/17 ¡ Semiconductor MSM514265C/CSL PACKAGE DIMENSIONS (Unit : mm) SOJ40-P-400-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.70 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 16/17 ¡ Semiconductor MSM514265C/CSL (Unit : mm) TSOPII44/40-P-400-0.80-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.49 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 17/17