E2G0023-17-41 ¡ Semiconductor MSM514400D/DL ¡ Semiconductor This version: Jan. 1998 MSM514400D/DL Previous version: May 1997 1,048,576-Word ¥ 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE DESCRIPTION The MSM514400D/DL is a 1,048,576-word ¥ 4-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM514400D/DL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/ single-layer metal CMOS process. The MSM514400D/DL is available in a 26/20-pin plastic SOJ, 20pin plastic ZIP, or 26/20-pin plastic TSOP. The MSM514400DL (the low-power version) is specially designed for lower-power applications. FEATURES • 1,048,576-word ¥ 4-bit configuration • Single 5 V power supply, ±10% tolerance • Input : TTL compatible, low input capacitance • Output : TTL compatible, 3-state • Refresh : 1024 cycles/16 ms, 1024 cycles/128 ms (L-version) • Fast page mode, read modify write capability • CAS before RAS refresh, hidden refresh, RAS-only refresh capability • Multi-bit test mode capability • Package options: 26/20-pin 300 mil plastic SOJ (SOJ26/20-P-300-1.27) (Product : MSM514400D/DL-xxSJ) 20-pin 400 mil plastic ZIP (ZIP20-P-400-1.27) (Product : MSM514400D/DL-xxZS) 26/20-pin 300 mil plastic TSOP (TSOPII26/20-P-300-1.27-K) (Product : MSM514400D/DL-xxTS-K) xx indicates speed rank. PRODUCT FAMILY Family Access Time (Max.) tRAC tAA tCAC tOEA Cycle Time Power Dissipation (Min.) Operating (Max.) Standby (Max.) MSM514400D/DL-50 50 ns 25 ns 13 ns 13 ns 90 ns 550 mW MSM514400D/DL-60 60 ns 30 ns 15 ns 15 ns 110 ns 495 mW MSM514400D/DL-70 70 ns 35 ns 20 ns 20 ns 130 ns 440 mW 5.5 mW/ 1.1 mW (L-version) 1/17 ¡ Semiconductor MSM514400D/DL PIN CONFIGURATION (TOP VIEW) OE 1 DQ1 1 26 VSS DQ2 2 25 DQ4 DQ3 3 WE 3 24 DQ3 VSS 5 RAS 4 23 CAS DQ2 7 22 OE RAS 9 A9 5 A0 11 18 A8 A2 13 A1 10 17 A7 VCC 15 A2 11 16 A6 A5 17 A3 12 15 A5 A7 19 VCC 13 14 A4 A0 9 26/20-Pin Plastic SOJ 2 CAS 4 DQ4 6 DQ1 8 WE DQ1 1 26 VSS DQ2 2 25 DQ4 WE 3 24 DQ3 RAS 4 23 CAS 10 A9 12 A1 14 A3 16 A4 18 A6 20 A8 A9 5 22 OE A0 9 18 A8 A1 10 17 A7 A2 11 16 A6 A3 12 15 A5 VCC 13 14 A4 20-Pin Plastic ZIP Pin Name A0 - A9 26/20-Pin Plastic TSOP (K Type) Function Address Input RAS Row Address Strobe CAS Column Address Strobe DQ1 - DQ4 Data Input/Data Output OE Output Enable WE Write Enable VCC Power Supply (5 V) VSS Ground (0 V) 2/17 ¡ Semiconductor MSM514400D/DL BLOCK DIAGRAM RAS Timing Generator Timing Generator CAS 10 Column Address Buffers 10 Write Clock Generator Column Decoders WE OE 4 Internal Address Counter A0 - A9 Refresh Control Clock Sense Amplifiers 4 I/O Selector Row Address Buffers 10 Row Decoders Word Drivers 4 4 4 4 10 Output Buffers Input Buffers DQ1 - DQ4 4 Memory Cells VCC On Chip VBB Generator VSS 3/17 ¡ Semiconductor MSM514400D/DL ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Rating Unit VT –1.0 to 7.0 V Short Circuit Output Current IOS 50 mA Power Dissipation PD* 1 W Operating Temperature Topr 0 to 70 °C Storage Temperature Tstg –55 to 150 °C Voltage on Any Pin Relative to VSS *: Ta = 25°C Recommended Operating Conditions Parameter Power Supply Voltage (Ta = 0°C to 70°C) Symbol Min. Typ. Max. Unit VCC 4.5 5.0 5.5 V VSS 0 0 0 V Input High Voltage VIH 2.4 — 6.5 V Input Low Voltage VIL –1.0 — 0.8 V Capacitance Parameter (VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz) Symbol Typ. Max. Unit Input Capacitance (A0 - A9) CIN1 — 6 pF Input Capacitance (RAS, CAS, WE, OE) CIN2 — 7 pF Output Capacitance (DQ1 - DQ4) CI/O — 7 pF 4/17 ¡ Semiconductor MSM514400D/DL DC Characteristics Parameter (VCC = 5 V ±10%, Ta = 0°C to 70°C) Symbol Condition MSM514400 MSM514400 MSM514400 D/DL-50 D/DL-60 D/DL-70 Unit Note Min. Max. Min. Max. Min. Max. Output High Voltage VOH IOH = –5.0 mA 2.4 VCC 2.4 VCC 2.4 VCC V Output Low Voltage VOL IOL = 4.2 mA 0 0.4 0 0.4 0 0.4 V Input Leakage Current ILI –10 10 –10 10 –10 10 mA –10 10 –10 10 –10 10 mA — 100 — 90 — 80 mA 1, 2 — 2 — 2 — 2 — 1 — 1 — 1 — 200 — 200 — — 100 — 90 — 5 — — 100 — — 0 V £ VI £ 6.5 V; All other pins not under test = 0 V Output Leakage Current ILO Average Power Supply Current ICC1 (Operating) DQ disable 0 V £ VO £ 5.5 V RAS, CAS cycling, tRC = Min. RAS, CAS = VIH Power Supply Current (Standby) ICC2 RAS, CAS ≥ VCC –0.2 V 1 200 mA 1, 5 — 80 mA 1, 2 5 — 5 mA — 90 — 80 mA 1, 2 80 — 70 — 60 mA 1, 3 300 — 300 — 300 mA RAS cycling, Average Power ICC3 CAS = VIH, Supply Current (RAS-only Refresh) tRC = Min. RAS = VIH, Power Supply Current (Standby) ICC5 CAS = VIL, Supply Current ICC6 (CAS before RAS Refresh) 1 DQ = enable Average Power RAS cycling, CAS before RAS RAS = VIL, Average Power ICC7 CAS cycling, Supply Current (Fast Page Mode) tPC = Min. Average Power tRC = 125 ms, ICC10 CAS before RAS, Supply Current (Battery Backup) Notes : 1. 2. 3. 4. 5. mA tRAS £ 1 ms 1, 4, 5 ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH. VCC – 0.2 V £ VIH £ 6.5 V, –1.0 V £ VIL £ 0.2 V. L-version. 5/17 ¡ Semiconductor MSM514400D/DL AC Characteristics (1/2) (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 11, 12 Parameter MSM514400 MSM514400 MSM514400 D/DL-50 D/DL-70 D/DL-60 Unit Note Symbol Min. Max. Min. Max. Min. Max. tRC 90 — 110 — 130 — ns tRWC 131 — 150 — 180 — ns tPC 35 — 40 — 45 — ns tPRWC 76 — 80 — 95 — ns Access Time from RAS tRAC — 50 — 60 — 70 ns 4, 5, 6 Access Time from CAS tCAC — 13 — 15 — 20 ns 4, 5 Access Time from Column Address tAA — 25 — 30 — 35 ns 4, 6 Access Time from CAS Precharge tCPA — 30 — 35 — 40 ns 4 Access Time from OE tOEA — 13 — 15 — 20 ns 4 Output Low Impedance Time from CAS tCLZ 0 — 0 — 0 — ns 4 CAS to Data Output Buffer Turn-off Delay Time tOFF 0 13 0 15 0 20 ns 7 OE to Data Output Buffer Turn-off Delay Time Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time tOEZ 0 13 0 15 0 20 ns 7 Transition Time tT 3 50 3 50 3 50 ns 3 Refresh Period tREF — 16 — 16 — 16 ms Refresh Period (L-version) tREF — 128 — 128 — 128 ms RAS Precharge Time tRP 30 — 40 — 50 — ns RAS Pulse Width tRAS 50 10,000 60 10,000 70 10,000 ns RAS Pulse Width (Fast Page Mode) tRASP 50 100,000 60 100,000 70 100,000 ns RAS Hold Time tRSH 13 — 15 — 20 — ns RAS Hold Time referenced to OE tROH 10 — 15 — 20 — ns CAS Precharge Time (Fast Page Mode) tCP 10 — 10 — 10 — ns CAS Pulse Width tCAS 13 10,000 15 10,000 20 10,000 ns CAS Hold Time tCSH 50 — 60 — 70 — ns CAS to RAS Precharge Time tCRP 5 — 5 — 5 — ns RAS Hold Time from CAS Precharge tRHCP 30 — 35 — 40 — ns RAS to CAS Delay Time tRCD 20 37 20 45 20 50 ns 5 RAS to Column Address Delay Time tRAD 15 25 15 30 15 35 ns 6 Row Address Set-up Time tASR 0 — 0 — 0 — ns Row Address Hold Time tRAH 10 — 10 — 10 — ns Column Address Set-up Time tASC 0 — 0 — 0 — ns Column Address Hold Time tCAH 10 — 15 — 15 — ns Column Address Hold Time from RAS tAR 45 — 50 — 55 — ns Column Address to RAS Lead Time tRAL 25 — 30 — 35 — ns 6/17 ¡ Semiconductor MSM514400D/DL AC Characteristics (2/2) (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 11, 12 Parameter Symbol MSM514400 MSM514400 MSM514400 D/DL-50 D/DL-70 D/DL-60 Unit Note Min. Max. Min. Max. Min. Max. Read Command Set-up Time tRCS 0 — 0 — 0 — ns Read Command Hold Time tRCH 0 — 0 — 0 — ns 8 Read Command Hold Time referenced to RAS tRRH 0 — 0 — 0 — ns 8 Write Command Set-up Time tWCS 0 — 0 — 0 — ns 9 Write Command Hold Time tWCH 10 — 10 — 10 — ns Write Command Hold Time from RAS tWCR 40 — 45 — 50 — ns Write Command Pulse Width tWP 10 — 10 — 10 — ns OE Command Hold Time tOEH 13 — 15 — 20 — ns Write Command to RAS Lead Time tRWL 13 — 15 — 20 — ns Write Command to CAS Lead Time tCWL 13 — 15 — 20 — ns Data-in Set-up Time tDS 0 — 0 — 0 — ns 10 Data-in Hold Time tDH 10 — 15 — 15 — ns 10 Data-in Hold Time from RAS tDHR 45 — 50 — 55 — ns OE to Data-in Delay Time tOED 13 — 15 — 20 — ns CAS to WE Delay Time tCWD 36 — 35 — 45 — ns 9 Column Address to WE Delay Time tAWD 48 — 50 — 60 — ns 9 RAS to WE Delay Time tRWD 73 — 80 — 95 — ns 9 CAS Precharge WE Delay Time tCPWD 53 — 55 — 65 — ns 9 tRPC 10 — 10 — 10 — ns CAS Active Delay Time from RAS Precharge RAS to CAS Set-up Time (CAS before RAS) tCSR 5 — 5 — 5 — ns RAS to CAS Hold Time (CAS before RAS) tCHR 10 — 10 — 10 — ns WE to RAS Precharge Time (CAS before RAS) tWRP 10 — 10 — 10 — ns WE Hold Time from RAS (CAS before RAS) tWRH 10 — 10 — 10 — ns RAS to WE Set-up Time (Test Mode) tWTS 10 — 10 — 10 — ns RAS to WE Hold Time (Test Mode) tWTH 10 — 10 — 10 — ns 7/17 ¡ Semiconductor Notes: MSM514400D/DL 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet is a 2-bit parallel test function. CA0 is not used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. 12. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet. 8/17 E2G0094-17-41G ,, , , ,,,, ¡ Semiconductor MSM514400D/DL TIMING WAVEFORM Read Cycle tRC tRP tRAS VIH – RAS VIL – tAR tCSH tCRP CAS tRCD VIH – VIL – Address WE OE VIL – tRSH tCAS tRAD tASR VIH – tCRP tRAH tASC Column Row tRCS tRCH tRRH VIH – VIL – tAA tROH tOEA VIH – VIL – tCAC tRAC DQ tRAL tCAH VOH – tOEZ Open VOL – tOFF Valid Data-out tCLZ "H" or "L" Write Cycle (Early Write) tRC tRP tRAS RAS VIH – VIL – tAR tCRP VIH – CAS VIL – WE VIH – VIL – tCSH tRCD tASC Row tCAH tWCH VIH – tCWL tWP VIL – tRWL VIH – VIL – tDS DQ tRAL Column tWCS tWCR OE tRSH tCAS tRAD tRAH tASR Address tCRP VIH – VIL – tDHR tDH Valid Data-in Open "H" or "L" 9/17 ,,, ¡ Semiconductor MSM514400D/DL Read Modify Write Cycle tRWC tRAS RAS VIH – VIL – tRP tAR tCRP tCSH tCRP tRCD tRSH tCAS VIH – CAS VIL – tASR VIH – Address VIL – WE VIH – VIL – OE VIH – VIL – DQ VI/OH– VI/OL– tRAH tASC tCAH Column Row tRAD tRWD tAA tRCS tOEA tCWL tRWL tWP tCWD tAWD tOED tRAC tCAC tCLZ tOEZ Valid Data-out tOEH tDS tDH Valid Data-in "H" or "L" 10/17 ¡ Semiconductor MSM514400D/DL , , , ,, , Fast Page Mode Read Cycle tRASP VIH – RAS V – IL VIH – CAS VIL – Address WE VIH – VIL – tRP tAR tCRP tRHCP tPC tRCD tRAD tASR tCP tCAS tRAH tASC tCSH tCAH tASC Column Row VIH – VIL – VOH – DQ VOL – tCAC Column tRCS tRCH tOFF tOEZ tRCH tAA tCPA tOEA tCAC tOFF tRRH tOEA tCAC tOEZ tCLZ Valid Data-out tCLZ tRCS tAA tCPA tOEA tRAC tRAL tCAH tASC Column tAA VIH – OE VIL – tCAS tCAH tRCH tRCS tCP tCAS tCRP tRSH tCLZ tOFF tOEZ Valid Data-out Valid Data-out "H" or "L" Fast Page Mode Write Cycle (Early Write) tRASP tAR VIH – RAS V – IL tCRP VIH – CAS VIL – Address VIH – VIL – tRAH tASC Row VIH – VIL – tDS DQ VIH – VIL – tCSH tCAH Column tCWL tWCH tWP tRAD tRHCP tRSH tRCD tWCS WE tPC tCAS tASR tRP tWCR tDH Valid Data-in tDHR tCP tCAS tASC tCAH tDH Valid Data-in tCAS tASC Column tCWL tWCS tWCH tWP tDS tCP tCRP tCAH tRAL Column tRWL tCWL tWCS tWCH tWP tDS tDH Valid Data-in Note: OE = "H" or "L" "H" or "L" 11/17 ¡ Semiconductor MSM514400D/DL ,,, , , , , Fast Page Mode Read Modify Write Cycle VIH – RAS VIL – tRASP tAR tRP tCSH tRCD VIH – CAS VIL – tCRP tCAS tASC tCAH tCAH Column Column tASC Column Row tRCS tCPWD tCWD tRWD tCWD tRCS V WE IH – VIL – tCWL tAWD tCWL tWP tDH VI/OH– VI/OL – Out tCLZ tOEA tOED tOEZ tCAC In tDH tDS tOEA tOEZ tCAC tWP tCPA tAA tOED VIH – OE V – IL tCWL tROH tWP tDH tDS tOEA tRWL tAWD tCPA tAA tAA tRAL tRCS tCPWD tCWD tAWD tDS tRAC DQ tCP tCAS tASC tCAH tRAH VIH – VIL – tCP tCAS tRSH tRAD tASR Address tPRWC Out tOED In tCLZ tOEZ tCAC Out tCLZ In "H" or "L" RAS-Only Refresh Cycle tRC RAS CAS Address VIL – VIH – VIL – VIH – VIL – tRP tRAS VIH – tCRP tASR tRPC tRAH Row tOFF DQ VOH – VOL – Open Note: WE, OE = "H" or "L" "H" or "L" 12/17 M L K ^ ] \ S R Q P ¡ Semiconductor MSM514400D/DL CAS before RAS Refresh Cycle tRP RAS tRAS tRC tRP VIH – VIL – tRPC tRPC tCP CAS tCSR tCHR tWRP tWRH VIH – VIL – tWRP ,,, WE VIH – VIL – DQ VOH – VOL – tOFF Open Note: OE, Address = "H" or "L" "H" or "L" Hidden Refresh Read Cycle tRC tRAS RAS CAS VIH – VIL – tCRP VIH – VIL – VIH – VIL – tRAS tRP tRP tAR tRSH tRCD tRAD tASC tRAH tASR Address tRC Row tCHR tCAH Column tRCS tRAL VIH – WE V IL – tAA tRRH tROH tOEA VIH – OE V IL – tRAC DQ VOH – VOL – tCAC tCLZ tOFF tOEZ Valid Data-out "H" or "L" 13/17 ¡ Semiconductor MSM514400D/DL Hidden Refresh Write Cycle tRC tRAS RAS CAS Address VIH – VIL – tRP tAR , ,,,, , VIH – VIL – VIH – VIL – tCRP tASR tRCD tRSH tRAD tASC tCAH tRAH Row WE VIH – VIL – OE VIH – VIL – tCHR tRAL Column tWCH tWP tWCS DQ tRC tRAS tRP tDS VIH – VIL – tWRP tWRH tDH Valid Data-in tDHR "H" or "L" Test Mode Initiate Cycle tRC tRP RAS VIH – VIL – tRPC tCP CAS tRAS tCSR VIH – VIL – tWTS WE tCHR tWTH VIH – VIL – tOFF DQ VOH – VOL – Open Note: OE, Address = "H" or "L" "H" or "L" 14/17 ¡ Semiconductor MSM514400D/DL PACKAGE DIMENSIONS (Unit : mm) SOJ26/20-P-300-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.80 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 15/17 ¡ Semiconductor MSM514400D/DL (Unit : mm) ZIP20-P-400-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.50 TYP. 16/17 ¡ Semiconductor MSM514400D/DL (Unit : mm) TSOPII26/20-P-300-1.27-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.38 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 17/17