TI SMJ320LC549HFGW60

SGUS032B – OCTOBER 2002 – REVISED MAY 2003
D Processed to MIL-PRF-38535 (QML)
D Advanced Multibus Architecture With Three
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Separate 16-Bit Data Memory Buses and
One Program Memory Bus
40-Bit Arithmetic Logic Unit (ALU)
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators
17- x 17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator
Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
Data Bus With a Bus Holder Feature
Address Bus With a Bus Holder Feature
Extended Addressing Mode for 8M × 16-Bit
Maximum Addressable External Program
Space
192K x 16-Bit Maximum Addressable
Memory Space (64K Words Program,
64K Words Data, and 64K Words I/O)
On-Chip ROM with Some Configurable to
Program/Data Memory
Dual-Access On-Chip RAM
Single-Access On-Chip RAM
Single-Instruction Repeat and
Block-Repeat Operations for Program Code
Block-Memory-Move Instructions for Better
Program and Data Management
D Instructions With a 32-Bit Long Word
D
D
D
D
D
D
D
D
D
D
D
Operand
Instructions With Two- or Three-Operand
Reads
Arithmetic Instructions With Parallel Store
and Parallel Load
Conditional Store Instructions
Fast Return From Interrupt
On-Chip Peripherals
– Software-Programmable Wait-State
Generator and Programmable Bank
Switching
– On-Chip Phase-Locked Loop (PLL) Clock
Generator With Internal Oscillator or
External Clock Source
– Time-Division Multiplexed (TDM) Serial
Port
– Buffered Serial Port (BSP)
– 8-Bit Parallel Host-Port Interface (HPI)
– One 16-Bit Timer
– External-Input/Output (XIO) Off Control
to Disable the External Data Bus,
Address Bus and Control Signals
Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
CLKOUT Off Control to Disable CLKOUT
On-Chip Scan-Based Emulation Logic,
IEEE Std 1149.1† (JTAG) Boundary Scan
Logic
16.7-ns Single-Cycle Fixed-Point
Instruction Execution Time (60 MIPS) for
3.3-V Power Supply
Packaging
– 164-Pin Ceramic Quad Flat Package
(HFG)
–55°C to 115°C Operating Temperature
Range, QML Processing
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
Copyright  2003, Texas Instruments Incorporated
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1
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
Table of Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . 10
Recommended Operating Conditions . . . . . . . . . . . 10
Parameter Measurement Information . . . . . . . . . . . . 11
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 12
Divide-by-Two/Divide-by-Four Clock Option . . . . . . 14
Multiply-by-N Clock Option . . . . . . . . . . . . . . . . . . . . . 15
Memory and Parallel I/O Interface Timing . . . . . . . . 16
I/O Timing Variation: SPICE Simulation . . . . . . . . . . 22
Ready Timing For Externally Generated
Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
HOLD and HOLDA Timings . . . . . . . . . . . . . . . . . . . .
Reset, BIO, Interrupt, and MP/MC Timings . . . . . . .
Instruction Acquisition (IAQ), Interrupt
Acknowledge (IACK), External Flag (XF),
and TOUT Timings . . . . . . . . . . . . . . . . . . . . . . .
Serial Port Receive Timing . . . . . . . . . . . . . . . . . . . . .
Serial Port Transmit Timing . . . . . . . . . . . . . . . . . . . .
Buffered Serial Port Receive Timing . . . . . . . . . . . . .
Buffered Serial Port Transmit Timing . . . . . . . . . . . .
Serial-Port Receive Timing in TDM Mode . . . . . . . .
Serial-Port Transmit Timing in TDM Mode . . . . . . . .
Host-Port Interface Timing . . . . . . . . . . . . . . . . . . . . .
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
30
33
34
35
36
38
40
41
42
48
description
The SMJ320LC549 fixed-point, digital signal processor (DSP) (hereafter referred to as the 549) is based on an
advanced modified Harvard architecture that has one program memory bus and three data memory buses. The
processor also provides an arithmetic logic unit (ALU) that has a high degree of parallelism, application-specific
hardware logic, on-chip memory, and additional on-chip peripherals. The 549 also utilizes a highly specialized
instruction set, which is the basis of its operational flexibility and speed.
Separate program and data spaces allow simultaneous access to program instructions and data, providing the
high degree of parallelism. Two reads and one write operation can be performed in a single cycle. Instructions
with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be
transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic,
and bit-manipulation operations that can all be performed in a single machine cycle. In addition, the 549 includes
the control mechanisms to manage interrupts, repeated operations, and function calls.
This data sheet contains the pin layouts, signal descriptions, and electrical specifications for the SMJ320LC549
DSP. For additional information, see the TMS320C54x, TMS320LC54x, TMS320VC54x Fixed-Point Digital
Signal Processors data sheet (literature number SPRS039). The SPRS039 is considered a family functional
overview and should be used in conjunction with this data sheet.
2
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SGUS032B – OCTOBER 2002 – REVISED MAY 2003
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
V SS
A21
CVDD
A9
A8
A7
A6
A5
A4
HD6
A3
VSS
A2
CV DD
A1
A0
DVDD
HDS2
VSS
HDS1
NC
VSS
HD5
D15
D14
D13
HD4
D12
CVDD
VSS
D11
D10
D9
D8
D7
D6
DVDD
VSS
NC
A20
A19
HFG PACKAGE†‡
(TOP VIEW)
NC
A22
NC
V SS
DV DD
A10
HD7
A11
A12
A13
A14
A15
NC
CV DD
HAS
V SS
CV DD
HCS
HR/W
READY
PS
CV DD
DS
V SS
IS
R/W
MSTRB
IOSTRB
MSC
XF
30
31
32
33
34
35
36
37
38
39
40
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
41
83
A18
A17
V SS
A16
D5
D4
D3
D2
D1
D0
RS
X2/CLKIN
X1
HD3
CLKOUT
CVDD
V SS
HPIENA
CVDD
NC
V SS
TMS
TCK
TRST
CVDD
TDI
V SS
TDO
EMU1/OFF
EMU0
TOUT
HD2
TEST1
CLKMD3
CLKMD2
CLKMD1
DVDD
BDX1
BFSX1
BCLKX1
V SS
VSS
BCLKR1
HCNTL0
VSS
BCLKR0
TCLKR
BFSR0
TFSR/TADD
BDR0
HCNTL1
VSS
TDR
CVDD
BCLKX0
TCLKX
NC
VSS
HINT
NC
CVDD
BFSX0
TFSX/TFRM
HRDY
DVDD
V SS
HD0
BDX0
TDX
CVDD
IACK
V SS
HBIL
NMI
INT0
INT1
INT2
INT3
NC
CVDD
HD1
NC
HOLDA
IAQ
HOLD
BIO
MP/MC
DV DD
NC
V SS
BDR1
BFSR1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
V SS
NC – No internal connection
† NC = No connection
‡ DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU, and VSS is the ground for both the I/O pins and the
core CPU.
The 549 signal descriptions table lists each terminal name, function, and operating mode(s) for the 164-pin
ceramic quad flatpack (CQFP).
The letter B in front of CLKRn, FSRn, DRn, CLKXn, FSXn, and DXn pin names denotes buffered serial port
(BSP), where n = 0 or 1 port. The letter T in front of CLKR, FSR, DR, CLKX, FSX, and DX pin names denotes
time-division multiplexed (TDM) serial port.
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SGUS032B – OCTOBER 2002 – REVISED MAY 2003
Pin Assignments for the 164-Pin HFG Package†
PIN
PIN
PIN
PIN
NUMBER
NAME
NUMBER
NAME
NUMBER
NAME
NUMBER
NAME
1
42
A19
84
VSS
BCLKX1
124
43
VSS
BCLKR1
83
2
VSS
NC
125
A20
3
A22
44
HCNTL0
85
BFSX1
126
NC
4
NC
45
86
BDX1
127
5
46
87
128
47
TCLKR
88
DVDD
CLKMD1
VSS
DVDD
129
D6
7
VSS
DVDD
A10
VSS
BCLKR0
48
BFSR0
89
CLKMD2
130
D7
8
HD7
49
TFSR/TADD
90
CLKMD3
131
D8
9
A11
50
BDR0
91
TEST1
132
D9
10
A12
51
HCNTL1
92
HD2
133
D10
11
A13
52
93
TOUT
134
D11
12
A14
53
VSS
TDR
94
EMU0
135
13
A15
54
95
EMU1/OFF
136
14
NC
55
CVDD
BCLKX0
VSS
CVDD
96
TDO
137
D12
15
CVDD
56
TCLKX
97
138
HD4
16
HAS
57
NC
98
VSS
TDI
139
D13
17
58
CVDD
140
D14
59
VSS
HINT
99
18
VSS
CVDD
100
TRST
141
D15
19
HCS
60
NC
101
TCK
142
HD5
20
HR/W
61
CVDD
102
TMS
143
21
READY
62
BFSX0
103
144
22
PS
63
TFSX/TFRM
104
VSS
NC
VSS
NC
145
HDS1
23
CVDD
64
HRDY
105
DS
65
DVDD
106
CVDD
HPIENA
146
24
147
VSS
HDS2
25
66
DVDD
108
VSS
CVDD
148
67
VSS
HD0
107
26
VSS
IS
149
A0
27
R/W
68
BDX0
109
CLKOUT
150
A1
28
MSTRB
69
TDX
110
HD3
151
CVDD
29
IOSTRB
70
CVDD
111
X1
152
A2
30
MSC
71
IACK
112
X2/CLKIN
153
31
XF
72
113
RS
154
32
HOLDA
73
VSS
HBIL
VSS
A3
114
D0
155
HD6
33
IAQ
74
NMI
115
D1
156
A4
34
HOLD
75
INT0
116
D2
157
A5
35
BIO
76
INT1
117
D3
158
A6
36
MP/MC
77
INT2
118
D4
159
A7
37
DVDD
78
INT3
119
D5
160
A8
38
NC
79
NC
120
A16
161
A9
39
VSS
BDR1
80
CVDD
121
CVDD
HD1
122
VSS
A17
162
81
163
A21
6
40
41
BFSR1
82
NC
123
A18
164
VSS
† DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU, and VSS is the ground for both the I/O pins and the
core CPU.
4
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Signal Descriptions
TERMINAL
NAME
TYPE†
DESCRIPTION
DATA SIGNALS
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(MSB)
Parallel port address bus A22 (MSB) through A0 (LSB). The sixteen LSBs (A15–A0) are multiplexed to address
external data/program memory or I/O. A15–A0 are placed in the high-impedance state in the hold mode. A15–A0
also go into the high-impedance state when EMU1/OFF is low. The seven MSBs (A22 to A16) are used for
extended program memory addressing.
The address bus have a feature called bus holder that eliminates passive components and the power dissipation
associated with it. The bus holders keep the address bus at the previous logic level when the bus goes into a
high-impedance state. The bus holders on the address bus are always enabled.
O/Z
(LSB)
(MSB)
I/O/Z
Parallel port data bus D15 (MSB) through D0 (LSB). D15–D0 are multiplexed to transfer data between the core
CPU and external data/program memory or I/O devices. D15–D0 are placed in the high-impedance state when
not output or when RS or HOLD is asserted. D15–D0 also go into the high-impedance state when EMU1/OFF
is low.
The data bus has a feature called bus holder that eliminates passive components and the power dissipation
associated with it. The bus holders keep the data bus at the previous logic level when the bus goes into a
high-impedance state. These bus holders are enabled or disabled by the BH bit in the bank switching control
register (BSCR).
(LSB)
INITIALIZATION, INTERRUPT AND RESET OPERATIONS
IACK
O/Z
Interrupt acknowledge signal. IACK indicates the receipt of an interrupt and that the program counter is fetching
the interrupt vector location designated by A15–0. IACK also goes into the high-impedance state when
EMU1/OFF is low.
INT0
External user interrupt inputs. INT0–INT3 are prioritized and are maskable by the interrupt mask register and the
INT1
I
interrupt mode bit. INT0 –INT3 can be polled and reset by the interrupt flag register.
INT2
INT3
† I = Input, O = Output, Z = High impedance
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SGUS032B – OCTOBER 2002 – REVISED MAY 2003
Signal Descriptions (Continued)
TERMINAL
NAME
TYPE†
DESCRIPTION
INITIALIZATION, INTERRUPT AND RESET OPERATIONS (CONTINUED)
NMI
I
Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. When
NMI is activated, the processor traps to the appropriate vector location.
RS
I
Reset input. RS causes the DSP to terminate execution and forces the program counter to 0FF80h. When RS
is brought to a high level, execution begins at location 0FF80h of the program memory. RS affects various
registers and status bits.
MP/MC
I
Microprocessor/microcomputer mode-select pin. If active-low at reset (microcomputer mode), MP/MC causes
the internal program ROM to be mapped into the upper program memory space. In the microprocessor mode,
off-chip memory and its corresponding addresses (instead of internal program ROM) are accessed by the DSP.
MULTIPROCESSING SIGNALS
I
Branch control input. A branch can be conditionally executed when BIO is active. If low, the processor executes
the conditional instruction. The BIO condition is sampled during the decode phase of the pipeline for the XC
instruction, and all other instructions sample BIO during the read phase of the pipeline.
O/Z
External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low
by RSBX XF instruction or by loading the ST1 status register. XF is used for signaling other processors in
multiprocessor configurations or as a general-purpose output pin. XF goes into the high-impedance state when
OFF is low, and is set high at reset.
DS
PS
IS
O/Z
Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for communicating
to a particular external space. Active period corresponds to valid address information. Placed into a
high-impedance state in hold mode. DS, PS, and IS also go into the high-impedance state when EMU1/OFF is
low.
MSTRB
O/Z
Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to data
or program memory. Placed in high-impedance state in hold mode. MSTRB also goes into the high-impedance
state when OFF is low.
READY
I
Data-ready input. READY indicates that an external device is prepared for a bus transaction to be completed.
If the device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the
processor performs ready-detection if at least two software wait states are programmed. The READY signal is
not sampled until the completion of the software wait states.
R/W
O/Z
Read/write signal. R/W indicates transfer direction during communication to an external device and is normally
high (in read mode), unless asserted low when the DSP performs a write operation. Placed in the high-impedance
state in hold mode, R/W also goes into the high-impedance state when EMU1/OFF is low.
IOSTRB
O/Z
I/O strobe signal. IOSTRB is always high unless low level asserted to indicate an external bus access to an I/O
device. Placed in high-impedance state in hold mode. IOSTRB also goes into the high-impedance state when
EMU1/OFF is low.
I
Hold input. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by
the ’54x, these lines go into high-impedance state.
HOLDA
O/Z
Hold acknowledge signal. HOLDA indicates to the external circuitry that the processor is in a hold state and that
the address, data, and control lines are in a high-impedance state, allowing them to be available to the external
circuitry. HOLDA also goes into the high-impedance state when EMU1/OFF is low.
MSC
O/Z
Microstate complete signal. Goes low on CLKOUT falling at the start of the first software wait state. Remains low
until one CLKOUT cycle before the last programmed software wait state. If connected to the READY line, MSC
forces one external wait state after the last internal wait state has been completed. MSC also goes into the
high-impedance state when EM1/OFF is low.
BIO
XF
MEMORY CONTROL SIGNALS
HOLD
† I = Input, O = Output, Z = High impedance
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Signal Descriptions (Continued)
TERMINAL
NAME
TYPE†
DESCRIPTION
MEMORY CONTROL SIGNALS (CONTINUED)
IAQ
O/Z
Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address
bus and goes into the high-impedance state when EMU1/OFF is low.
OSCILLATOR/TIMER SIGNALS
CLKOUT
O/Z
Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle
is bounded by the falling edges of this signal. CLKOUT also goes into the high-impedance state when EMU1/OFF
is low.
CLKMD1
CLKMD2
CLKMD3
I
Clock mode external/internal input signals. CLKMD1, CLKMD2, and CLKMD3 allow you to select and configure
different clock modes, such as crystal, external clock, and various PLL factors. Refer to PLL section for a detailed
functional description of these pins.
X2/CLKIN
I
Input pin to internal oscillator from the crystal. If the internal (crystal) oscillator is not being used, a clock can
become input to the device using this pin. The internal machine cycle time is determined by the clock
operating-mode pins (CLKMD1, CLKMD2 and CLKMD3).
X1
O
Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left
unconnected. X1 does not go into the high-impedance state when EMU1/OFF is low.
O/Z
Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is a CLKOUT-cycle
wide. TOUT also goes into the high-impedance state when EMU1/OFF is low.
I
Receive clocks. External clock signal for clocking data from the data-receive (DR) pin into the buffered serial port
receive shift registers (RSRs). Must be present during buffered serial port transfers. If the buffered serial port is
not being used, BCLKR0 and BCLKR1 can be sampled as an input by way of IN0 bit of the SPC register.
I/O/Z
Transmit clock. Clock signal for clocking data from the serial port transmit shift register (XSR) to the data transmit
(DX) pin. BCLKX can be an input if MCM in the serial port control register is cleared to 0. It also can be driven
by the device at 1/(CLKDV + 1) where CLKDV range is 0–31 CLKOUT frequency when MCM is set to 1. If the
buffered serial port is not used, BCLKX can be sampled as an input by way of IN1 of the SPC register. BCLKX0
and BCLKX1 go into the high-impedance state when OFF is low.
TOUT
BUFFERED SERIAL PORT 0 AND BUFFERED SERIAL PORT 1 SIGNALS
BCLKR0
BCLKR1
BCLKX0
BCLKX1
BDR0
BDR1
I
BDX0
BDX1
O/Z
Buffered serial-port-transmit output. Serial data is transmitted from the XSR by way of BDX. BDX0 and BDX1 are
placed in the high-impedance state when not transmitting and when EMU1/OFF is low.
I
Frame synchronization pulse for receive input. The falling edge of the BFSR pulse initiates the data-receive
process, beginning the clocking of the RSR.
I/O/Z
Frame synchronization pulse for transmit input/output. The falling edge of the BFSX pulse initiates the
data-transmit process, beginning the clocking of the XSR. Following reset, the default operating condition of
BFSX is an input. BFSX0 and BFSX1 can be selected by software to be an output when TXM in the serial control
register is set to 1. This pin goes into the high-impedance state when EMU1/OFF is low.
BFSR0
BFSR1
BFSX0
BFSX1
Buffered serial-data-receive input. Serial data is received in the RSR by BDR0/BDR1.
TDM SERIAL PORT SIGNALS
TCLKR
I
TDM receive clock input
TDR
I
TDM serial data-receive input
TFSR/TADD
I/O
TDM receive frame synchronization or TDM address
TCLKX
I/O/Z
TDM transmit clock
TDX
O/Z
TDM serial data-transmit output
TFSX/TFRM
I/O/Z
TDM transmit frame synchronization
† I = Input, O = Output, Z = High impedance
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SGUS032B – OCTOBER 2002 – REVISED MAY 2003
Signal Descriptions (Continued)
TERMINAL
NAME
TYPE†
DESCRIPTION
HOST-PORT INTERFACE SIGNALS
HD0–HD7
I/O/Z
Parallel bidirectional data bus. HD0–HD7 are placed in the high-impedance state when not outputting data. The
signals go into the high-impedance state when EMU1/OFF is low. These pins each have bus holders similar to
those on the address/data bus, but which are always enabled.
HCNTL0
HCNTL1
I
Control inputs
HBIL
I
Byte-identification input
HCS
I
Chip-select input
HDS1
HDS2
I
Data strobe inputs
HAS
I
Address strobe input
HR/W
I
Read/write input
HRDY
O/Z
Ready output. This signal goes into the high-impedance state when EMU1/OFF is low.
HINT
O/Z
Interrupt output. When the DSP is in reset, this signal is driven high. The signal goes into the high-impedance
state when EMU1/OFF is low.
I
HPI module select input. This signal must be tied to a logic 1 state to have HPI selected. If this input is left open
or connected to ground, the HPI module will not be selected, internal pullup for the HPI input pins are enabled,
and the HPI data bus has keepers set. This input is provided with an internal pull-down resistor which is active
only when RS is low. HPIENA is sampled when RS goes high and ignored until RS goes low again. Refer to the
Electrical Characteristics section for the input current requirements for this pin.
HPIENA
SUPPLY PINS
CVDD
Supply
DVDD
Supply
+VDD. CVDD is the dedicated power supply for the core CPU.
+VDD. DVDD is the dedicated power supply for I/O pins.
VSS
Supply
Ground. VSS is the dedicated power ground for the device.
IEEE1149.1 TEST PINS
TCK
I
IEEE standard 1149.1 test clock. Pin with internal pullup device. This is normally a free-running clock signal with
a 50% duty cycle. The changes on the test-access port (TAP) of input signals TMS and TDI are clocked into the
TAP controller, instruction register, or selected test data register on the rising edge of TCK. Changes at the TAP
output signal (TDO) occur on the falling edge of TCK.
TDI
I
IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK.
TDO
O/Z
IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) is shifted out
of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in
progress. TDO also goes into the high-impedance state when EMU1/OFF is low.
TMS
I
IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into
the TAP controller on the rising edge of TCK.
TRST
I
IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the
operations of the device. If TRST is not connected or driven low, the device operates in its functional mode, and
the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device.
EMU0
I/O/Z
Emulator interrupt 0 pin. When TRST is driven low, EMU0 must be high for the activation of the EMU1/OFF
condition. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined
as input/output by way of IEEE standard 1149.1 scan system.
† I = Input, O = Output, Z = High impedance
8
POST OFFICE BOX 1443
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SGUS032B – OCTOBER 2002 – REVISED MAY 2003
Signal Descriptions (Continued)
TERMINAL
NAME
TYPE†
DESCRIPTION
IEEE1149.1 TEST PINS (CONTINUED)
EMU1/OFF
I/O/Z
Emulator interrupt 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or
from the emulator system and is defined as input/output by way of IEEE standard 1149.1 scan system. When
TRST is driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active low, puts all output
drivers into the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not
for multiprocessing applications). Therefore, for the OFF condition, the following conditions apply:
TRST = low,
EMU0 = high
EMU1/OFF = low
DEVICE TEST PIN
TEST1
I
Test1 – Reserved for internal use only. This pin must not be connected (NC).
† I = Input, O = Output, Z = High impedance
POST OFFICE BOX 1443
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9
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
absolute maximum ratings over specified temperature range (unless otherwise noted)†
Supply voltage, DVDD and CVDD‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.6 V
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.6 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.6 V
Thermal resistance, Junction-to-Case, ΘJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.82°C/W
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 115°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ All voltage values are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
UNIT
DVDD
Device supply voltage
3
3.3
3.6
V
CVDD
Core supply voltage
3
3.3
3.6
V
VSS
Supply voltage, GND
VIH
High-level
High
level in
input
ut voltage
0
Schmitt trigger inputs,
DVDD = 3.3±0.3 V§
All other inputs
VIL
IOH
Low-level input voltage¶
IOL
TC
Low-level output current
2.5
DVDD + 0.3*
2
DVDD + 0.3*
–0.3*
High-level output current
Operating case temperature
V
–55
V
0.8
V
–300
µA
1.5
mA
115
°C
*Not production tested.
§ The following pins have schmitt trigger inputs: RS, INTn, NMI, X2/CLKIN, CLKMDn, TCK, HAS, HCS, HDSn, BCLKRn, TCLKR, BCLKXn, and
TCLKX
¶ VIL for TRST is not production tested.
See Figure 1 for 3.3-V device test load circuit values.
10
POST OFFICE BOX 1443
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SGUS032B – OCTOBER 2002 – REVISED MAY 2003
PARAMETER MEASUREMENT INFORMATION
timing parameter symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols,
some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their meanings:
Letters and symbols and their meanings:
a
access time
H
High
c
cycle time (period)
L
Low
d
delay time
V
Valid
dis
disable time
Z
High impedance
en
enable time
f
fall time
h
hold time
r
rise time
su
setup time
t
transition time
v
valid time
w
pulse duration (width)
X
Unknown, changing, or don’t care level
signal transition reference points
All timing references are made at a voltage of 1.5 volts, except rise and fall times which are referenced at the
10% and 90% points of the specified low and high logic levels, respectively.
IOL
50 Ω
Tester Pin
Electronics
VLoad
CT
Output
Under
Test
IOH
Where: IOL
IOH
VLoad
CT
=
=
=
=
1.5 mA (all outputs)
300 µA (all outputs)
1.5 V
40 pF typical load circuit capacitance.
Figure 1. 3.3-V Test Load Circuit
POST OFFICE BOX 1443
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11
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
electrical characteristics and operating conditions
electrical characteristics over recommended operating case temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
VOH
High-level output voltage‡
VDD = 3.3±0.3 V,
VOL
Low-level output voltage‡
In ut current in high
Input
impedance
A[22:0]
–150
250
IIZ
IOL = MAX
VDD = MAX§
All other pins
VDD = MAX, VI = VSS to VDD
–10
10
TRST
With internal pulldown
–10
800
With internal pulldown, RS = 0
–20
400
RS = 1
–20
10
HPIENA
II
Input current
(VI = VSS to VDD)
IOH = MAX
TMS, TCK, TDI, HPI¶
With internal pullups
–400
10
D[15:0], HD[7:0]
Bus holders enabled, VDD = MAX§
–150
250
X2/CLKIN
Oscillator enabled
– 40
40
Supply current, core CPU
Supply current, pins
IDD
Su ly current,
Supply
standby
Ci
Input capacitance
–10
VDD = 3.3 V, fx = 40 MHz,# TC = 25°C
DVDD = 3.3 V, fx = 40 MHz,# TC = 25°C
IDLE2
PLL × 1 mode,
IDLE3
Divide-by-two mode, CLKIN stopped
40 MHz input
UNIT
V
0.4
All other input-only pins
IDDC
IDDP
2.4
V
µA
µA
10
28||
mA
10.8k
mA
2
mA
15
µA
15
pF
Co
Output capacitance
15
pF
† All values are typical unless otherwise specified.
‡ All input and output voltage levels except RS, INT0–INT3, NMI, X2/CLKIN, CLKMD1–CLKMD3 are LVTTL-compatible. Not applicable to X1
which is an analog signal to a crystal oscillator.
§ VIL(MIN) ≤ VI ≤ VIL(MAX) or VIH(MIN) ≤ VI ≤ VIH(MAX)
¶ HPI input signals except for HPIENA.
# Clock mode: PLL × 1 with external source
|| This value was obtained with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program being
executed.
k This value was obtained with single-cycle external writes, CLKOFF = 0 and load = 15 pF. For more details on how this calculation is performed,
refer to the Calculation of TMS320C54x Power Dissipation application report (literature number SPRA164).
12
POST OFFICE BOX 1443
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SGUS032B – OCTOBER 2002 – REVISED MAY 2003
internal oscillator with external crystal
The internal oscillator is enabled by selecting the appropriate clock mode at reset (this is device-dependent –
see PLL section) and connecting a crystal or ceramic resonator across X1 and X2/CLKIN. The CPU clock
frequency is one-half the crystal’s oscillation frequency following reset. After reset, the clock mode of the devices
with the software PLL can also be changed to divide-by-four. Since the internal oscillator can be used as a clock
source to the PLL, the crystal oscillation frequency can be multiplied to generate the CPU clock if desired.
The crystal should be in fundamental mode operation and parallel resonant with an effective series resistance
of 30ohms and power dissipation of 1 mW. The connection of the required circuit, consisting of the crystal and
two load capacitors, is shown in Figure 2. The load capacitors, C1 and C2, should be chosen such that the
equation below is satisfied. CL in the equation is the load specified for the crystal.
CL +
C 1C 2
(C 1 ) C 2)
recommended operating conditions (see Figure 2)
549-60
fx
Input clock frequency
*Not production tested.
† This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞.
‡ It is recommended that the PLL clocking option be used for maximum frequency operation.
X1
MIN
10†*
MAX
20‡*
UNIT
MHz
X2/CLKIN
Crystal
C1
C2
Figure 2. Internal Divide-by-Two Clock Option With External Crystal
POST OFFICE BOX 1443
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13
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
divide-by-two/divide-by-four clock option – PLL disabled
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two or four to
generate the internal machine cycle. The selection of the clock mode is described in the clock generator section.
When an external clock source is used, the frequency injected must conform to specifications listed in the timing
requirements table.
switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 2 and
Figure 3, and the recommended operating conditions table)
549-60
PARAMETER
tc(CO)
td(CIH-CO)
tf(CO)
tr(CO)
MIN
TYP
3*
2tc(CI)
6
Cycle time, CLKOUT
Delay time, X2/CLKIN high to CLKOUT high/low
Fall time, CLKOUT†
10*
2
Rise time, CLKOUT†
tw(COL)
tw(COH)
MAX
†
ns
ns
ns
2
Pulse duration, CLKOUT low†
Pulse duration, CLKOUT high†
UNIT
ns
H–4*
H–2
H*
ns
H–4*
H–2
H*
ns
*Not production tested.
† This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞.
timing requirements (see Figure 3)
549-60
MIN
20‡
MAX
†
UNIT
tc(CI)
tf(CI)
Cycle time, X2/CLKIN
Fall time, X2/CLKIN
8*
ns
tr(CI)
tw(CIL)
Rise time, X2/CLKIN
ns
7*
8*
†
7*
†
ns
Pulse duration, X2/CLKIN low
tw(CIH) Pulse duration, X2/CLKIN high
*Not production tested.
† This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞.
‡ It is recommended that the PLL clocking option be used for maximum frequency operation.
tr(CI)
tw(CIH)
tc(CI)
tf(CI)
X2/CLKIN
tw(CIL)
tc(CO)
tw(COH)
tf(CO)
tr(CO)
td(CIH-CO)
CLKOUT
Figure 3. External Divide-by-Two Clock Timing
14
POST OFFICE BOX 1443
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tw(COL)
ns
ns
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
multiply-by-N clock option – PLL enabled
The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to generate
the internal machine cycle. The selection of the clock mode and the value of N is described in the clock generator
section.
When an external clock source is used, the frequency injected must conform to specifications listed in the timing
requirements table.
switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 2 and
Figure 4, and the recommended operating conditions table)
549-60
PARAMETER
MIN
16.7†
TYP
MAX
UNIT
tc(CO)
td(CIH-CO)
Cycle time, CLKOUT
tf(CO)
tr(CO)
Fall time, CLKOUT
tw(COL)
tw(COH)
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
H–2
ns
tp
Transitory phase, PLL lock-up time
Delay time, X2/CLKIN high/low to CLKOUT high/low
tc(CI)/N
6
ns
2
ns
2
ns
H–2
ns
Rise time, CLKOUT
ns
50*
ms
*Not production tested.
† Tested with N = 3 only.
timing requirements (see Figure 4)
549-60
tc(CI)
Cycle time, X2/CLKIN
MAX
Integer PLL multiplier N (N = 1–15)
MIN
20‡*
PLL multiplier N = x.5
20‡*
100*
PLL multiplier N = x.25, x.75
20‡*
50*
UNIT
200*
ns
tf(CI)
tr(CI)
Fall time, X2/CLKIN
8*
ns
Rise time, X2/CLKIN
8*
ns
tw(CIL)
tw(CIH)
Pulse duration, X2/CLKIN low
5*
ns
Pulse duration, X2/CLKIN high
5*
ns
*Not production tested.
‡ Note that for all values of tc(CI), the minimum tc(CO) period must not be exceeded.
tw(CIL)
tw(CIH)
tc(CI)
tr(CI)
tf(CI)
X2/CLKIN
td(CIH-CO)
tc(CO)
tw(COH)
tw(COL)
tp
CLKOUT
tf(CO)
tr(CO)
Unstable
Figure 4. External Multiply-by-One Clock Timing
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15
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
memory and parallel I/O interface timing
switching characteristics over recommended operating conditions for a memory read
(MSTRB = 0)†‡ (see Figure 5)
549-60
PARAMETER
MIN
MAX
UNIT
td(CLKL-A)
td(CLKH-A)
Delay time, address valid from CLKOUT low§
–1.5*
7
ns
Delay time, address valid from CLKOUT high (transition)¶
–1.5*
6.5
ns
td(CLKL-MSL)
td(CLKL-MSH)
Delay time, MSTRB low from CLKOUT low
–1.5*
6
ns
Delay time, MSTRB high from CLKOUT low
Hold time, address valid after CLKOUT low§
–1.5*
6
ns
–1.5*
7
ns
Hold time, address valid after CLKOUT high¶
–1.5*
6.5
ns
th(CLKL-A)R
th(CLKH-A)R
*Not production tested.
† Address, PS, and DS timings are all included in timings referenced as address.
‡ See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance.
§ In the case of a memory read preceded by a memory read
¶ In the case of a memory read preceded by a memory write
timing requirements for a memory read (MSTRB = 0) [H = 0.5 tc(CO)]†‡ (see Figure 5)
549-60
MIN
MAX
UNIT
ta(A)M
ta(MSTRBL)
Access time, read data access from address valid
2H–10*
ns
Access time, read data access from MSTRB low
2H–10*
ns
tsu(D)R
th(D)R
Setup time, read data before CLKOUT low
th(A-D)R
Hold time, read data after address invalid
Hold time, read data after CLKOUT low
th(D)MSTRBH Hold time, read data after MSTRB high
*Not production tested.
† Address, PS, and DS timings are all included in timings referenced as address.
‡ See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance.
16
POST OFFICE BOX 1443
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5
ns
2
ns
1*
ns
0*
ns
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
memory and parallel I/O interface timing (continued)
CLKOUT
td(CLKL-A)
th(CLKL-A)R
A[15:0]
th(A-D)R
tsu(D)R
ta(A)M
th(D)R
D[15:0]
th(D)MSTRBH
td(CLKL-MSL)
td(CLKL-MSH)
ta(MSTRBL)
MSTRB
R/W
PS, DS
Figure 5. Memory Read (MSTRB = 0)
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17
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
memory and parallel I/O interface timing (continued)
switching characteristics over recommended operating conditions for a memory write
(MSTRB = 0) [H = 0.5 tc(CO)]†‡ (see Figure 6)
549-60
PARAMETER
MIN
MAX
UNIT
td(CLKH-A)
td(CLKL-A)
Delay time, address valid from CLKOUT high§
Delay time, address valid from CLKOUT low¶
–1.5*
6.5
ns
–1.5*
7
ns
td(CLKL-MSL)
td(CLKL-D)W
Delay time, MSTRB low from CLKOUT low
–1.5*
6
ns
td(CLKL-MSH)
td(CLKH-RWL)
Delay time, MSTRB high from CLKOUT low
td(CLKH-RWH)
td(RWL-MSTRBL)
Delay time, R/W high from CLKOUT high
th(A)W
Hold time, address valid after CLKOUT high§
th(D)MSH
tw(SL)MS
Hold time, write data valid after MSTRB high
Pulse duration, MSTRB low
2H–5*
ns
tsu(A)W
tsu(D)MSH
Setup time, address valid before MSTRB low
2H–5*
ns
Setup time, write data valid before MSTRB high
2H–10 2H+8*§
ns
Delay time, data valid from CLKOUT low
Delay time, R/W low from CLKOUT high
Delay time, MSTRB low after R/W low
POST OFFICE BOX 1443
9
ns
6
ns
–1*
6
ns
–1*
5.5
ns
H – 4*
H + 3*
ns
–1.5*
7*
ns
H+5*¶
ns
H–5*
*Not production tested.
† Address, PS, and DS timings are all included in timings referenced as address.
‡ See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance.
§ In the case of a memory write preceded by a memory write.
¶ In the case of a memory write preceded by an I/O cycle.
18
0*
–1.5*
• HOUSTON, TEXAS 77251–1443
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
memory and parallel I/O interface timing (continued)
CLKOUT
td(CLKH-A)
td(CLKL-A)
th(A)W
A[15:0]
td(CLKL-D)W
th(D)MSH
tsu(D)MSH
D[15:0]
td(CLKL-MSL)
td(CLKL-MSH)
tsu(A)W
MSTRB
td(CLKH-RWL)
td(CLKH-RWH)
tw(SL)MS
td(RWL-MSTRBL)
R/W
PS, DS
Figure 6. Memory Write (MSTRB = 0)
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19
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
memory and parallel I/O interface timing (continued)
switching characteristics over recommended operating conditions for a parallel I/O port read
(IOSTRB = 0)†‡ (see Figure 7)
549-60
PARAMETER
MIN
MAX
UNIT
td(CLKL-A)
td(CLKH-ISTRBL)
Delay time, address valid from CLKOUT low
–1.5*
7
ns
Delay time, IOSTRB low from CLKOUT high
–0.5*
6
ns
td(CLKH-ISTRBH)
th(A)IOR
Delay time, IOSTRB high from CLKOUT high
–1*
6
ns
–1.5*
7*
ns
Hold time, address after CLKOUT low
*Not production tested.
† Address and IS timings are included in timings referenced as address.
‡ See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance.
timing requirements for a parallel I/O port read (IOSTRB = 0) [H = 0.5 tc(CO)]†‡ (see Figure 7)
549-60
MIN
MAX
UNIT
ta(A)IO
ta(ISTRBL)IO
Access time, read data access from address valid
tsu(D)IOR
th(D)IOR
Setup time, read data before CLKOUT high
5*
ns
Hold time, read data after CLKOUT high
2*
ns
0*
ns
Access time, read data access from IOSTRB low
th(ISTRBH-D)R
Hold time, read data after IOSTRB high
*Not production tested.
† Address and IS timings are included in timings referenced as address.
‡ See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance.
CLKOUT
th(A)IOR
td(CLKL-A)
A[15:0]
tsu(D)IOR
ta(A)IO
th(D)IOR
D[15:0]
th(ISTRBH-D)R
td(CLKH-ISTRBH)
ta(ISTRBL)IO
td(CLKH-ISTRBL)
IOSTRB
R/W
IS
Figure 7. Parallel I/O Port Read (IOSTRB = 0)
20
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
3H–10*
ns
2H–10*
ns
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
memory and parallel I/O interface timing (continued)
switching characteristics over recommended operating conditions for a parallel I/O port write
(IOSTRB = 0) [H = 0.5 tc(CO)] (see Figure 8)†
549-60
PARAMETER
UNIT
MIN
MAX
7
ns
td(CLKL-A)
td(CLKH-ISTRBL)
Delay time, address valid from CLKOUT low‡
–1.5*
Delay time, IOSTRB low from CLKOUT high
–0.5*
6
ns
td(CLKH-D)IOW
td(CLKH-ISTRBH)
Delay time, write data valid from CLKOUT high
H–5*
H+8.5
ns
td(CLKL-RWL)
td(CLKL-RWH)
Delay time, R/W low from CLKOUT low
th(A)IOW
Delay time, IOSTRB high from CLKOUT high
–1*
6
ns
–0.5*
6
ns
–1*
6
ns
Hold time, address valid from CLKOUT low‡
–1.5*
7*
ns
th(D)IOW
Hold time, write data after IOSTRB high
H–5*
H+5*
ns
tsu(D)IOSTRBH
Setup time, write data before IOSTRB high
H–5*
H+2*
ns
H–5*
H+5*
ns
Delay time, R/W high from CLKOUT low
tsu(A)IOSTRBL
Setup time, address valid before IOSTRB low
*Not production tested.
† See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance.
‡ Address and IS timings are included in timings referenced as address.
CLKOUT
tsu(A)IOSTRBL
td(CLKL-A)
th(A)IOW
A[15:0]
td(CLKH-D)IOW
th(D)IOW
D[15:0]
td(CLKH-ISTRBL)
td(CLKH-ISTRBH)
tsu(D)IOSTRBH
IOSTRB
td(CLKL-RWH)
td(CLKL-RWL)
R/W
IS
Figure 8. Parallel I/O Port Write (IOSTRB = 0)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
21
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
I/O timing variation with load capacitance: SPICE simulation results
Condition: Temperature
Capacitance
Voltage
Model
: 125° C
: 0–100pF
: 2.7/3.0/3.3 V
: Weak/Nominal/Strong
90%
10%
Figure 9. Rise and Fall Time Diagram
Table 1. Timing Variation With Load Capacitance: [2.7 V] 10% – 90%
WEAK
NOMINAL
STRONG
RISE
FALL
RISE
FALL
RISE
FALL
0 pF
0.476 ns
0.457 ns
0.429 ns
0.391 ns
0.382 ns
0.323 ns
10 pF
1.511 ns
1.278 ns
1.386 ns
1.148 ns
1.215 ns
1.049 ns
20 pF
2.551 ns
2.133 ns
2.350 ns
1.956 ns
2.074 ns
1.779 ns
30 pF
3.614 ns
3.011 ns
3.327 ns
2.762 ns
2.929 ns
2.512 ns
40 pF
4.664 ns
3.899 ns
4.394 ns
3.566 ns
3.798 ns
3.264 ns
50 pF
5.752 ns
4.786 ns
5.273 ns
4.395 ns
4.655 ns
4.010 ns
60 pF
6.789 ns
5.656 ns
6.273 ns
5.206 ns
5.515 ns
4.750 ns
70 pF
7.817 ns
6.598 ns
7.241 ns
6.000 ns
6.442 ns
5.487 ns
80 pF
8.897 ns
7.531 ns
8.278 ns
6.928 ns
7.262 ns
6.317 ns
90 pF
10.021 ns
8.332 ns
9.152 ns
7.735 ns
8.130 ns
7.066 ns
100 pF
11.072 ns
9.299 ns
10.208 ns
8.537 ns
8.997 ns
7.754 ns
Table 2. Timing Variation With Load Capacitance: [3 V] 10% – 90%
WEAK
22
NOMINAL
STRONG
RISE
FALL
RISE
FALL
RISE
FALL
0 pF
0.436 ns
0.387 ns
0.398 ns
0.350 ns
0.345 ns
0.290 ns
10 pF
1.349 ns
1.185 ns
1.240 ns
1.064 ns
1.092 ns
0.964 ns
20 pF
2.273 ns
1.966 ns
2.098 ns
1.794 ns
1.861 ns
1.634 ns
30 pF
3.226 ns
2.765 ns
2.974 ns
2.539 ns
2.637 ns
2.324 ns
40 pF
4.168 ns
3.573 ns
3.849 ns
3.292 ns
3.406 ns
3.013 ns
50 pF
5.110 ns
4.377 ns
4.732 ns
4.052 ns
4.194 ns
3.710 ns
60 pF
6.033 ns
5.230 ns
5.660 ns
4.811 ns
5.005 ns
4.401 ns
70 pF
7.077 ns
5.997 ns
6.524 ns
5.601 ns
5.746 ns
5.117 ns
80 pF
8.020 ns
6.899 ns
7.416 ns
6.336 ns
6.559 ns
5.861 ns
90 pF
8.917 ns
7.709 ns
8.218 ns
7.124 ns
7.323 ns
6.498 ns
100 pF
9.885 ns
8.541 ns
9.141 ns
7.830 ns
8.101 ns
7.238 ns
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
I/O timing variation with load capacitance: SPICE simulation results (continued)
Table 3. Timing Variation With Load Capacitance: [3.3 V] 10% – 90%
WEAK
NOMINAL
STRONG
RISE
FALL
RISE
FALL
RISE
FALL
0 pF
0.404 ns
0.361 ns
0.371 ns
0.310 ns
0.321 ns
0.284 ns
10 pF
1.227 ns
1.081 ns
1.133 ns
1.001 ns
1.000 ns
0.892 ns
20 pF
2.070 ns
1.822 ns
1.915 ns
1.675 ns
1.704 ns
1.530 ns
30 pF
2.931 ns
2.567 ns
2.719 ns
2.367 ns
2.414 ns
2.169 ns
40 pF
3.777 ns
3.322 ns
3.515 ns
3.072 ns
3.120 ns
2.823 ns
50 pF
4.646 ns
4.091 ns
4.319 ns
3.779 ns
3.842 ns
3.466 ns
60 pF
5.487 ns
4.859 ns
5.145 ns
4.503 ns
4.571 ns
4.142 ns
70 pF
6.405 ns
5.608 ns
5.980 ns
5.234 ns
5.301 ns
4.767 ns
80 pF
7.284 ns
6.463 ns
6.723 ns
5.873 ns
5.941 ns
5.446 ns
90 pF
8.159 ns
7.097 ns
7.560 ns
6.692 ns
6.740 ns
6.146 ns
100 pF
8.994 ns
7.935 ns
8.300 ns
7.307 ns
7.431 ns
6.822 ns
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
23
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
ready timing for externally generated wait states
timing requirements for externally generated wait states [H = 0.5 tc(CO)]† (see Figure 10, Figure 11,
Figure 12, and Figure 13)
549-60
MIN
tsu(RDY)
th(RDY)
tv(RDY)MSTRB
th(RDY)MSTRB
tv(RDY)IOSTRB
th(RDY)IOSTRB
tv(MSCL)
tv(MSCH)
MAX
UNIT
Setup time, READY before CLKOUT low
7
ns
Hold time, READY after CLKOUT low
Valid time, READY after MSTRB low‡
2
Hold time, READY after MSTRB low‡
Valid time, READY after IOSTRB low‡
4H+1*
Hold time, READY after IOSTRB low‡
5H*
Valid time, MSC low after CLKOUT low
–1*
6
ns
Valid time, MSC high after CLKOUT low
–1*
6
ns
ns
4H–10*
ns
ns
5H–10*
ns
ns
*Not production tested.
† The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by
READY, at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
‡ These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
CLKOUT
A[15:0]
tsu(RDY)
th(RDY)
READY
tv(RDY)MSTRB
th(RDY)MSTRB
MSTRB
tv(MSCH)
tv(MSCL)
MSC
Wait States
Generated Internally
Wait State
Generated
by READY
Figure 10. Memory Read With Externally Generated Wait States
24
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
ready timing for externally generated wait states (continued)
CLKOUT
A[15:0]
D[15:0]
th(RDY)
tsu(RDY)
READY
tv(RDY)MSTRB
th(RDY)MSTRB
MSTRB
tv(MSCH)
tv(MSCL)
MSC
Wait States
Generated Internally
Wait State Generated
by READY
Figure 11. Memory Write With Externally Generated Wait States
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
25
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
ready timing for externally generated wait states (continued)
CLKOUT
A[15:0]
th(RDY)
tsu(RDY)
READY
tv(RDY)IOSTRB
th(RDY)IOSTRB
IOSTRB
tv(MSCH)
tv(MSCL)
MSC
Wait
States
Generated
Internally
Figure 12. I/O Read With Externally Generated Wait States
26
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
Wait State Generated
by READY
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
ready timing for externally generated wait states (continued)
CLKOUT
A[15:0]
D[15:0]
th(RDY)
tsu(RDY)
READY
tv(RDY)IOSTRB
th(RDY)IOSTRB
IOSTRB
tv(MSCH)
tv(MSCL)
MSC
Wait States
Generated
Internally
Wait State Generated
by READY
Figure 13. I/O Write With Externally Generated Wait States
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
27
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
HOLD and HOLDA timings
switching characteristics over recommended operating conditions for memory control signals
and HOLDA [H = 0.5 tc(CO)] (see Figure 14)
549-60
PARAMETER
MIN
MAX
UNIT
tdis(CLKL-A)
tdis(CLKL-RW)
Disable time, CLKOUT low to address, PS, DS, IS high impedance
5*
ns
Disable time, CLKOUT low to R/W high impedance
5*
ns
tdis(CLKL-S)
ten(CLKL-A)
Disable time, CLKOUT low to MSTRB, IOSTRB high impedance
5*
ns
Enable time, CLKOUT low to address, PS, DS, IS
2H+5*
ns
ten(CLKL-RW)
ten(CLKL-S)
Enable time, CLKOUT low to R/W enabled
2H+5*
ns
Enable time, CLKOUT low to MSTRB, IOSTRB enabled
2H+5*
ns
tv(HOLDA)
Valid time, HOLDA low after CLKOUT low
0*
5*
ns
Valid time, HOLDA high after CLKOUT low
0*
5*
ns
tw(HOLDA)
Pulse duration, HOLDA low duration
*Not production tested.
2H–3*
ns
timing requirements for HOLD [H = 0.5 tc(CO)] (see Figure 14)
549-60
MIN
tw(HOLD)
tsu(HOLD)
Pulse duration, HOLD low duration
Setup time, HOLD before CLKOUT low
*Not production tested.
28
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
MAX
UNIT
4H+10*
ns
10*
ns
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
HOLD and HOLDA timings (continued)
CLKOUT
tsu(HOLD)
tsu(HOLD)
tw(HOLD)
HOLD
tv(HOLDA)
tv(HOLDA)
tw(HOLDA)
HOLDA
tdis(CLKL-A)
ten(CLKL-A)
A[15:0]
PS, DS, IS
D[15:0]
tdis(CLKL-RW)
ten(CLKL-RW)
tdis(CLKL-S)
ten(CLKL-S)
tdis(CLKL-S)
ten(CLKL-S)
R/W
MSTRB
IOSTRB
Figure 14. HOLD and HOLDA Timing (HM = 1)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
29
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
reset, BIO, interrupt, and MP/MC timings
timing requirements for reset, interrupt, BIO, and MP/MC [H = 0.5 tc(CO)] (see Figure 15, Figure 16,
and Figure 17)
549-60
MIN
MAX
UNIT
th(RS)
th(BIO)
Hold time, RS after CLKOUT low
0*
ns
Hold time, BIO after CLKOUT low
0
ns
th(INT)
th(MPMC)
Hold time, INTn, NMI, after CLKOUT low†
0
ns
0*
ns
tw(RSL)
tw(BIO)S
Hold time, MP/MC after CLKOUT low
Pulse duration, RS lowद
4H+10*
ns
Pulse duration, BIO low, synchronous
2H+10*
ns
4H*
ns
tw(BIO)A
tw(INTH)S
Pulse duration, BIO low, asynchronous
Pulse duration, INTn, NMI high (synchronous)
2H+10*
ns
tw(INTH)A
tw(INTL)S
Pulse duration, INTn, NMI high (asynchronous)
4H*
ns
Pulse duration, INTn, NMI low (synchronous)
2H+10*
ns
tw(INTL)A
tw(INTL)WKP
Pulse duration, INTn, NMI low (asynchronous)
4H*
ns
Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup
Setup time, RS before X2/CLKIN low§
10*
ns
tsu(RS)
tsu(BIO)
tsu(INT)
tsu(MPMC)
Setup time, BIO before CLKOUT low
Setup time, INTn, NMI, RS before CLKOUT low
Setup time, MP/MC before CLKOUT low
5*
ns
10
2H*
ns
10
2H*
ns
10*
ns
*Not production tested.
† The external interrupts (INT0–INT3, NMI) are synchronized to the core CPU by way of a two flip-flop synchronizer which samples these inputs
with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1–0–0 sequence at the timing that is
corresponding to three CLKOUTs sampling sequence.
‡ If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 µs to ensure
synchronization and lock-in of the PLL.
§ Divide-by-two mode
¶ Note that RS may cause a change in clock frequency, therefore changing the value of H (see the PLL section).
30
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
reset, BIO, interrupt, and MP/MC timings (continued)
X2/CLKIN
tsu(RS)
tw(RSL)
RS, INTn, NMI
tsu(INT)
th(RS)
CLKOUT
tsu(BIO)
th(BIO)
BIO
tw(BIO)S
Figure 15. Reset and BIO Timings
CLKOUT
tsu(INT)
tsu(INT)
th(INT)
INTn, NMI
tw(INTH)A
tw(INTL)A
Figure 16. Interrupt Timing
CLKOUT
RS
th(MPMC)
tsu(MPMC)
MP/MC
Figure 17. MP/MC Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
31
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
instruction acquisition (IAQ), interrupt acknowledge (IACK), external flag (XF), and TOUT timings
switching characteristics over recommended operating conditions for IAQ and IACK
[H = 0.5 tc(CO)] (see Figure 18)
549-60
PARAMETER
UNIT
MIN
MAX
5
ns
td(CLKL-IAQL)
td(CLKL-IAQH)
Delay time, IAQ low from CLKOUT low
–1*
Delay time, IAQ high from CLKOUT low
–1*
td(A)IAQ
td(CLKL-IACKL)
Delay time, address valid before IAQ low
Delay time, IACK low from CLKOUT low
td(CLKL-IACKH)
td(A)IACK
Delay time , IACK high from CLKOUT low
th(A)IAQ
th(A)IACK
Hold time, address valid after IAQ high
–3*
ns
Hold time, address valid after IACK high
–5*
ns
tw(IAQL)
tw(IACKL)
Pulse duration, IAQ low
2H–3*
ns
Pulse duration, IACK low
2H–3*
ns
5
ns
4*
ns
–0.5*
7
ns
–0.5*
7
ns
5*
ns
Delay time, address valid before IACK low
*Not production tested.
CLKOUT
A[15:0]
td(CLKL-IAQH)
td(CLKL-IAQL)
th(A)IAQ
td(A)IAQ
tw(IAQL)
IAQ
td(CLKL-IACKL)
td(CLKL-IACKH)
th(A)IACK
td(A)IACK
tw(IACKL)
IACK
MSTRB
Figure 18. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timing
32
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
instruction acquisition (IAQ), interrupt acknowledge (IACK), external flag (XF), and TOUT timings
(continued)
switching characteristics over recommended operating conditions for external flag (XF) and TOUT
[H = 0.5 tc(CO)] (see Figure 19 and Figure 20)
549-60
PARAMETER
td(XF)
td(TOUTH)
td(TOUTL)
UNIT
MIN
MAX
Delay time, XF high after CLKOUT low
–1*
6
Delay time, XF low after CLKOUT low
–1*
6
Delay time, TOUT high after CLKOUT low
–1*
6
ns
–1*
5
ns
Delay time, TOUT low after CLKOUT low
tw(TOUT)
Pulse duration, TOUT
*Not production tested.
2H–3*
ns
ns
CLKOUT
td(XF)
XF
Figure 19. External Flag (XF) Timing
CLKOUT
td(TOUTH)
td(TOUTL)
TOUT
tw(TOUT)
Figure 20. TOUT Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
33
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
serial port receive timing
timing requirements for serial port receive [H = 0.5 tc(CO)] (see Figure 21)
549-60
UNIT
MIN
MAX
6H*
†
ns
tc(SCK)
tf(SCK)
Cycle time, serial port clock
Fall time, serial port clock
6*
ns
tr(SCK)
tw(SCK)
Rise time, serial port clock
6*
ns
tsu(FSR)
th(FSR)
Setup time, TFSR/TADD before TCLKR falling edge
th(DR)
Hold time, TDR after TCLKR falling edge
Pulse duration, serial port clock low/high
Hold time, TFSR/TADD after TCLKR falling edge
tsu(DR)
Setup time, TDR before TCLKR falling edge
*Not production tested.
† The serial port design is fully static and, therefore, can operate with tc(SCK) approaching ∞.
tc(SCK)
3H*
ns
6
ns
6*
ns
6
ns
6
ns
tf(SCK)
tw(SCK)
TCLKR
th(FSR)
tw(SCK)
tr(SCK)
tsu(FSR)
tsu(DR)
TFSR/TADD
th(DR)
TDR
Bit
1
2
Figure 21. Serial Port Receive Timing
34
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
7/15
8/16
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
serial port transmit timing
switching characteristics over recommended operating conditions for serial port transmit with
external clocks and frames (see Figure 22)
549-60
PARAMETER
td(DX)
th(DX)
MIN
MAX
Delay time, TDX valid after TCLKX rising
25
Hold time, TDX valid after TCLKX rising
–5*
UNIT
ns
ns
tdis(DX)
Disable time, TDX after TCLKX rising
*Not production tested.
40*
ns
timing requirements for serial port transmit with external clocks and frames [H = 0.5tc(CO)]
(see Figure 22)
549-60
MIN
tc(SCK)
td(FSX)
Cycle time, serial port clock
th(FSX)
th(FSX)H
Hold time, TFSX/TFRM after TCLKX falling edge (see Note 1)
tf(SCK)
tr(SCK)
MAX
†
6H*
Delay time, TFSX/TFRM after TCLKX rising edge
2H–5
6*
UNIT
ns
ns
ns
2H–5*‡
ns
Fall time, serial port clock
6*
ns
Rise time, serial port clock
6*
ns
Hold time, TFSX/TFRM after TCLKX rising edge (see Note 1)
tw(SCK)
Pulse duration, serial port clock low/high
3H*
ns
*Not production tested.
† The serial port design is fully static and, therefore, can operate with tc(SCK) approaching ∞.
‡ If the TFSX/TFRM pulse does not meet this specification, the first bit of serial data is driven on TDX until the falling edge of TFSX/TFRM. After
the falling edge of TFSX/TFRM, data is shifted out on TDX pin. The transmit buffer-empty interrupt is generated when the th(FSX) and th(FSX)H
specification is met.
NOTE 1: Internal clock with external TFSX/TFRM and vice versa are also allowable. However, TFSX/TFRM timings to TCLKX always are defined
depending on the source of TFSX/TFRM, and CLKX timings always are dependent upon the source of CLKX. Specifically, the
relationship of TFSX/TFRM to TCLKX is independent of the source of TCLKX.
tc(SCK)
tf(SCK)
tw(SCK)
TCLKX
td(FSX)
th(FSX)H
tw(SCK)
th(FSX)
tr(SCK)
TFSX/TFRM
td(DX)
tdis(DX)
th(DX)
TDX Bit
1
2
7/15
8/16
Figure 22. Serial Port Transmit Timing With External Clocks and Frames
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
35
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
serial port transmit timing (continued)
switching characteristics over recommended operating conditions for serial port transmit with
internal clocks and frames [H = 0.5tc(CO)] (see Figure 23)
549-60
PARAMETER
MIN
TYP
MAX
8H
UNIT
tc(SCK)
td(FSX)
Cycle time, serial port clock
Delay time, TCLKX rising to TFSX/TFRM
15
ns
td(DX)
tdis(DX)
Delay time, TCLKX rising to TDX
15
ns
20*
ns
th(DX)
tf(SCK)
Hold time, TDX valid after TCLKX rising edge
tr(SCK)
tw(SCK)
Rise time, serial port clock
Disable time, TCLKX rising to TDX
– 5*
ns
Fall time, serial port clock
Pulse duration, serial port clock low/high
4
ns
4
ns
4H–8*
ns
*Not production tested.
tc(SCK)
tf(SCK)
tw(SCK)
TCLKX
td(FSX)
tw(SCK)
tr(SCK)
td(FSX)
td(DX)
TFSX/TFRM
tdis(DX)
th(DX)
TDX
1
2
7/15
8/16
Figure 23. Serial Port Transmit Timing With Internal Clocks and Frames
36
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
ns
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
buffered serial port receive timing
timing requirements (see Figure 24)
549-60
MIN
UNIT
MAX
†
tc(SCK)
tf(SCK)
Cycle time, serial port clock
Fall time, serial port clock
20*
4*
ns
tr(SCK)
tw(SCK)
Rise time, serial port clock
4*
ns
tsu(BFSR)
th(BFSR)
Setup time, BFSR before BCLKR falling edge (see Note 2)
tsu(BDR)
th(BDR)
Setup time, BDR before BCLKR falling edge
Pulse duration, serial port clock low/high
ns
6*
ns
2
Hold time, BFSR after BCLKR falling edge (see Note 2)
7*
ns
tc(SCK)–2*‡
ns
0.5*
ns
7*
ns
Hold time, BDR after BCLKR falling edge
*Not production tested.
† The serial port design is fully static and therefore can operate with tc(SCK) approaching infinity.
‡ First bit is read when BFSR is sampled low by BCLKR clock.
NOTE 2: Timings for BCLKR and BFSR are given with polarity bits (BCLKP and BFSP) set to 0.
tc(SCK)
tw(SCK)
tf(SCK)
BCLKR
th(BFSR)
tr(SCK)
tw(SCK)
tsu(BFSR)
tsu(BDR)
BFSR
th(BDR)
BDR
1
2
8/10/12/16
Figure 24. Buffered Serial Port Receive Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
37
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
buffered serial port transmit timing of external frames
switching characteristics over recommended operating conditions (see Figure 25)
549-60
PARAMETER
MIN
td(BDX)
tdis(BDX)
Delay time, BDX valid after BCLKX rising
tdis(BDX)pcm
ten(BDX)pcm
Disable time, PCM mode, BDX after BCLKX rising
Disable time, BDX after BCLKX rising
MAX
18*
ns
6*
ns
6*
ns
4*
Enable time, PCM mode, BDX after BCLKX rising
th(BDX)
Hold time, BDX valid after BCLKX rising
*Not production tested.
UNIT
8*
ns
2*
ns
timing requirements (see Figure 25)
549-60
MIN
MAX
†
tc(SCK)
tf(SCK)
Cycle time, serial port clock
Fall time, serial port clock
4*
ns
tr(SCK)
tw(SCK)
Rise time, serial port clock
4*
ns
th(BFSX)
tsu(BFSX)
20*
UNIT
Pulse duration, serial port clock low/high
6*
Hold time, BFSX after BCLKX falling edge (see Notes 3 and 4)
6*
Setup time, BFSX before BCLKX falling edge (see Notes 3 and 4)
6*
ns
ns
tc(SCK)–6*‡
ns
ns
*Not production tested.
† The serial port design is fully static and therefore can operate with tc(SCK) approaching infinity.
‡ If BFSX does not meet this specification, the first bit of the serial data is driven on BDX until BFSX goes low (sampled on falling edge of BCLKX).
After falling edge of the BFSX, data is shifted out on the BDX pin.
NOTES: 3. Internal clock with external BFSX and vice versa are also allowable. However, BFSX timings to BCLKX always are defined
depending on the source of BFSX, and BCLKX timings always are dependent upon the source of BCLKX.
4. Timings for BCLKX and BFSX are given with polarity bits (BCLKP and BFSP) set to 0.
tc(SCK)
tw(SCK)
tf(SCK)
BCLKX
tr(SCK)
th(BFSX)
tw(SCK)
tsu(BFSX)
BFSX
th(BDX)
td(BDX)
tdis(BDX)
BDX
1
2
8/10/12/16
Figure 25. Buffered Serial Port Transmit Timing of External Clocks and External Frames
38
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
buffered serial port transmit timing of internal frame and internal clock
switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 26)
549-60
PARAMETER
MIN
MAX
UNIT
tc(SCK)
td(BFSX)
Cycle time, serial port clock, internal clock
td(BDX)
tdis(BDX)
Delay time, BDX valid after BCLKX rising edge
tdis(BDX)pcm
ten(BDX)pcm
Disable time, PCM mode, BDX after BCLKX rising edge
th(BDX)
tf(SCK)
Hold time, BDX valid after BCLKX rising edge
Fall time, serial port clock
3.5*
ns
tr(SCK)
tw(SCK)
Rise time, serial port clock
3.5*
ns
Delay time, BFSX after BCLKX rising edge (see Notes 3 and 4)
0*
Disable time, BDX after BCLKX rising edge
62H*
ns
10*
ns
11*
ns
5*
ns
5*
ns
0*
Enable time, PCM mode, BDX after BCLKX rising edge
7*
ns
–3*
ns
Pulse duration, serial port clock low/high
6*
ns
*Not production tested.
NOTES: 3. Internal clock with external BFSX and vice versa are also allowable. However, BFSX timings to BCLKX always are defined
depending on the source of BFSX, and BCLKX timings always are dependent upon the source of BCLKX.
4. Timings for BCLKX and BFSX are given with polarity bits (BCLKP and BFSP) set to 0.
tc(SCK)
tw(SCK)
tf(SCK)
BCLKX
tr(SCK)
td(BFSX)
tw(SCK)
td(BFSX)
BFSX
th(BDX)
td(BDX)
tdis(BDX)
BDX
1
2
8/10/12/16
Figure 26. Buffered Serial Port Transmit Timing of Internal Clocks and Internal Frames
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
39
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
serial-port receive timing in TDM mode
timing requirements [H = 0.5tc(CO)] (see Figure 27)
549-60
MIN
MAX
†
16H*
UNIT
tc(SCK)
tf(SCK)
Cycle time, serial-port clock
Fall time, serial-port clock
6*
ns
ns
tr(SCK)
tw(SCK)
Rise time, serial-port clock
6*
ns
Pulse duration, serial-port clock low/high
8H*
ns
tsu(TD-TCH)
th(TCH-TD)
Setup time, TDR/TADD before TCLK rising edge
10*
ns
Hold time, TDR/TADD after TCLK rising edge
2*
ns
tsu(TF-TCH)
th(TCH-TF)
Setup time, TFRM before TCLK rising edge‡
10*
ns
Hold time, TFRM after TCLK rising edge‡
10*
ns
*Not production tested.
† The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching infinity.
‡ TFRM timing and waveforms shown in Figure 27 are for external TFRM. TFRM can also be configured as internal. The TFRM internal case is
illustrated in the transmit timing diagram in Figure 28.
tw(SCK)
tf(SCK)
tw(SCK)
TCLK
tc(SCK)
tr(SCK)
tsu(TD-TCH)
th(TCH-TD)
TDR
B0
B15
B14
B13
B12
B11
A0
A1
A2
A3
A4
B2
tsu(TF-TCH)
TADD
th(TCH-TF)
TFRM
Figure 27. Serial-Port Receive Timing in TDM Mode
40
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
A7
B1
B0
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
serial-port transmit timing in TDM mode
switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 28)
549-60
PARAMETER
th(TCH-TDV)
th(TCH-TDV)
td(TCH-TFV)
td(TC-TDV)
d(TC TDV)
MIN
MAX
Hold time, TDX/TADD valid after TCLK rising edge, TCLK external
–3.5*
Hold time, TDX/TADD valid after TCLK rising edge, TCLK internal
Delay time, TFRM valid after TCLK rising edge TCLK ext†
0.5*
H – 3*
3H + 22*
Delay time, TFRM valid after TCLK rising edge, TCLK int†
H – 3*
3H + 12*
UNIT
ns
ns
Delay time, TCLK to valid TDX/TADD, TCLK ext
25*
Delay time, TCLK to valid TDX/TADD, TCLK int
18*
ns
ns
*Not production tested.
† TFRM timing and waveforms shown in Figure 28 are for internal TFRM. TFRM can also be configured as external. The TFRM external case is
illustrated in the receive timing diagram in Figure 27.
timing requirements [H = 0.5tc(CO)] (see Figure 28)
549-60
tc(SCK)
tf(SCK)
Cycle time, serial-port clock
tr(SCK)
tw(SCK)
Rise time, serial-port clock
MIN
16H*‡
MAX
§
Fall time, serial-port clock
ns
6*
ns
6*
ns
8H*‡
Pulse duration, serial-port clock low/high
UNIT
ns
*Not production tested.
‡ When SCK is generated internally, this value is typical.
§ The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching 1.
tw(SCK)
tw(SCK)
tf(SCK)
TCLK
tc(SCK)
td(TC-TDV)
tr(SCK)
B15
TDX
B0
th(TCH-TDV)
B14
td(TCH-TFV)
B12
B8
A2
A3
A7
B7
B2
B1
B0
th(TCH-TDV)
td(TC-TDV)
A1
TADD
B13
A0
td(TCH-TFV)
TFRM
Figure 28. Serial-Port Transmit Timing in TDM Mode
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
41
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
host-port interface timing
switching characteristics over recommended operating
(see Notes 5 and 6) (see Figure 29 through Figure 32)
conditions
[H
=
0.5tc(CO)]
549-60
PARAMETER
td(DSL-HDV)
Delay time, DS low to HD driven
MIN
MAX
5*
12*
Case 1: Shared-access mode if
tw(DSH) < 7H
td(HEL-HDV1)
UNIT
ns
7H+20–tw(DSH)*
Case 2: Shared-access mode if
Delay time, HDS falling to HD valid for first byte tw(DSH) > 7H
of a non-subsequent read: → max 20 ns†‡
Case 3: Host-only mode if
tw(DSH) < 20 ns
20*
ns
40–tw(DSH)*
Case 4: Host-only mode if
tw(DSH) > 20 ns
20*
5*‡
td(DSL-HDV2)
td(DSH-HYH)
Delay time, DS low to HD valid, second byte
tsu(HDV-HYH)
th(DSH-HDV)R
Setup time, HD valid before HRDY rising edge
3H–10*
Hold time, HD valid after DS rising edge, read
0*
td(COH-HYH)
td(DSH-HYL)
Delay time, DS high to HRDY high
20*
10H+10*
ns
ns
ns
14
ns
Delay time, CLKOUT rising edge to HRDY high
10*
ns
Delay time, HDS or HCS high to HRDY low
12*
ns
td(COH-HTX)
Delay time, CLKOUT rising edge to HINT change
15*
ns
*Not production tested.
† Host-only mode timings apply for read accesses to HPIC or HPIA, write accesses to BOB, and resetting DSPINT or HINT to 0 in shared-access
mode. HRDY does not go low for these accesses.
‡ Shared-access mode timings are met automatically if HRDY is used.
NOTES: 5. SAM = shared-access mode, HOM = host-only mode
HAD stands for HCNTRL0, HCNTRL1, and HR/W.
HDS refers to either HDS1 or HDS2.
DS refers to the logical OR of HCS and HDS.
6. On host read accesses to the HPI, the setup time of HD before DS rising edge depends on the host waveforms and cannot be
specified here.
42
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
host-port interface timing (continued)
timing requirements [H = 0.5tc(CO)] (see Note 5, Figure 29 through Figure 32)
549-60
MIN
tsu(HBV-DSL)
th(DSL-HBV)
Setup time, HAD/HBIL valid before DS or HAS falling edge
tsu(HSL-DSL)
tw(DSL)
Setup time, HAS low before DS falling edge
tw(DSH)
tc(DSH-DSH)†
tsu(HDV-DSH)
td(DSH-HSL)‡
MAX
UNIT
10*
ns
5*
ns
ns
Pulse duration, DS low
12*
30*†
Pulse duration, DS high
10*
ns
Hold time, HAD/HBIL valid after DS or HAS falling edge
time DS rising edge to next DS
Cycle time,
rising edge
Case 1: HOM access timings
(see Access Timings Without HRDY)
Case 2a: SAM accesses and HOM active writes
to DSPINT or HINT.
(see Access Timings With HRDY)
Setup time, HD valid before DS rising edge
Delay time, DS high to next HAS low
ns
50*
ns
10H*
12*
ns
10H*
ns
th(DSH – HDV)W
Hold time, HD valid after DS rising edge, write
3.5*
ns
*Not production tested.
† A host not using HRDY should meet the 10H requirement all the time unless a software handshake is used to change the access rate according
to the HPI mode.
‡ Must only be met if HAS is going low when not accessing the HPI (as would be the case where multiple devices are being driven by one host).
NOTE 5: SAM = shared-access mode, HOM = host-only mode
HAD stands for HCNTRL0, HCNTRL1, and HR/W.
HDS refers to either HDS1 or HDS2.
DS refers to the logical OR of HCS and HDS.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
43
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
host-port interface timing (continued)
FIRST BYTE
Valid
HAD
SECOND BYTE
Valid
Valid
th(DSL-HBV)
th(DSL-HBV)
tsu(HBV-DSL)
tsu(HBV-DSL)
HBIL
tw(DSH)
tw(DSH)
tw(DSL)
tw(DSL)
HCS
HDS
tc(DSH-DSH)
td(DSL-HDV2)
td(HEL-HDV1)
th(DSH-HDV)
td(DSL-HDV)
HD
Read
Valid
th(DSH-HDV)R
Valid
tsu(HDV-DSH)
tsu(HDV-DSH)
th(DSH-HDV)W
th(DSH-HDV)
HD
Write
Valid
Valid
Figure 29. Read/Write Access Timings Without HRDY or HAS
44
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
host-port interface timing (continued)
FIRST BYTE
SECOND BYTE
HAS
tsu(HBV-DSL)
Valid
HAD
td(DSH-HSL)
th(DSL-HBV)
tsu(HSL-DSL)
Valid
Valid
th(DSL-HBV)†
tsu(HBV-DSL)†
HBIL
tc(DSH-DSH)
tw(DSH)
tw(DSL)
HCS
HDS
td(HEL-HDV1)
td(DSL-HDV2)
th(DSH-HDV)R
th(DSH-HDV)R
td(DSL-HDV)
HD
Read
Valid
Valid
tsu(HDV-DSH)
tsu(HDV-DSH)
th(DSH-HDV)W
th(DSH-HDV)W
HD
Write
Valid
Valid
† When HAS is tied to VDD
Figure 30. Read/Write Access Timings Using HAS Without HRDY
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
45
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
host-port interface timing (continued)
FIRST BYTE
SECOND BYTE
HAS
tsu(HSL-DSL)
td(DSH-HSL)
tsu(HBV-DSL)
th(DSL-HBV)
HAD
tsu(HBV-DSL)†
th(DSL-HBV)†
HBIL
tw(DSH)
tc(DSH-DSH)
tw(DSL)
HCS
HDS
tsu(HDV-HYH)
td(DSH-HYH)
HRDY
td(DSH-HYL)
td(HEL-HDV1)
td(DSL-HDV2)
th(DSH-HDV)R
td(DSL-HDV)
HD
READ
Valid
th(DSH-HDV)R
Valid
tsu(HDV-DSH)
tsu(HDV-DSH)
th(DSH-HDV)W
th(DSH-HDV)W
HD
WRITE
Valid
Valid
td(COH-HYH)
CLKOUT
td(COH-HTX)
HINT
† When HAS is tied to VDD
Figure 31. Read/Write Access Timing With HRDY
46
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
host-port interface timing (continued)
HCS
td(DSH-HYL)
HRDY
td(DSH-HYH)
HDS
Figure 32. HRDY Signal When HCS is Always Low
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
47
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
MECHANICAL DATA
HFG (S-CQFP-F164)
CERAMIC QUAD FLATPACK WITH NCTB
1.140 (28,96)
SQ
1.120 (28,45)
0.325 (8,26)
Tie Bar Width
0.275 (6,99)
1.000 (25,40)
BSC
”A”
41
1
42
164
Á
Á
Á
Á
1.520 (38,61)
1.480 (37,59)
2.505 (63,63)
2.485 (63,12)
82
124
83
1.150 (29,21)
BSC 8 Places
0.061 (1,55)
DIA 4 Places
0.059 (1,50)
123
Á
Á
Á
Á
”C”
”B”
0.105 (2,67) MAX
0.018 (0,46) MAX
164 X
0.010 (0,25)
0.006 (0,15)
BRAZE
0.040 (1,02)
0.030 (0,76)
0,025 (0,64)
DETAIL ”A”
0.009 (0,23)
0.004 (0,10)
0.020 (0,51) MAX
DETAIL ”B”
0.014 (0,36)
0.002 (0,05)
0.130 (3,30) MAX
DETAIL ”C”
4040231-9/J 01/99
NOTES: A.
B.
C.
D.
E.
F.
G.
48
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Ceramic quad flatpack with flat leads brazed to non-conductive tie bar carrier
This package is hermetically sealed with a metal lid.
The leads are gold-plated and can be solder-dipped.
Leads not shown for clarity purposes
Falls within JEDEC MO-113AA (REV D)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
PACKAGE OPTION ADDENDUM
www.ti.com
4-Apr-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
5962-0251201QXA
ACTIVE
CFP
HFG
164
1
TBD
Call TI
N / A for Pkg Type
SMJ320LC549HFGW60
ACTIVE
CFP
HFG
164
1
TBD
Call TI
N / A for Pkg Type
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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to Customer on an annual basis.
Addendum-Page 1
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