E2E1026-27-Y4 ¡ Semiconductor MSM66101 ¡ Semiconductor This version: MSM66101 Jan. 1998 Previous version: Nov. 1996 OLMS-66K Series 16-Bit Microcontroller GENERAL DESCRIPTION The MSM66101 is a high performance microcontroller that employs OKI original nX-8/100 CPU core. This chip includes a 16-bit CPU, ROM, RAM, I/O ports, multifunction 16-bit timers, 10bit A/D converter, serial I/O port, and pulse width modulator (PWM). FEATURES • 64K address space for program memory • 64K address space for data memory • High-speed execution Minimum cycle for instruction • Powerful instruction set : : Internal ROM : 12K bytes Internal RAM : 384 bytes : : • Abundant addressing modes : 400ns @ 10MHz Instruction set superior in orthogonal matrix 8/16-bit data transfer instructions 8/16-bit arithmetic instructions Multiplication and division operation instructions Bit manipulation instructions Bit logic instrucitons ROM table reference instructions Register addressing Page addressing Pointing register indirect addressing Stack addressing Immediate value addressing • I/O port Input-output port : 5 ports ¥ 8 bits (Each bit can be assigned to input or output) Input port : 1 port ¥ 8 bits • Built-in multifunctional 16-bit timer : 2 Following 4 modes can be set for each timer :Auto-reload timer mode Clock output mode Capture register mode Real time output mode • Serial port : 1 channel (UART mode with baud rate generator) • 12-bit pulse width modulator : 2 • Watchdog timer • Transition detector : 4 • 10-bit A/D converter : 8 channels • Interrupts Nonmaskable : 1 Maskable : Internal 10/external 2 • Stand-by function STOP mode : Software clock stop mode HALT mode : Software CPU stop mode HOLD mode : Hardware CPU stop mode 1/28 ¡ Semiconductor MSM66101 • Package options: 64-pin plastic shrink DIP (SDIP64-P-750-1.78) : (Product name: MSM66101-¥¥¥SS) 64-pin plastic QFP (QFP64-P-1414-0.80-BK) : (Product name: MSM66101-¥¥¥GS-BK) 68-pin plastic QFJ (PLCC) (QFJ68-P-S950-1.27) : (Product name: MSM66101-¥¥¥JS) 64-pin ceramic piggyback (ADIP64-C-750-1.78) : (Product name: MSM66G101VS) * The piggyback type is used only for engineering samples. ¥¥¥ indicates the code number. 2/28 INTERRUPT CONT. PERIPHERAL CONT. NMI P3.2/INT0 P3.3/INT1 RESOUT P2.3/CLKOUT WDT PWM 0,1 A/D CONV. TRANSITION D. SERIAL PORT TIMER 0–1 P4.2/PWM0 P4.3/PWM1 P5.7/AI 7 AGND VREF P5.0/AI 0 P4.7/TRNS3 P4.4/TRNS0 P3.1/RXD P3.0/TXD P3.5/TM1IO P4.0/TM0CK P4.1/TM1CK P3.4/TM0IO CONT. SYSTEM ACC TEMPORARY R. CONSTANTS ALU ALU SSP CONT. PSW INSTRUCTION DEC. LRB PC RAP IR CONT. MEMORY P0 P1 P2 P3 PORT ROM 12K ¥ 8 bits RAM 384 ¥ 8 bits P4 P5 C O N T . P O R T B U S A15/P1.7 A8 /P1.0 AD7/P0.7 AD0/P0.0 WR RD PSEN ALE READY EA ¡ Semiconductor MSM66101 BLOCK DIAGRAM HLDA/P2.5 HOLD/P2.4 FLT RES OSC1 OSC0 GND VDD 3/28 ¡ Semiconductor MSM66101 PIN CONFIGURATION (TOP VIEW) AD0/P0.0 1 64 VDD AD1/P0.1 2 63 VREF AD2/P0.2 3 62 AGND AD3/P0.3 4 61 P5.7/AI7 AD4/P0.4 5 60 P5.6/AI6 AD5/P0.5 6 59 P5.5/AI5 AD6/P0.6 7 58 P5.4/AI4 AD7/P0.7 8 57 P5.3/AI3 A8/P1.0 9 56 P5.2/AI2 A9/P1.1 A10/P1.2 10 11 55 54 P5.1/AI1 P5.0/AI0 A11/P1.3 12 53 P4.7/TRNS3 A12/P1.4 13 52 P4.6/TRNS2 A13/P1.5 14 51 P4.5/TRNS1 A14/P1.6 15 50 P4.4/TRNS0 A15/P1.7 16 49 P4.3/PWM1 P2.0 P2.1 17 18 48 47 P4.2/PWM0 P4.1/TM1CK P2.2 19 46 P4.0/TM0CK CLKOUT/P2.3 20 45 P3.7 RESOUT 21 44 P3.6 ALE 22 43 P3.5/TM1IO PSEN 23 42 P3.4/TM0IO RD 24 41 P3.3/INT1 WR READY 25 26 40 39 P3.2/INT0 P3.1/RXD EA 27 38 P3.0/TXD FLT 28 37 P2.7 RES 29 36 P2.6 OSC0 30 35 P2.5/HLDA OSC1 GND 31 34 32 33 P2.4/HOLD NMI 64-Pin Plastic Shrink DIP 4/28 , ¡ Semiconductor MSM66101 49 P5.3/AI3 50 P5.4/AI4 54 P5.5/AI5 52 P5.6/AI6 53 P5.7/AI7 54 AGND 55 VREF 56 VDD 57 P0.0/AD0 58 P0.1/AD1 59 P0.2/AD2 60 P0.3/AD3 61 P0.4/AD4 62 P0.5/AD5 63 P0.6/AD6 64 P0.7/AD7 PIN CONFIGURATION (TOP VIEW) (Continued) 1 48 P5.2/AI2 2 47 P5.1/AI1 3 46 P5.0/AI0 4 45 P4.7/TRNS3 5 44 P4.6/TRNS2 6 43 P4.5/TRNS1 7 42 P4.4/TRNS0 8 41 P4.3/PWM1 9 40 P4.2/PWM0 P2.1 10 39 P4.1/TM1CK P2.2 11 38 P4.0/TM0CK CLKOUT/P2.3 12 37 P3.7/TM3IO RESOUT 13 36 P3.6/TM2IO ALE 14 35 P3.5/TM1IO PSEN 15 34 P3.4/TM0IO A8/P1.0 A9/P1.1 A10/P1.2 A11/P1.3 A12/P1.4 A13/P1.5 A14/P1.6 A15/P1.7 P2.0 RD 16 RXD/P3.1 31 INT0/P3.2 32 TXD/P3.0 30 RXC/P2.7 29 TXC/P2.6 28 HLDA/P2.5 27 NMI 25 HOLD/P2.4 26 GND 24 OSC1 23 RES 21 OSC0 22 EA 19 FLT 20 WR 17 READY 18 33 P3.3/INT1 64-Pin Plastic QFP 5/28 ¡ Semiconductor MSM66101 44 P3.3/INT1 46 P3.5/TM1IO 45 P3.4/TM0IO 48 P3.7 47 P3.6 50 P4.0/TM0CK 49 NC 52 P4.2/PWM0 51 P4.1/TM1CK 54 P4.4/TRNS0 53 P4.3/PWM1 56 P4.6/TRNS2 55 P4.5/TRNS1 58 P5.0/AI0 57 P4.7/TRNS3 60 P5.2/AI2 59 P5.1/AI1 PIN CONFIGURATION (TOP VIEW) (Continued) AI3/P5.3 61 AI4/P5.4 62 43 P3.2/INT0 42 P3.1/RXD AI5/P5.5 63 AI6/P5.6 64 41 P3.0/TXD 40 P2.7 AI7/P5.7 65 AGND 66 39 P2.6 38 P2.5/HLDA VREF 67 VDD 68 37 P2.4/HOLD 36 NMI 27 WR RD 26 AD7/P0.7 9 ALE 24 PSEN 25 29 EA 28 READY CLKOUT/P2.3 22 RESOUT 23 AD5/P0.5 7 AD6/P0.6 8 P2.1 20 P2.2 21 31 RES 30 FLT NC 18 P2.0 19 AD3/P0.3 5 AD4/P0.4 6 A14/P1.6 16 A15/P1.7 17 33 OSC1 32 OSC0 A12/P1.4 14 A13/P1.5 15 AD1/P0.1 3 AD2/P0.2 4 A10/P1.2 12 A11/P1.3 13 35 GND 34 GND A8/P1.0 10 A9/P1.1 11 VDD 1 AD0/P0.0 2 NC: No-connection pin 68-Pin Plastic QFJ (PLCC) 6/28 ¡ Semiconductor MSM66101 PIN DESCRIPTIONS Symbol Type Description P0.0–P0.7/ AD0–AD7 I/O P0: 8-bit input-output port. Each bit can be assigned to input or output. AD: Outputs the lower 8 bits of program counter during external program memory fetch, and receives the addressed instruction under the control of PSEN. Also outputs the address and outputs or inputs data during an external data memory access instruction under the control of ALE, RD, and WR. P1.0–P1.7/ I/O P1: 8-bit input-output port. Each bit can be assigned to input or output. A: Outputs the upper 8 bits of program counter (PC8–15) during external program memory fetch. Also this pin outputs the upper 8 bits of address during external data memory access instructions. A8–A15 P2.0–P2.2 P2.3/CLKOUT I/O P2: 8-bit input-output port. Each bit can be assigned to input or output. CLKOUT: Output pin for supplying a clock to peripheral circuits. Output frequency range is equal to or twice the system clock. HOLD: Input pin to request the CPU to enter the hardware power-down state. HLDA: HOLD ACKNOWLEDGE: the HLDA signal appears in response to the HOLD signal and indicates that the CPU has entered the power-down state. I/O P3: 8-bit input-output port. Each bit can be assigned to be an input or an output. TXD: Serial port transmitter data output pin. RXD: Serial port receiver data input pin with high impedance. INT: Interrupt Request Input pin. P2.4/HOLD P2.5/HLDA P2.6 P2.7 P3.0/TXD P3.1/RXD P3.2/INT0 P3.3/INT1 P3.4/TM0IO P3.5/TM1IO P3.6 P3.7 TM0IO-TM1IO: One of the following signals is output or input. • Clock at twice the frequency range of the 16-bit timer overflow • Load trigger signal to the capture register input • Setting value output Whether the signal is input or output depends on the mode. P4.0/TM0CK P4.1/TM1CK P4.2/PWM0 P4.3/PWM1 P4.4 – P4.7/ TRANS0 – 3 I/O P5.0 – P5.7/ AI0 –AI7 I P4: 8-bit input-output port. Each bit can be assigned to an input or an output. TM0CK, TM1CK: Clock input pins of timer 0, timer 1. TRANS: The input pins which sense the rising edge and set the flag. PWM: 12-bit pulse-width modulator output pin. P5: 8-bit input port. AI: Analog signal input pin for A/D converter. 7/28 ¡ Semiconductor MSM66101 PIN DESCRIPTIONS (Continued) Symbol Type Description RESOUT O Outputs 'H' level when the CPU is in RESET status. Reset to 'L' level in some programs. ALE O Address Latch Enable: The timing pulse to latch the lower 8 bits of the address output from port 0 when the CPU accesses the external memory. PSEN O Program Store Enable: The strobe pulse to fetch to external program memory. RD O WR O READY I Output strobe activated during a bus read cycle. Used to enable data on to the bus from the external data memory. Output strobe during a bus write cycle. Used as write strobe to external data memory. Used when the CPU accesses low speed peripherals. EA I Normally set to 'H' level. If set to 'L' level, the CPU fetches the code from external program memory. FLT I RES I If FLT is 'H' level, ALE, WR, RD, PSEN are set to 'H' level when reset. If FLT is set to 'L', ALE, WR, RD, PSEN are set to floating level when reset. RESET input pin. OSC0 I OSC1 O NMI I VREF I Reference voltage input pin for A/D converter. AGND I Ground for A/D converter. VDD I System power supply. I Ground. GND Clock oscillation pins Nonmaskable interrupt input pin (falling edge) 8/28 ¡ Semiconductor MSM66101 REGISTERS Accumulator 15 0 ACC Control Register (CR) 15 0 PSW Program Status Word Program Counter PC Local Register Base LRB System Stack Pointer SSP Pointing Register (PR) 15 0 Index Register 1 X1 Index Register 2 X2 Data Pointer DP USP User Stack Pointer Local Register 7 0 7 0 ER0 R1 R0 ER1 R3 R2 ER2 R5 R4 ER3 R7 R6 9/28 ¡ Semiconductor MSM66101 SFR Address (HEX) 0000 0001 0002 0003 0004I 0005I 0006 0007 0010I Name Symbol System stack pointer SSP (ASSP) Local register base LRB (ALRB) Program status word Accumulator Standby control register PSWL (APSW) R/W FFH undefined R/W 00H ACC 00H SBYCON F8H 00H/WDT is stopped WDT W Peripheral control register PRPHF R/W 0013 Stop code acceptor STPACP W 001AI 001BI 8 FDH "0" 08H IRQ 8/16 Interrupt enable register C8H 0CH Watchdog timer Interrupt request register 8/16 PSWH 0012I 0019I Reset FFH 0011 0018I 8/16-bit Operation 0FH 08H IE 0FH 001CI External Iinterrupt control register EXICON FCH 0020 Port 0 data register P0 undefined 0021 Port 0 mode register P0IO 00H 0022 Port 1 data register P1 undefined 0023 Port 1 mode register P1IO 0024 Port 2 data register P2 0025 Port 2 mode register P2IO 0026I Port 2 secondary function control register P2SF C7H 0028 Port 3 data register P3 undefined 0029 Port 3 mode register P3IO 00H 002AI Port 3 secondary function control register P3SF C0H 002C Port 4 data register P4 undefined 002D Port 4 mode register P4IO 00H 002E Port 4 secondary function control register P4SF 00H 002F Port 5 0030 0031 0032 0033 0034 0035 0036 0037 P5 Timer 0 counter TM0 Timer 0 register TMR0 undefined 8 TM1 Timer 1 register TMR1 00H — R 00H 00H 00H R/W Timer 1 counter 00H R/W 16 00H 00H 00H 00H 00H I indicates that the register has a nonexistent bit. 10/28 ¡ Semiconductor MSM66101 SFR (Continued) Address (HEX) Name Symbol R/W 8/16-bit Operation Reset 0040 Timer 0 control register TCON0 00H 0041 Timer 1 control register TCON1 00H 0046I Transition detector register Serial port transmission baud rate generator counter TRNSIT undefined 0048 0049 Serial port transmission baud rate generator register STTMR 004AI STTMC 0050I Serial port transmission baud rate generator control register Serial port transmission mode control register 0051 Serial port transmission data buffer register STBUF W 0054 Serial port receiving mode control register SRCON R/W 12H 0055 Serial port receiving data buffer register SRBUF R undefined 0056I Serial port receiving error register SRSTAT 0058I A/D scan mode register ADSCAN 0060I 0061 0062I 0063 0064I 0065 0066I 0067 0068I 0069 006AI 006B 006CI 006D 006EI 006F STTM 00H R/W 00H 8 82H STCON A/D conversion result register 0 ADCR0 A/D conversion result register 1 ADCR1 A/D conversion result register 2 ADCR2 A/D conversion result register 3 ADCR3 ADCR4 A/D conversion result register 5 ADCR5 A/D conversion result register 6 ADCR6 A/D conversion result register 7 ADCR7 undefined F0H R/W R A/D conversion result register 4 0FH 80H 8/16 undefined I indicates that the register has a nonexistent bit. 11/28 ¡ Semiconductor MSM66101 SFR (Continued) Address (HEX) 0070 0071I 0072 0073I 0074 0075I 0076 Name Symbol PWM 0 counter PWMC0 PWM 0 register PWMR0 8/16-bit operation PWM 1 counter PWMC1 PWMR1 0078I PWM 0 control register PWCON0 007AI PWM 1 countrol register PWCON1 Reset 00H F0H 00H 8/16 PWM 1 register 0077I R/W R/W F0H 00H F0H 00H F0H 8 0CH 0CH I indicates that the register has a nonexistent bit. 12/28 ¡ Semiconductor MSM66101 ADDRESSING MODES The MSM66101 provides independent 64K-byte data and 64K-byte program spaces with various types of addressing modes. These modes are shown below, for both RAM (for data space) and ROM (for program space). 1. RAM Addressing Mode (for data space) 1.1 Register Direct Addressing Example ROR DP DP 1.2 Page Addressing a) Zero Page Example L A, 18H SFR 0000H 0018H b) Direct Page Example ST A, off 10H RAM xx00H xx10H 1.3 Pointing Register (PR) Indirect Addressing a) Data Point (DP) Indirect Example SLL [DP] RAM DP b) User Stack Pointer (USP) Indirect Example SRL 10H [USP] USP RAM –128 to +127 13/28 ¡ Semiconductor MSM66101 c) Index Register (X1, X2) Indirect Example INC 300H [X1] RAM X1 0–65535 1.4 Immediate Addressing Example MOV SSP, #27FH 2. ROM Addressing Mode (for program space) 2.1 Direct Addressing Example LC A, 200H ROM 0200H 2.2 Simple Indirect Addressing Example LC A, [DP] ROM DP 2.3 Double Indirect Addressing Example LC A, [[DP]] RAM ROM DP 2.4 Indirect Addressing with 16-bit Offset Example CMPC A, [300H [X1]] X1 ROM 0–65535 14/28 ¡ Semiconductor MSM66101 MEMORY MAPS Program Memory Space 0000H 0000H 0027H 0028H Internal ROM Area 0037H 0038H Vector Table Area (40 bytes) VCAL Table Area (16 bytes) 2FFFH External Memory FFFFH 2FFFH Data Memory Space Zero Page Area 0000H 007FH 0080H 00BFH 00C0H 00FFH Internal RAM Area 01FFH External Memory Area 0000H SFR area Special Function Registers PR area PORT, A/D C, TIMER, PWM, etc.... 007FH 0080H PR0 PR1 PR2 PR3 PR4 PR5 PR6 PR7 00BFH 00C0H 80 82 X1 Low-Order High-Order X2 84 86 DP USP FFFFH 01FFH 15/28 ¡ Semiconductor MSM66101 ABSOLUTE MAXIMUM RATINGS (Ta = 25°C) Parameter Supply Voltage Symbol Condition Rating Input Voltage VI –0.3 to VDD+0.3 Output Voltage VO –0.3 to VDD+0.3 GND = AGND = 0V Analog Ref. Voltage VREF –0.3 to VDD+0.3 Analog Input Voltage VAI –0.3 to VREF 64-pin shrink DIP Power Dissipation PD Ta=85°C per package 565 68-pin QFJ 1120 TSTG — V 930 64-pin QFP Ta = 85°C per output Storage Temperature Unit –0.3 to 7.0 VDD mW 50 –55 to +150 °C Unit RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Range Supply Voltage VDD fOSC £ 10MHz 4.5 to 5.5 Memory Hold Voltage VDDH fOSC = 0Hz 2.0 to 5.5 Operating Frequency fOSC VDD = 5V ±10% 0 to 10 MHz Ambient Temperature Ta — MOS load –40 to +85 °C Fan Out N TTL load V 20 P0 2 P1, P2, P3, P4 1 — 16/28 ¡ Semiconductor MSM66101 ELECTRICAL CHARACTERISTICS DC Characteristics (VDD = 5V ± 10%, Ta = –40 to +85°C) Parameter "H" Input Voltage 1, 3, 6 Min. 2.4 Typ. — Max. VDD+0.3 4.0 — VDD+0.3 4.2 — VDD+0.3 "H" Input Voltage 2 3.6 — VDD+0.3 "L" Input Voltage 1, 2, 3, 6 –0.3 — 0.8 –0.3 — 0.8 "H" Input Voltage 5, 7 "H" Input Voltage 8 "L" Input Voltage 5, 7 Symbol Condition VIH — VIL — "L" Input Voltage 8 "H" Output Voltage 1, 4 "H" Output Voltage 2 "L" Output Voltage 1, 4 "L" Output Voltage 2 VOH VOL –0.3 — 0.4 IO = –400mA 4.2 — — IO = –200mA 4.2 — — IO = 3.2mA — — 0.4 IO = 1.6mA — — 0.4 — — 1/–1 — — 1/–20 — — 10/–10 –2 — — –1 — — 10 — — Input Leakage Current 3, 6, 7 Input Current 5 IIH/IIL VI = VDD/0V Input Current 8 "H" Output Current 1 "H" Output Current 2 "L" Output Current 1 IOH VO = 2.4V IOL Unit V mA mA 5 — — ILO VO = VDD/0V — — ±2 Input Capacitance CI 5 — CO f = 1MHz Ta = 25°C — Output Capacitance — 7 — Analog Reference Power Supply Current IREF A/D in operation — 0.3 2 mA A/D stopped — 0.5 10 mA Current Consumption (during STOP) * IDDS VDD = 2V — 0.2 10 — — 1 100 Current Consumption (during HALT) IDDH — 6 10 Current Consumption IDD "L" Output Current 2 Output Leakage Current 1, 2, 4 1: 2: 3: 4: 5: 6: 7: 8: *: fOSC = 10MHz No load mA pF mA mA — 20 35 Applied to P0 Applied to P1, P2,P3 and P4 Applied to P5 Applied to ALE, PSEN, RD, WR and RESOUT Applied to RES and NMI Applied to READY and EA Applied to FLT Applied to OSC0 VDD or GND for ports serving as the input pin. No-load for any other. 17/28 ¡ Semiconductor MSM66101 AC Characteristics • External program memory control Symbol Condition Clock (OSC) Pulse Parameter tfW — ALE Pulse Width PSEN Pulse Width (VDD=5V±10%, Ta=–40 to +85°C) Min. Max. Unit 50 — tAW 3tfW–20 — tPW 4tfW–20 — PSEN Pulse Delay Time tPAD Low Address Setup time tAAS tfW–20 2tfW–35 tfW+20 2tfW+20 Low Address Hold Time tAAH tfW–20 tfW+40 High Address Delay Time tAAD tfW–20 tfW+40 High Address Hold Time tAPH tfW–20 tfW+40 Instruction Setup Time tIS 100 — Instruction Hold Time tIH 0 tfW–20 CL = 50pF ns • External data memory control Parameter (VDD=5V±10%, Ta=–40 to +85°C) Min. Max. Unit Symbol Condition Clock (OSC) Pulse tfW — 50 — ALE Pulse Width tAW 3tfW–20 — RD Pulse Width tRW 4tfW–20 — WR Pulse Width tWW 4tfW–20 — RD Pulse Delay Time tRAD tWAD tfW–20 tfW–20 tfW+20 WR Pulse Delay Time Low Address Setup Time tAAS 2tfW–35 2tfW+20 Low Address Hold Time tAAH tfW–20 tfW+40 High Address Setup Time tAAD tfW–20 tfW+40 High Address Hold Time tARH tfW–20 tfW+40 High Address Hold Time tAWH tfW–20 tfW+40 Memory Data Setup Time tMS 100 — Memory Data Hold Time tMH 0 tfW–20 Data Delay Time tDD tfW–20 Data Hold Time tDH tfW–20 tfW+40 tfW+40 CL = 50pF tfW+20 ns 18/28 ¡ Semiconductor MSM66101 CLK t∆W t∆W ALE tAW PSEN tPAD AD0–7 tPW PC0–7 tAAS INST0–7 tAAH AD8–15 tIS tIH PC8–15 tAAD tAPH RD tRAD AD0–7 tRW RAP0–7 tAAS DIN 0–7 tAAH AD8–15 tMS tMH RAP8–15 tAAD tAPH WR tWAD AD0–7 tWW RAP0–7 tAAS AD8–15 DOUT0–7 tAAH tDD tDH RAP8–15 tAAD tAWH 19/28 ¡ Semiconductor MSM66101 • Serial port control Master mode (VDD=5V±10%, Ta=–40 to +85°C) Parameter Symbol Condition Min. Max. Clock (OSC) Pulse Width tfW — 50 — Serial Clock Pulse Width tSCKW — 8tfW — Output Data Setup Time tSTMXS 8tfW+40 — Output Data Hold Time tSTMXH 6tfW–20 — Input Data Setup Time tSRMXS 2tfW+10 — Input Data Hold Time tSRMXH 50 — CL=50pF Unit ns Slave mode (VDD=5V±10%, Ta=–40 to +85°C) Parameter Symbol Condition Min. Max. Clock (OSC) Pulse Width tfW — 50 — Serial Clock Pulse Width tSCKW — 8tfW — Output Data Setup Time tSTSXS 6tfW+40 — Output Data Hold Time tSTSXH 6tfW–20 — Input Data Setup Time tSRSXS 100 — Input Data Hold Time tSRSXH 100 — CL=50pF Unit ns 20/28 1 0 / . & % $ # " 5 4 3 2 * ) ( ' H G K J I D C F E P O N V U T S R Q ¡ Semiconductor MSM66101 OSC t∆W t∆W SCK tSCKW tSCKW SDOUT (TXD) tSTMXH SDIN (RXD) tSTMXS Valid Valid tSRMXH tSRMXS SCK tSCKW tSCKW SDOUT (TXD) tSTSXH SDIN (RXD) Valid tSTSXS Valid tSRSXH tSRSXS 21/28 ¡ Semiconductor MSM66101 A/D Converter Characteristics • Operating range Parameter Symbol Condition Min. Typ. Max. VDD fOSC £ 10MHz 4.5 — 5.5 Power Supply Voltage Unit Analog Reference Voltage VR 4.5 — VDD Analog Input Voltage VAI VAG — VR Analog Reference Power Voltage Resistance RR — 16 — kW Operating Temperature Top –40 — +85 °C VAG = GND = 0V VDD = 5V ± 10% V • A/D Converter accuracy Normal operation mode Parameter (VDD=5V±10%, fOSC=10MHz, Ta=–40 to +85°C) Symbol Condition Resolution n Absolute Error EA Relative Error ER Zero Point Error EZ Full Scale Error EF Differential Linearity Error ED Crosstalk EC See the recommended circuit. VR=VDD VAG=GND=0V Analog input source impedance £5kW One channel conversion time tC=64ms Min. Typ. * Max. * * — — — — 10 10 — — — — +3.0 –3.5 +2.0 –3.5 — — — — ±1.5 ±1.0 0 0 — — +3.0 +2.0 –0.5 –1.0 — — –3.5 –3.5 — — — — +3.0 +2.0 — — ±0.5 ±0.5 — — Unit Bit LSB * VDD=5V, Ta=25°C HALT/HOLD operation mode Parameter Resolution (VDD=5V±10%, fOSC=10MHz, Ta=–40 to +85°C) Symbol Condition n See the recommended circuit. VR=VDD VAG=GND=0V Analog input source impedance £5kW One channel conversion time tC=64ms Absolute Error EA Relative Error ER Zero Point Error EZ Full Scale Error EF Differential Linearity Error ED Crosstalk EC Min. Typ. * — — Max. * — * — 10 10 +1.0 –2.0 — — — — +2.0 –3.5 — — — — ±1.0 ±0.5 +0.5 +0.5 — — +2.0 +1.0 –1.0 –1.5 — — –3.5 –2.0 — — — — +2.0 +1.0 — — ±0.5 ±0.5 — — Unit Bit LSB * VDD=5V, Ta=25°C 22/28 ¡ Semiconductor MSM66101 • Recommended circuit Reference Voltage VREF +5V VDD + 0.1 47 µF µF RI – + + 0.1 47 µF µF AI0–7 ~ GND Analog Input 0V AGND 0.1 µF RI (Analog input source impedance) £ 5kW • A/D Converter conversion characteristics 1 [HEX] EF MAX 3FF EF MIN Ideal Conversion (center line) Conversion Code Actual Conversion width Actual Conversion (center line) 000 EZ MIN EZ MAX VREF [V] Analog Input Conversion Characteristics Diagram 1 23/28 ¡ Semiconductor MSM66101 Absolute error (EA) The absolute error indicates a difference between actual conversion and ideal conversion, excluding a quantizing error. The absolute error of the A/D converter gets larger as it approaches the zero point or full scale. (See to Conversion Characteristics Diagram 1.) Relative error (ER) The relative error indicates a deviation from a line which connects the center point of the zero point conversion width with that of the full scale conversion width, excluding a quantizing error. The relative error of this A/D converter is almost due to a differential linearity error. Zero point error (EZ) and full scale error (EF) The zero point error and full scale error indicate a difference between actual conversion and ideal conversion at the zero point and full scale, respectively. (See Conversion Characteristics Diagram 1.) • A/D Converter conversion characteristics 2 (Temperature Characteristics) [HEX] [LSB] +25°C 3FF +4 –40°C +85°C +3 ES Differential Linearity Error +2 Conversion Code During normal operation ES +1 During HALT ES 000 Eta [V] Analog Input Conversion Characteristics Diagram 2-1 0 –40 +85 [°C] Temperature Ta Conversion Characteristics Diagram 2-2 Differential linearity error (ED) The differential linearity error indicates a difference between the actual conversion width (actual step width) and ideal value (1LSB). With this A/D converter, a voltage for actual conversion is shifted and the inclination of a voltage is changed, with changes of temperature (see Conversion Characteristics Diagram 2-1). Specifications described in the foregoing tables are established from Eta shown in Conversion Characteristics Diagram 2-1. Conversion Characteristics Diagram 2-2 shows temperature characteristics of differential linearity error of ES. 24/28 ¡ Semiconductor MSM66101 PACKAGE DIMENSIONS (Unit : mm) SDIP64-P-750-1.78 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin Cu alloy Solder plating 5 mm or more 8.70 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 25/28 ¡ Semiconductor MSM66101 (Unit : mm) QFP64-P-1414-0.80-BK Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.87 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 26/28 ¡ Semiconductor MSM66101 (Unit : mm) QFJ68-P-S950-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin Cu alloy Solder plating 5 mm or more 4.50 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 27/28 ¡ Semiconductor MSM66101 (Unit : mm) ADIP64-C-750-1.78 Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 28/28