E2U0027-28-83 ¡ Semiconductor MSM7540L/7560L ¡ Semiconductor This version: Aug. 1998 MSM7540L/7560L Previous version: Nov. 1996 Single Rail ADPCM CODEC GENERAL DESCRIPTION The MSM7540L/7560L are single channel ADPCM CODEC ICs which perform mutual transcoding between an analog voice band signal 300 to 3400 Hz and 32 kbps ADPCM serial data. Using advanced circuit technology, these devices operate from a single 3 V power supply and provide low power consumption. The MSM7540L/7560L are optimized for advanced digital cordless telephone system applications. FEATURES • Single 3 V Power Supply Operation • ADPCM Algorithm : Complies completely with 1988's version ITU-T G.721 (32 kbps) • Transmit/Receive Full-Duplex Operation • Transmit/Receive Synchronous Mode Only • Serial ADPCM Transmission Data Rate : 32 kbps to 2048 kbps • Serial PCM Transmission Data Rate : 64 kbps to 2048 kbps • PCM Interface Coding Format MSM7540L : A-law or Linear (14 bit, 2's compliment) Selectable MSM7560L : m-law or Linear (14 bit, 2's compliment) Selectable • Low Power Consumption Operating Mode : 18 mW Typ. (VDD = 3.0 V) Power-Down Mode : 0.3 mW Typ. (VDD = 3.0 V) • Two Analog Input Amplifier Stages : Externally Adjustable Gain • Analog Output Stage : Push-pull Drive (direct drive of 350 W␣ + 120 nF) • Built-in Crystal Oscillator (10.368 MHz) • Built-in Reference Voltage Supply • Option Reset Specified by ITU-T G. 721/ADPCM • Package: 28-pin plastic SOP (SOP28-P-430-1.27-K) (Product name: MSM7540LGS-K) (Product name: MSM7560LGS-K) 32-pin plastic TSOP (TSOPI32-P-814-0.50-1K) (Product name: MSM7560LTS-K) 1/15 GSX1 AIN2 X2 – + RCLPF – + A/D Conv. 0 BPF 1 1 COMPANDER 0 ADPCM CODER P / S XSYNC IS BCLKA 0 P / S PCMSO S / P PCMSI ¡ Semiconductor AIN1 X1 BLOCK DIAGRAM V DD AG DG GSX2 SG V REF 1 PDN MCK RES CLOCK/ TIMING BCLKB LPS AOUT+ –1 AOUT– – + S / P PCMRI PCMRO 0 P / S ADPCM DECODER S / P 1 PWI RCLPF D/A Conv. 1 LPF 0 EXPANDER 0 1 IR RSYNC 2/15 MSM7540L/7560L VFRO MSM7540L/7560L ¡ Semiconductor PIN CONFIGURATION (TOP VIEW) RES 1 28 BCLKB PCMRI 2 27 BCLKA PCMRO 3 26 XSYNC IR 4 25 RSYNC IS 5 24 MCK PCMSI 6 23 X2 PCMSO 7 22 X1 LPS 8 21 PDN DG 9 20 VDD AG 10 19 AOUT+ SG 11 18 AOUT– AIN1 12 17 PWI GSX1 13 16 VFRO AIN2 14 15 GSX2 28-Pin Plastic SOP X1 X2 NC MCK RSYNC XSYNC BCLKA BCLKB RES PCMRI PCMRO IR IS NC PCMSI PCMSO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 PDN VDD NC AOUT+ AOUT– PWI VFRO GSX2 AIN2 GSX1 AIN1 SG AG NC DG LPS NC: No connection 32-Pin Plastic TSOP 3/15 MSM7540L/7560L ¡ Semiconductor PIN AND FUNCTIONAL DESCRIPTIONS AIN1, AIN2, GSX1, GSX2 Transmits analog input and the output for transmit gain adjustment. AIN1 (AIN2) connects to the inverting input of the internal transmit amplifier. GSX1 (GSX2) connects to the output of the internal transmit amplifier output. Refer to Fig. 1 for gain adjustment. VFRO, AOUT+, AOUT–, PWI Receives analog output and the output for receive gain adjustment. VFRO is receive filter output. AOUT+ and AOUT– are differential analog signal outputs which can directly drive ZL = 350 W + 120 nF. Refer to Fig. 1 for gain adjustment. C1 Analog Input R1 AIN1 – + R2 GSX1 C2 R3 AIN2 – to ENCODER + R4 GSX2 Transmit Gain: = (R2/R1) ¥ (R4/R3) VFRO RS* Receive Gain: = (R6/R5) from DECODER R5 PWI R6 – AOUT– + Z L =120 nF + 350 W V0 Analog Output –1 AOUT+ *: Side Tone Pass (Gain = R6/RS) Figure1 Analog Input/Output Interface 4/15 ¡ Semiconductor MSM7540L/7560L SG Analog signal ground voltage output. The output voltage of this pin is approximately 1.4 V. Put bypass capacitors between this pin and the AG pin. During power-down this output voltage is 0 V. The external SG voltage, if necessary, should be used via a buffer. AG Analog ground. DG Digital ground. This ground is separated internally from the analog signal ground pin (AG). The DG pin must be kept as close as possible to AG on the PCB. VDD +3 V power supply. LPS PCM coding law selection. MSM7540L only; if this pin goes to a "0" level, PCMSO, PCMSI, PCMRO, and PCMRI become the A-law character signal, and if these pins goes to a "1" level, the signal becomes a linear value character signal (2's complement). MSM7560L only; if this pin goes to a "0" level, PCMSO, PCMSI, PCMRO, and PCMRI become the m-law character signal, and if these pins goes to a "1" level, the signal becomes a linear value character signal (2's complement). PDN Power down control input. If this pin is "0", this device is in the power-down state. Normally, this pin is set to "1". RES Optional reset input specified by ITU-T Recommendation G. 721. If this pin is "0", the device is in the reset state. The reset width (during "L") should be 125 ms or more. MCK Master clock input. The frequency must be 10.368 MHz. The master clock signal may be asynchronous to BCLKA, BCLKB, XSYNC, and RSYNC. PCMSO Transmit PCM data output. PCM is output from MSB in synchronization with the rising edge of BCLKB and XSYNC. 5/15 ¡ Semiconductor MSM7540L/7560L PCMSI Transmit PCM data input. This signal is converted to transmit ADPCM data. PCM is shifted in synchronization with the falling edge of BCLKB. Normally, this pin is connected to PCMSO. PCMRO Receive PCM data output. PCM is the output signal after ADPCM decoder processing. This signal is output serially from MSB in synchronization with the rising edge of BCLKB and RSYNC. PCMRI Receive PCM data input. PCM is shifted on the falling edge of the BCLKB input from MSB. Normally, this pin is connected to PCMRO. IS Transmit ADPCM signal output. After having encoded PCM with ADPCM, this signal is output from MSB in synchronization with the rising edge of BCLKA and XSYNC. This pin is an open drain output and remains in a high impedance state during power-down. IS requires a pull-up resistor. IR Receive ADPCM signal input. The ADPCM signal is shifted in series and synchronization with the falling edge of BCLKA and RSYNC and output from MSB. BCLKB Shift clock input for the PCM data (PCMSO, PCMSI, PCMRO, PCMRI). The frequency is set in the 64 kHz to 2048 kHz range. XSYNC 8 kHz synchronous signal input for transmit PCM and ADPCM data. Synchronize this signal with BCLKA and BCLKB signal. XSYNC is used to indicate the MSB of the serial PCM and ADPCM data stream. Be sure to input the XSYNC signal because it is also used as the imput of the timing generator. RSYNC 8 kHz synchronous signal input for receive PCM and ADPCM data. Synchronize this signal with BCLKA and BCLKB signal. RSYNC is used to indicate the MSB of the serial PCM and ADPCM data stream. BCLKA Shift clock input for the ADPCM data (IS, IR). The frequency is set in the of 32 kHz to 2048 kHz range. 6/15 MSM7540L/7560L ¡ Semiconductor X1, X2 Crystal oscillator (10.368 MHz) connection. Connect X2, the clock output pin, directly to the MCK pin. When using a conventional external clock of 10.368 MHz, X1 should be connected to the ground, X2 open, and provide the external clock through the MCK pin. <Using a self-oscilation circuit> <Using an external clock> MSM7540L/60L MSM7540L/60L X1 X2 10.368 MHz MCK X1 X2 MCK 10.368 MHz 7/15 MSM7540L/7560L ¡ Semiconductor ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit Power Supply Voltage VDD Analog Input Voltage VAIN — –0.3 to +5 V — –0.3 to VDD + 0.3 V Digital Input Voltage VDIN — –0.3 to VDD + 0.3 V TSTG Storage Temperature — –55 to +150 °C RECOMMENDED OPERATING CONDITIONS Parameter Symbol Power Supply Voltage VDD Operating Temperature Ta Condition Voltage must be fixed — MCK, XSYNC, RSYNC, PCMRI, Input High Voltage VIH PCMSI, BCLKA, BCLKB, IR, LPS, PDN, RES Min. Typ. Max. Unit 2.7 — 3.6 V –25 +25 +75 °C — VDD V 0.45 ¥ VDD MCK, XSYNC, RSYNC, PCMRI, Input Low Voltage VIL Master Clock Frequency fMCK MCK fBCKA fBCKB fSYMC — –0.01% 10.368 +0.01% MHz BCLKA 32 — 2048 kHz BCLKB 64 — 2048 kHz XSYNC, RSYNC — 8.0 — kHz MCK, BCLKA, BCLKB 30 50 70 % — — 50 ns — — 50 ns 100 — — ns LPS, PDN, RES Bit Clock Freqency Synchronous Signal Frequency Clock Duty Ratio DC 0.16 0 PCMSI, BCLKA, BCLKB, IR, ¥ VDD V MCK, XSYNC, RSYNC, PCMRI, Digital Input Rise Time tIr PCMSI, BCLKA, BCLKB, IR, LPS, PDN, RES MCK, XSYNC, RSYNC, PCMRI, Digital Input Fall Time tIf PCMSI, BCLKA, BCLKB, IR, tXS BCLKA, BCLKB to XSYNC LPS, PDN, RES Transmit Sync Signal Setting Time tXS XSYNC to BCLKA, BCLKB 100 — — ns tRS BCLKA, BCLKB to RSYNC 100 — — ns tSR RSYNC to BCLKA, BCLKB 100 — — ns Synchronous Signal Width tWS XSYNC, RSYNC 1 BCLK — 100 ms PCM, ADPCM Set-up Time tDS — 100 — — ns — Receive Sync Signal Setting Time PCM, ADPCM Hold Time Digital Output Load Bypass Capacitor for SG tDH 100 — — ns RDL IS (Pull-up Resistor) 500 — — W CDL IS, PCMSO, PCMRO — — 100 pF CSG SG´GND — 10+0.1 — mF 8/15 MSM7540L/7560L ¡ Semiconductor ELECTRICAL CHARACTERISTICS DC and Digital Interface Characteristics Parameter Power Supply Current (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Symbol IDD1 Condition Operating Mode, No Signal (VDD = 3.0 V) Min. Typ. Max. Unit — 6 12 mA IDD2 Power Down Mode (VDD = 3.0 V) — 0.1 0.2 mA Input High Voltage VIH — 0.45 ¥ VDD — VDD V Input Low Voltage VIL — 0.0 — 0.16 ¥ VDD V — — 2.0 mA Input Leakage Current Output Low Voltage IIH VI = VDD IIL VI = 0 V — — 0.5 mA VOL 1 LSTTL, Pull-up: 500 W 0.0 0.2 0.4 V Output Leakage Current IO Input Capacitance CIN — — 10 mA — — 5 — pF Condition IS Transmit Analog Interface Characteristics Min. Typ. Max. Unit Input Resistance Parameter Symbol RINX AIN1, AIN2 10 — — MW Output Load Resistance RLGX GSX1, GSX2 20 — — kW Output Load Capacitance CLGX GSX1, GSX2 — — 100 pF Output Amplitude VOGX GSX1, GSX2, RL = 20 kW — — *1.300 VPP Input Offset Voltage VOFGX Pre–OPAMPs –20 — +20 mV SG Output Voltage VSG — — 1.4 — V SG Output Inpedance RSG — — 40 80 kW SG Rise Time TSG — 700 — ms Min. Typ. Max. Unit 10 — — MW GND´SG 10 mF + 0.1 mF (Rise Time to 90% of max. level) Receive Analog Interface Characteristics Parameter Input Resistance Output Load Resistance Output Capacitance Output Voltage Level Symbol Condition RINPW PWI RLVF VFRO 50 — — kW RLAO AOUT+, AOUT– 1.2 — — kW CLVF VFRO — — 100 pF CLAO AOUT+, AOUT– — — 100 pF VOVF VFRO, RL = 50 kW — — *1.300 VPP RL = 1.2 kW — — *1.300 VPP — — *1.300 VPP –100 — +100 mV –20 — +20 mV 40 — — dB VOAO AOUT+, AOUT– ZL = 350 W + 120 nF(See Fig.1) VOFVF Offset Voltage Open Loop Gain * VOFAO GDB VFRO AOUT+, AOUT– (GAIN = 0 dB), Power amp only Power amp (0.3 to 3.4 kHz, ZL = 350 W + 120 nF)(See Fig.1) –7.7 dBm (600 W) = 0 dBm0, + 3.14 dBm0 = 1.300 VPP (MSM7540L) –7.7 dBm (600 W) = 0 dBm0, + 3.17 dBm0 = 1.300 VPP (MSM7560L) 9/15 MSM7540L/7560L ¡ Semiconductor AC Chracteristics (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Condition Parameter Symbol Freq. Level (Hz) (dBm0) LOSS T1 0 to 60 Others LOSS T2 300 to 3000 Transmit Frequency LOSS T3 1020 Response LOSS T4 3300 Receive Frequency Response to Distortion Ratio Receive Signal to Distortion Ratio Transmit Gain Tracking Receive Gain Tracking Typ. Max. Unit 25 — — dB — +0.20 dB –0.15 0 — Reference –0.15 dB — +0.80 dB LOSS T5 3400 0 — 0.80 dB LOSS T6 3968.75 13 — — dB LOSS R1 0 to 3000 –0.15 — +0.20 dB LOSS R2 1020 LOSS R3 3300 LOSS R4 3400 LOSS R5 3968.75 SD T1 Transmit Signal Min. 0 — 3 SD T2 SD T3 Reference 0 1020 –30 (*1) dB –0.15 — +0.80 dB 0 — 0.80 dB 13 — — dB 35 — — dB 35 — — dB 35 — — dB SD T4 –40 28 — — dB SD T5 –45 23 — — dB SD R1 3 35 — — dB 35 — — dB 35 — — dB SD R2 SD R3 0 1020 –30 (*1) SD R4 –40 28 — — dB SD R5 –45 23 — — dB GT T1 3 –0.2 — +0.2 dB GT T2 –10 GT T3 1020 –40 GT T4 –50 dB Reference — –0.2 — +0.2 dB –0.5 — +0.5 dB GT T5 –55 –1.2 — +1.2 dB GT R1 3 –0.2 — +0.2 dB GT R2 –10 GT R3 1020 –40 Reference dB –0.2 — +0.2 dB GT R4 –50 –0.5 — +0.5 dB GT R5 –55 –1.2 — +1.2 dB — *1 Use the P-message weighted filter 10/15 MSM7540L/7560L ¡ Semiconductor AC Characteristics (Continued) (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Condition Parameter Symbol Freq. Level (Hz) (dBm0) NIDLT — AIN = SG NIDLR — — Idle Channel Noise Absolute Signal Amplitude AVT 1020 AVR PSRRT Noise Freq. Noise Level Rejection Ratio PSRRR : 0 to 50 kHz : 50 mVPP Delay Time (*1) (*1) (*2) Min. Typ. — — — — GSX2 0.285 VFRO 0.285 0 Power Supply Noise Digital Output Others 0.320 (*3) 0.320 (*3) Max. Unit –68 (–75.7) dBm0p –72 (dBmp) (–79.7) 0.359 Vrms 0.359 Vrms 30 — — dB 30 — — dB tSDX 50 — 200 ns tSDR 50 — 200 ns 50 — 200 ns 50 — 200 ns 50 — 200 ns tXD1 tXD2 — 1 LSTTL + 100 pF, Pull-up: 500 W tXD3 — — *1 Use the P-message weighted filter *2 PCMRI input code "11010101"(MSM7540L) "11111111"(MSM7560L) *3 0.320 Vrms = 0 dBm0 = –7.7 dBm Note: All ADPCM coder and decoder characteristics comply with ITU-T Recommendation G.721. 11/15 MSM7540L/7560L ¡ Semiconductor TIMING DIAGRAM Transmit Side PCM/ADPCM Data Interface 0 BCLKB txs XSYNC 1 2 tsx 3 4 5 6 7 8 txd1 txd2 10 11 12 13 14 txd3 MSB PCMSO 9 tws LSB txd3 tsdx MSB PCMSO (during linear) BCLKA 0 txs XSYNC 1 2 txd1 txd2 tsx LSB 3 4 5 6 7 8 9 10 7 8 9 10 9 10 txd3 IS MSB tsdx LSB Receive Side PCM/ADPCM Data Interface BCLKA 0 trs 1 2 tsr 3 4 5 6 11 12 13 14 tws RSYNC tds IR txd3 tdh MSB 0 BCLKB trs 1 LSB 2 tsr 3 4 5 6 7 8 RSYNC trd1 PCMRO txd3 trd2 MSB LSB trd3 tsdx PCMRO (during linear) MSB LSB Note: Linear format A code of an input/output level is determined by the 14-bit 2'compliment. Refer to the table below for code format. Input/Output level MSB to LSB +Full-scall 01111111111111 0 00000000000000 –Full-scall 10000000000000 12/15 MSM7540L/7560L ¡ Semiconductor APPLICATION CIRCUIT V DD MSM7540L/7560L 1 V DD 2 Receive PCM Output Receive ADPCM Input 3 4 5 Transmit ADPCM Output 6 Transmit PCM Output 7 8 9 10 11 Transmit Analog Input 12 13 14 RES BCLKB PCMRI BCLKA PCMRO XSYNC IR RSYNC IS MCK PCMSI X2 PCMSO X1 LPS PDN DG V DD AG AOUT+ SG AOUT– AIN1 PWI GSX1 VFRO AIN2 GSX2 ADPCM Algorithm Reset Input 28 Shift Clock Input for PCM, ADPCM Data (64 kHz to 2048 kHz) 27 26 8 kHz Sync Signal Input 25 24 23 22 21 10.368 MHz Power Down Input 20 19 18 17 16 15 Receive Analog Output (Push-Pull) 13/15 ¡ Semiconductor MSM7540L/7560L PACKAGE DIMENSIONS (Unit : mm) SOP28-P-430-1.27-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.75 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 14/15 ¡ Semiconductor MSM7540L/7560L (Unit : mm) TSOPI32-P-814-0.50-1K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.27 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 15/15