E2U0035-16-X2 ¡ Semiconductor MSM7582/7582B ¡ Semiconductor This version: Jan. 1998 MSM7582/7582B Previous version: Nov. 1996 p/4 Shift QPSK MODEM GENERAL DESCRIPTION The MSM7582/7582B are CMOS ICs for the p/4 shift QPSK modem developed for the digital cordless telephone systems. The devices are designed for Personal and Cell station applications, the MSM7582B is the improved MSM7582 in modulator burst rise-up and fall-down characteristics. FEATURES • Single Power Supply (VDD: 2.7 V to ␣ 3.6 V) (Modulator Block) • Built-in Root Nyquist Filter for Baseband Limiting (50% Roll-off) • Ramp Bit for Burst Signal Rise-up: MSM7582/1.75 symbols MSM7582B/2.0 symbols • Ramp Bit for Burst Signal Fall-down: MSM7582/2.75 symbols MSM7582B/2.0 symbols • Built-in D/A converters for Analog Output of Quadrature Signal I/Q Components and Power Envelope Output I2 + Q2 • Differential I/Q Analog output format • I/Q Output DC Offset / Gain Adjustable (Demodulator Block) • Full Digital System, p/4 shift QPSK Demodulation • Input IF signal Frequency Selectable: 1.2/10.7/10.75/10.8 MHz • Built-in Clock Recovery: 4 Circuits useful for Cell station (Common) • Various Power-down Modes: Tramsmit/Receive Independant • Built-in Precise Analog Voltage Reference • MCU Serial Interface for Mode setting and Built-in Test circuit • Test Modes: Eye pattern / AFC Compensating Signal / Phase Detection Signal, possible to monitor • Transmission Speed: 384 kbps • Low Power consumption Operating mode : 15 mA Typ. / Modulator (VDD = 3.0 V) : 9 mA Typ. / Demodulator (VDD = 3.0 V) Whole system Power-down mode: 0.01 mA Typ. (VDD = 3.0 V) • Package: 32-pin plastic TSOP (TSOPI32-P-814-0.50-1K)(Product name : MSM7582TS-K) (Product name : MSM7582BTS-K) 1/24 IFIN Phase Detector MCK Decision Unit AFC IFSEL1 (From CR) RXC S To each block X2 E DPLL Decoder L X1 DEN EXCK DIN DOUT Control Register (CR) +1 ENV +1 -1 Root Nyquist LPF Q ± D/A CONV ENV D/A CONV VREF To internal SG AFC RPR RCW SLS1 SLS2 PS/CS I ± D/A CONV -1 +1 To each block S E L 3.84 MHz To Monitor To D/A output of each block TXD TXW S/P MAPPING S E L APLL 1/10 2/24 TEST1, TEST0 TXCSEL (From CR) (From CR) TXCI 384 kHz TXCO MSM7582/7582B I+ I– Q+ Q– SG RXD IFSEL0 (From CR) S E L IFCK Delay Detector ¡ Semiconductor SL1 SL2 SL3 SL4 VDD DGND AGND BLOCK DIAGRAM To monitor output of each block To modem ENV PDN0 PDN1 PDN2 ¡ Semiconductor MSM7582/7582B PIN CONFIGURATION (TOP VIEW) AGND SG I+ I– Q+ Q– ENV PDN0 PDN1 PDN2 VDD SLS1 SLS2 RCW AFC RPR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 DGND IFIN TXCI TXCO TXD TXW DEN EXCK DIN DOUT MCK RXD RXC IFCK X2 X1 32-Pin Plastic TSOP 3/24 ¡ Semiconductor MSM7582/7582B PIN AND FUNCTIONAL DESCRIPTIONS TXD Transmit data input for 384 kbps. TXCI Transmit clock input. When the control register CR0 – B6 is “0”, a 384 kHz clock pulse synchronous with TXD should be input to this pin. This clock pulse should be continuous because these devices use APLL to generate the internal clock pulse. When CR0 – B6 is “1”, a 3.84 MHz clock pulse should be input to this pin. When the 3.84 MHz clock pulse is applied, TXCO outputs a 384 kHz clock pulse, which is generated by dividing the 3.84 MHz to TXCI by 10. The transmit data, synchronous 384 kHz clock pulse, should be input to the TXD. In this case the devices do not use APLL, and the 3.84 MHz clock pulse need not be continuous. (Refer to Fig. 1.) TXCO Transmit clock output. When CR0 - B6 is “0”, TXCO outputs the 384 kHz clock pulse (APLL output) for monitoring purposes. When CR0 – B6 is “1”, this pin outputs a 384 kHz clock pulse generated by dividing the TXCI input by 10. (Refer to Fig. 1.) When CR0 – B6 = “0” and CR5 – B7 = “1”, this pin outputs the burst timing position. TXW Transmit data window input. The transmit timing signal for the burst data is input to the device pin. If TXW is “1”, the modulation data is output. However, the MSM7582 is different from the MSM7582B in the ramp response time for burst rise-up and burst fall-down of I, Q modulated outputs, as shown in the table below. (Refer to Fig, 1-1 for the MSM7582 and Fig, 1-2 for the MSM7582B) MSM7582 MSM7582B Ramp Rise-up 1.75 symbols 2 symbols Ramp Fall-down 2.75 symbols 2 symbols The TXCO burst position output timing discribed before, is different, according to this table. 4/24 , , ¡ Semiconductor MSM7582 MSM7582/7582B (1) CR0 – B6 = "0" TXD TXCI (384 kHz) TXW TXCO (384 kHz) I, Q D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 Dn-1 Dn Ramp rise-up 1.75 symbols Delay of 6.25 symbols Delay of 6.25 symbols Ramp Fall-down 2.75 symbols Delay of 6.25 symbols Ramp Fall-down 2.75 symbols (2) CR0 – B6 = "1" TXD TXCI (3.84 MHz) TXW TXCO (384 kHz) I, Q D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 Dn-1 Dn Ramp rise-up 1.75 symbols Delay of 6.25 symbols Figure 1-1 Transmit Timing Diagram 5/24 , , ¡ Semiconductor MSM7582B MSM7582/7582B (1) CR0 – B6 = "0" TXD TXCI (384 kHz) TXW TXCO (384 kHz) I, Q D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 Dn-1 Dn Ramp rise-up 2 symbols Ramp fall-down 2 symbols Delay of 6.25 symbols Delay of 6.25 symbols (2) CR0 – B6 = "1" TXD TXCI (3.84 MHz) TXW TXCO (384 kHz) I, Q D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 Dn-1 Dn Ramp rise-up 2 symbols Delay of 6.25 symbols Ramp fall-down 2 symbols Delay of 6.25 symbols Figure 1-2 Transmit Timing Diagram I+, I– Quadrature modulation signal I component differential analog outputs. Their output levels are 500 mVpp with 1.6 Vdc as the center value. The output pin load conditions are: R ≥ 10 kW, C ≤ 20 pF. The gain of these pins can be adjusted using the control register CR1 – B7 to B4, and the offset voltage at the I– pin can be adjusted using CR3 – B7 to B3. Q+, Q– Quadrature modulation signal Q component differential analog outputs. Their output levels are 500 mVPP with 1.6 Vdc as the center value. The output pin load conditions are: R ≥ 10 kW, C ≤ 20 pF. The gain of these pins can be adjusted using the control register CR1 – B3 to B0, and the offset voltage at the Q– pin can be adjusted by using CR4 – B7 to B3. 6/24 ¡ Semiconductor MSM7582/7582B ENV Quadrature modulation signal envelope ( I2 + Q2 )output. Its output level is 500 mVPP with 1.6 Vdc as a center value. The output pin load conditions are : R ≥ 10 kW, C ≤ 20 pF. The gain of this output can be adjusted using the control register CR2 – B7 to B4. This pin is also used to monitor eye pattern, AFC Compensating signal, and phase defection of the demodulator block during the test mode. Refer to the description of the control register for details. SG Internal reference voltage output. The output voltage is about 2.0 V. A bypass capacitor should be connected between this pin and the AGND pin. PDN0, PDN1, PDN2 Inputs for power-down control. PDN0 controls the standby / communication modes, PDN1 controls the modulator, and PDN2 controls the demodulator. Refer to Table 1 for details. Table-1 Power Down Control PDN0 PDN2 PDN1 Standby Mode Function Mode 0 0/1 1 All power-down. The control register is reset. Mode A 0 0 0 All power-down. The control register is not reset. Mode B 0 1 0 1 0 0 Modulator power is off (VREF and PLL power are also off). Demodulator power is on. Mode C Modulator power is off (VREF and PLL power is on). I and Q outputs are in a high-impedance state. Mode D Only demodulator clock recovery block power is on. 1 0 1 1 1 0 Communication Mode Modulator power is on Only demodulator clock recovery block power is on. Mode E Modulator power is off (VREF and PLL power is on). I and Q outputs are in a high-impedance state. Mode F Demodulator power is on. 1 1 1 Modulator power is on Demodulator power is on. Mode G VDD +3 V power supply voltage. AGND Analog signal ground. DGND Digital signal ground. AGND and DGND are not connected in the device. This pin should be tied to the AGND pin on the PCB as close as possible from the device. 7/24 ¡ Semiconductor MSM7582/7582B MCK Master clock input. The clock frequency is 19.2 MHz. IFIN Modulated signal input for the demodulator block. Select the IF frequency from 1.2 MHz, 10.7 MHz, 10.75 MHz, and 10.8 MHz, based on CR0 – B4 and B3. IFCK Clock signal input for demodulator block IF frequencies (10.7 MHz or 10.75 MHz). If the IF frequency is 10.7 MHz, 19.0222 MHz should be supplied. When it is 10.75 MHz, 19.1111 MHz should be supplied. When the IF frequency is 1.2 MHz or 10.8 MHz, set this pin to “0” or “1”. (Refer to Fig. 2.) X1, X2 Crystal oscillator connection pins. When supplying a 19.0222 MHz or 19.1111 MHz clock to IFCK, use these pins (Refer to Fig. 2.) When IFIN = 10.7 MHz or 10.75 MHz When IFIN = 1.2 MHz or 10.8 MHz MSM7582/7582B MSM7582/7582B X1 X1 X2 IFCK X2 IFCK 19.0222 MHz or 19.1111 MHz Figure 2 How to Use IFCK, X1, and X2 RXD, RXC Receive data and clock output. When power is turned on, the outputs of circuits selected by SLS1 and SLS2 appear at these pins. (Refer to Fig. 3) RXD1 RXC SLS2 SLS1 The recovery data and clock pulse are selected asynchronously using the SLS signals. Figure 3 RXD and RXC Timing Diagram 8/24 ¡ Semiconductor MSM7582/7582B SLS2, SLS1 Receiver slot select signal inputs. The devices have four sets of clock recovery circuit to each channel and four AFC information storage registers. One these circuits is selected from a combination of the signals at these pins. (SLS2, SLS1) = (0, 0): Slot 1, (0, 1): Slot 2 (1, 0): Slot 3, (1, 1): Slot 4 RPR High-speed phase clock control signal input for the clock recovery circuit. If this pin is “1”, the clock recovery circuit starts in the high-speed phase clock mode. When the phase difference is less than a defined value, the circuit shifts to the low-speed phase clock mode automatically. When this pin is “0”, the circuit is always in the low-speed phase clock mode. AFC AFC operation range specification signal input. As shown in Fig. 4, the AFC information is reset when both AFC and RPR are set to “1”. AFC operation starts after a fixed number of clock cycles and after the AFC information is reset. If RPR is set to “1”, an average number of times that AFC turns on is low. If RPR is “0”, AFC is high. If AFC is “0”, frequency error is not calculated, but the frequency is corrected using an error that is held. RCW Clock recovery circuit operation ON/OFF control signal input. If RCW pin is “0”, DPLL does not make any phase corrections. (CASE1) AFC RPR AFC information is reset. (CASE2) Average number of times AFC is high. Average number of times AFC is low. AFC information is maintained. AFC "0" RPR The clock recovery circuit starts with the previous AFC information. Average number of times AFC is high. AFC information is maintained. Figure 4 AFC Control Timing Diagram 9/24 ¡ Semiconductor MSM7582/7582B DEN , EXCK, DIN, DOUT , , Serial control ports for the microprocessor interface. The MSM7582 and MSM7582B contain a 6-byte control register. An external CPU uses these pins to read data from and write data to the control register. DEN is an enable signal input pin. EXCK is a data shift clock pulse input pin. DIN is an address and data input pin. DOUT is a data output pin. Figure 5 shows an input/output timing diagram. DEN EXCK DIN W A2 A1 A0 DOUT B7 B6 B5 B4 B3 B2 B1 B0 B2 B1 B0 High Impedance (a) Data Write Timing Diagram DEN EXCK DIN DOUT R A2 High Impedance A1 A0 B7 B6 B5 B4 B3 (b) Data Read Timing Diagram Figure 5 MCU Interface Input/Output Timing Diagram 10/24 ¡ Semiconductor MSM7582/7582B The register map is shown below Table-2 Control Register Map Register Address Data R/W A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 CR0 0 0 0 PS/CS TXCSEL MODOFF IFSEL1 IFSEL0 ENVSEL TEST1 TEST0 R/W CR1 0 0 1 Ich GAIN3 Ich GAIN2 Ich GAIN1 Ich GAIN0 Qch GAIN3 Qch GAIN2 Qch GAIN1 Qch GAIN0 R/W CR2 0 1 0 ENV GAIN3 ENV GAIN2 ENV GAIN1 ENV GAIN0 — — — — R/W CR3 0 1 1 Ich Offset4 Ich Offset3 Ich Offset2 Ich Offset1 Ich Offset0 — — — R/W CR4 1 0 0 Qch Offset4 Qch Offset3 Qch Offset2 Qch Offset1 Qch Offset0 — — — R/W CR5 1 0 1 BSTO ENBL ICT6 ICT5 ICT4 LOCAL INV1 LOCAL INV0 CLK SEL1 CLK SEL0 R/W R/W : Read/Write enable R : Read-only register 11/24 ¡ Semiconductor MSM7582/7582B ABSOLUTE MAXIMUM RATINGS Symbol Condtion Rating Unit Power Supply Voltage Parameter VDD — 0 to 5 V Digital Input Voltage VDIN — –0.3 to VDD +0.3 V Operating Temperature Top — –25 to +70 °C Storage Temperature TSTG — –55 to +150 °C RECOMMENDED OPERATING CONDITIONS (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Symbol Condtion Min. Typ. Max. Unit Power Supply Voltage VDD — 2.7 — 3.6 V Operating Temperature Range Ta — +70 °C Parameter –25 — Input High Voltage VIH All digital input pins 0.45 ¥ VDD — VDD V Input Low Voltage VIL All digital input pins 0 — 0.16 ¥ VDD V Master Clock Frequency fMCK MCK — 19.2 — MHz fTXC1 TXCI (when CR0 – B6 = "0") — 384 — kHz Modulator Input Frequency Demodulator Input Frequency fTXC2 TXCI (when CR0 – B6 = "1") — 3.84 — MHz fIFCK1 IFCK (when IFIN = 10.7 MHz) –50 ppm 19.0222 +50 ppm MHz fIFCK2 IFCK (when IFIN = 10.75 MHz) –50 ppm Clock Duty Cycle DCCK MCK, IFCK, TXCI IF Input Duty Cycle DCIF IFCK 19.1111 +50 ppm MHz 40 50 60 % 45 50 55 % ELECTRICAL CHARACTERISTICS DC Characteristics Parameter (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) IDD1 Power Supply Current Condition Symbol Mode A, Mode B (when VDD = 3.0 V) Min. Typ. Max. Unit — 0.02 0.05 mA IDD2 Mode C (when VDD = 3.0 V) — 5.5 11.0 mA IDD3 Mode D (when VDD = 3.0 V) — 5.5 11.0 mA IDD4 Mode E (when VDD = 3.0 V) — 11.5 23.0 mA IDD5 Mode F (when VDD = 3.0 V) — 9.5 19.0 mA IDD6 Mode G (when VDD = 3.0 V) — 14.0 28.0 mA Output High Voltage VOH IOH = 0.4 mA 0.5 ¥ VDD — VDD V Output Low Voltage VOL IOL = –1.2 mA 0.0 — 0.4 V Input Leakage Current IIH — — — 10 mA IIL — — — 10 mA 12/24 ¡ Semiconductor MSM7582/7582B Analog Interface Characteristics Parameter Output Resistance Load Output Capacitance Load Symbol (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Condtion RLIQ I+, I–, Q+, Q–, ENV CLIQ I+, I–, Q+, Q–, ENV VDC1 I+, I–, Q+, Q– (TXW = 0) VDC2 I+ (CR0 – B5 = 1) when not modulated Output DC Voltage Level Output AC Voltage Level VDC3 Q+ (CR0 – B5 = 1) when not modulated Min. Typ. Max. Unit 1.0 — — kW — — 20 pF 1.55 1.6 1.65 V — 1.77 — V — 1.67 — V VDC4 ENV (TXW = 0) — 1.35 — V VDC5 ENV (TXW = 1, CR0 – B2 = 0, TXD = 0) — 1.72 — V VDC6 ENV (TXW = 1, CR0 – B2 = 1, TXD = 0) — 1.63 — V — 360 — mVPP VAC I+, I–, Q+, Q– (TXD = 0) Output DC Voltage Adjustment Level Range DCVL — — ±45 — mV Output AC Voltage Adjustment Level Range ACVL — — ±4 — % P600 600 kHz detuning (*) 60 — — dB P900 900 kHz detuning (*) 65 — — dB Out-of-band Spectrum Modulation Accuracy EVM Demodulator IF Input Level IFV IFIN Input Impedance RIF — — 1.0 3.0 % rms 0.5 — VDD VPP — — 20 — kW IFIN input level CIF — — 5 — pF SG Output Voltage VSG — — 2.0 — V SG Output Impedance RSG — — 1.5 — kW * Power attenuation at 600 kHz or 900 kHz ±96 kHz as referred to two times of the power in frequency band of 0 to 96 kHz 13/24 ¡ Semiconductor MSM7582/7582B Digital Interface Characteristics Parameter (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Condtion Min. Typ. Max. Unit –200 — 200 ns 0 — 200 ns 0 — 200 ns 0 — 200 ns 0 — 200 ns 0 — 200 ns 10 — — ms tRW 10 — — ms tM1 50 — — ns tM2 50 — — ns tM3 50 — — ns tM4 50 — — ns 100 — — ns 50 — — ns 50 — — ns Symbol Other tSX tDS Transmitter Digital Input/Output Setting Time tDH tXD1 C load = 50 pF Fig. 6 tXD2 tXD3 tXD4 tRD1 Receiver Digital Input/Output Setting Time Serial Port Digital Input/Output Setting Time EXCK Clock Frequency tRD2 tRS1 to C load = 50 pF Fig. 7 tRS4 tM5 tM6 C load = 50 pF Fig. 8 tM7 tM8 0 — 100 ns tM9 50 — — ns tM10 50 — — ns tM11 0 — 50 ns — — 10 MHz fEXCK — EXCK 14/24 ¡ Semiconductor MSM7582/7582B TIMING DIAGRAM Transmit Data Input Timing TXCI [TXCO*] (384 kHz) 1 tSX 2 3 N-2 N-1 N N+1 tSX TXW tDS tDH TXD 1 2 3 N-2 N-1 N * [ ]: When CR0 – B6 = "1", TXCO is indicated. Transmit Clock (TXCO) Output Timing (when CR0 – B6 = 1) TXCI (3.84 MHz) 1 2 3 4 5 tXD1 6 7 8 9 10 tXD2 tXD1 TXCO (384 kHz) Transmit Burst Position Output (TXCO) Timing (when CR0 – B6 = 0 and CR5 – B7 = 1) M7582 TXCI (384 kHz) 1 2 8 9 N N+1 N+17 N+18 N+19 TXW tXD3 tXD4 TXCO M7582B TXCI (384 kHz) 1 2 8 9 N N+1 N+17 N+18 N+19 TXW tXD3 tXD4 TXCO Figure 6 Transmit (Modulator) Digital Input/Output Timing 15/24 ¡ Semiconductor MSM7582/7582B SLS1 SLS2 tRS1 tRS2 RCW tRS3 tRS4 AFC tRW RPR RXC tRD1 tRD2 RXD Figure 7 Receiver (Demodulator) Digital Input/Output Timing DEN tM1 DIN tM3 2 3 4 A2 5 6 11 12 tM4 tM7 tM6 tM4 W/R tM10 tM5 tM2 1 EXCK A1 A0 B7 B1 B0 tM11 tM8 DOUT B7 B1 B0 Figure 8 Serial Control Port Interface 16/24 ¡ Semiconductor MSM7582/7582B FUNCTIONAL DESCRIPTION Control Registers (1) CR0 (basic operation mode setting) CR0 Initial value (*) B7 B6 B5 B4 B3 B2 B1 B0 PS/CS TXC SEL MOD OFF IFSEL 1 IFSEL 0 ENV SEL TEST 1 TEST 0 0 0 0 0 0 0 0 0 * the initial value is set when a reset signal is supplied by a PDN. B7: PS/CS selection 1/CS (4 Clock recovery DPLLs are on.) 0/PS (2 Clock recovery DPLLs are on.) B6: Transmit timing clock selection 0/TXCI input: 384 kHz. TXCO output: 384 kHz output from APLL. Transmit data TXD is input in synchronization with the rising edge of TXCI (APLL is on.) 1/TXCI input: 3.84 MHz. TXCO output: 384 kHz (one-tenth of the TXCI frequency). Transmit data TXD is input in synchronization with the rising edge of TXCO (APLL is off.) B5: Modulation on/off control 1/modulation OFF (with phase fixed) 0/modulation ON. B4, B3: Receiver input IF frequency selection (0, 0), (0, 1): 1.2 MHz (1, 0): 10.8 MHz (1, 1): 10.7 MHz/10.75 MHz B2: Transmit envelope (I2 + Q2 or I2 + Q2 )output selection 1/I2 + Q2 output 0/ I2 + Q2 output B1, B0: Test mode selection bits. Each monitor output is output to the transmit ENV pin. (0, 0): Transmit envelope (I2 + Q2 or I2 + Q2 ) output (0, 1): receiver phase detection signal output (1, 0): receiver delay detection signal output (1, 1): receiver AFC information output 17/24 ¡ Semiconductor MSM7582/7582B (2) CR1 (I, Q gain adjustment) CR1 B7 B6 B5 B4 B3 B2 B1 B0 Ich GAIN3 Ich GAIN2 Ich GAIN1 Ich GAIN0 Qch GAIN3 Qch GAIN2 Qch GAIN1 Qch GAIN0 0 0 0 0 0 0 0 0 Initial value B7 to B4: I+/I– output gain setting, in 3 mV steps (Refer to Table-3.) B3 to B0: Q+/Q– output gain setting, in 3 mV steps (Refer to Table-3.) (3) CR2 (ENV gain adjustment) CR2 B7 B6 B5 B4 B3 B2 B1 B0 ENV GAIN3 ENV GAIN2 ENV GAIN1 ENV GAIN0 — — — — 0 0 0 0 0 0 0 0 Initial value B7 to B4: ENV output gain adjustment (Refer to Table-3.) B3 to B0: Not used Table-3 I, Q, and ENV Output Gain Values CR1-B7 -B6 -B5 -B4 CR1-B3 -B2 -B1 -B0 CR2-B7 -B6 -B5 -B4 Description Amplitude 1.042 ¥ Reference value 0 1 1 1 0 1 1 0 1.036 0 1 0 1 1.030 0 1 0 0 1.024 0 0 1 1 1.018 0 0 1 0 1.012 0 0 0 1 1.006 0 0 0 0 1.000 (Reference value) 1 1 1 1 0.994 1 1 1 0 0.988 1 1 0 1 0.982 1 1 0 0 0.976 1 0 1 1 0.970 1 0 1 0 0.964 1 0 0 1 0.958 1 0 0 0 0.952 18/24 ¡ Semiconductor MSM7582/7582B (4) CR3 (I– output offset voltage adjustment) CR3 B7 B6 B5 B4 B3 B2 B1 B0 Ich Offset4 Ich Offset3 Ich Offset2 Ich Offset1 Ich Offset0 — — — 0 0 0 0 0 0 0 0 Initial value B7 to B3: I– output pin offset voltage adjustment (Refer to Table-4.) B2 to B0: Not used (5) CR4 (Q– output offset voltage adjustment) CR4 B7 B6 B5 B4 B3 B2 B1 B0 Qch Offset4 Qch Offset3 Qch Offset2 Qch Offset1 Qch Offset0 — — — 0 0 0 0 0 0 0 0 Initial value B7 to B4: Q– output pin offset voltage adjustment (Refer to Table-4.) B3 to B0: Not used Table-4 I and Q Channel Offset Adjustment Values CR3-B7 B6 B5 B4 B3 CR3-B7 B6 B5 B4 B3 CR4-B7 B6 B5 B4 B3 CR4-B7 B6 B5 B4 B3 0 1 1 1 1 +45 mV 1 1 1 1 1 0 1 1 1 0 1 1 0 0 +42 mV 1 1 1 1 0 –6 mV 1 +39 mV 1 1 1 0 1 –9 mV 0 1 1 0 1 0 0 0 +36 mV 1 1 1 0 0 –12 mV 1 1 +33 mV 1 1 0 1 1 –15 mV 0 1 0 1 0 +30 mV 1 1 0 1 0 –18 mV 0 0 1 0 0 1 +27 mV 1 1 0 0 1 –21 mV 1 0 0 0 +24 mV 1 1 0 0 0 –24 mV 0 0 1 1 1 +21 mV 1 0 1 1 1 –27 mV 0 0 1 1 0 +18 mV 1 0 1 1 0 –30 mV 0 0 1 0 1 +15 mV 1 0 1 0 1 –33 mV 0 0 1 0 0 +12 mV 1 0 1 0 0 –36 mV 0 0 0 1 1 +9 mV 1 0 0 1 1 –39 mV 0 0 0 1 0 +6 mV 1 0 0 1 0 –42 mV 0 0 0 0 1 +3 mV 1 0 0 0 1 –45 mV 0 0 0 0 0 0 mV 1 0 0 0 0 –48 mV Description Offset Description Offset –3 mV 19/24 ¡ Semiconductor MSM7582/7582B (6) CR5 CR5 Initial value B7 B6 B5 B4 B3 B2 B1 B0 BSTO ENBL ICT6 ICT5 ICT4 LOCAL INV1 LOCAL INV0 CLK SEL1 CLK SEL0 0 0 0 0 0 0 0 0 B7: Modulator burst window output enable bit. 1/The timing of the I and Q baseband modulation output burst is output at the TXCO pin. 0/The 384 kHz transmit timing clock pulse is output at the TXCO pin. B6 to B4: ICT6 to ICT4. Device test control bits. B3, B2: Local inverting mode setting bits. (1, 1) = local inverting mode (0, 0) = normal mode B1: Clock pulse shaping mode selection bit. 1/Clock pulse shaping mode (Refer to Fig 9.) 0/Oscillator circuit mode B0: Power-on control bit for X1, X2 pins, when the clock pulse shaping mode. 1/ Always power-on 0/ Power-down in the whole device power-down state when Power on otherwise. Note: CR5 – B6 to B4 are used to test the device. They should be set to “0” during normal operation. MSM7582/82B TS-K X1 X2 MCK TCXO 19.2 MHz About Pulse shape To other input 0.7 to 1.0 VPP within about 3 VPP of 19.2 MHz Figure 9 Example of Application Circuit when the Clock Pulse Shaping Mode is Generated by CR5-B1 20/24 ¡ Semiconductor MSM7582/7582B State Transition Time Mode A PDN1 = 1 Note: The transition time is 1 ms or less unless otherwise stated 1 ms Mode B 5 ms Standby mode (PDN0 = 0) Communication mode (PDN0 = 1) 40 ms Mode E PDN1 = 1 PDN2 = 0 Mode C PDN1 = 0 PDN2 = 0 PDN1 = 0 PDN2 = 1 5 ms Mode D Mode F PDN1 = 0 PDN2 = 1 PDN1 = 0 PDN2 = 0 5 ms 40 ms Mode G PDN1 = 1 PDN2 = 1 Figure 10 Power-Down State Transition Time 21/24 ¡ Semiconductor MSM7582/7582B APPLICATION CIRCUIT VDD C1 C2 C3 To orthogonal modulator + Modulator I component output Modulator Q component output Power-down control signal 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AGND SG I+ I– Q+ Q– ENV PDN0 PDN1 PDN2 VDD SLS1 SLS2 RCW AFC RPR MSM7582TS-K DGND IFIN TXCI TXCO TXD TXW DEN EXCK DIN DOUT MCK RXD RXC IFCK X2 X1 Demodulator control signal 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 C4 Demodulator IF input Modulator 384 kHz input Modulator input data Modulator data window 19.2 MHz input Receive data output Receive clock output Control register control signal C1 = 10 mF C2 = C3 = 0.1 mF C4 = 1000 pF Figure 11 Example of Circuit Configuration 22/24 ¡ Semiconductor MSM7582/7582B Demodulator Control Timing Diagram (Example) , Democulator unit Modulator input data Slot 1 R1 G Slot 2 G Slot 3 R2 R3 G Slot 4 G R4 G Timing for CS PDN2 SLS2 "0" "0" "1" "1" SLS1 "0" "1" "0" "1" R1 R2 R3 R4 AFC RXD RXC Timing for PS PDN2 SLS2 "0" SLS1 "0" AFC RXD R1 RXC 240 bits 625 ms (1) Control channel / synchronous burst (SS + PR = 64 bits) RXD 64 bits G G G G G G G G R R R R SS SS PR PR PR UW CR CR G G G G G G G G AFC RPR RCW 56 bits (2) When synchronization is not established (for PS only) AFC RPR RCW For PS, the window is initially open to wait for the control signal from CS. RPR is closed after UW is detected. (3) Communication channel (SS + PR = 8 bits) RXD 8 bits G G G G G G G G R R R R SS SS PR PR PR UW CR CR G G G G G G G G AFC RPR "0" RCW When the strength of the received wave is large Less than 30 bits When the strength of the received wave is small. G : R : SS : PR : UW : CR : Guard bit Ramp bit Start symbol bit Preamble bit Unique word bit CRC bit 23/24 ¡ Semiconductor MSM7582/7582B PACKAGE DIMENSIONS (Unit : mm) TSOPI32-P-814-0.50-1K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.27 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 24/24