OKI MSM7662

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¡ Semiconductor
MSM7662
¡ Semiconductor
PEDL7662-02
el
Pr
PEDL7662-02
This version: Oct.
1999
MSM7662
Previous version : Oct. 1998
NTSC/PAL Digital Video Decoder
GENERAL DESCRIPTION
The MSM7662 is an LSI device that decodes NTSC or PAL analog video signals into YCbCr and
RGB digital data based on ITU-RBT.601.
The device has built-in two channels of A/D converters and can accept composite video and S
video signals for the input video signals. Composite video signals are converted to YCbCr and
RGB digital data via the 2-dimensional Y/C separation circuit with an adaptive filter.
Analog video signals can be sampled by a clock at the pixel frequency or at twice the pixel
frequency. A decimation filter is built-in for sampling at twice the pixel frequency.
Input signals are synchronized internally and high-speed locking for color burst is possible.
Because a FIFO buffer is built into the output format circuit, jitter-free output can be obtained
even for non-standard signals.
APPLICATION EXAMPLES
Since the synchronization of input signals and high-speed locking for color burst are possible, the
device is optimized for applications used by switching multiple cameras.
It is also used for various image processing applications because of jitter-free output data
through a built-in FIFO buffer.
8-bit (YCbCr), 16-bit (8-bit (Y) + 8-bit (CbCr)), and 24-bit (RGB) output interfaces can be selected
as an output mode so that various devices such as monitoring system, digital video memory,
digital TV, video processing unit and video communication unit can be selected on the receiving
side.
FEATURES (• new feature not found on MSM7661B)
• Input analog signal
NTSC/PAL composite video signal or S-video signal
• Maximum 5 composite or 2 S-video + 2 composite analog inputs can be connected (switchable
by external pins or internal registers)
• Built-in clamp circuits and video amps
• Built-in 8-bit A/D converters (2 channels)
• 4 selectable output interfaces
ITU-RBT.656 (conditional)
8-bit (YCbCr)
: 8-bit (YCbCr) YCbCr = 4 : 2 : 2/YCbCr = 4 : 1 : 1 (limit)
16-bit (YCbCr) : 8-bit (Y) + 8-bit (CbCr) YCbCr = 4 : 2 : 2/YCbCr = 4 : 1 : 1 (limit)
24-bit RGB
: 8-bit (R) + 8-bit (G) + 8-bit (B)
2-dimensional
Y/C
separation using adaptive comb filter (this filter is bypassed for S-video
°
signal input)
NTSC format: 3 lines or 2 lines, PAL format: 2 lines (3 virtual lines)
• Selectable data I/O signal synchronization
4 synchronization modes, internal FIFO modes (FIFO-1, FIFO-2) and external field memory
modes (FM-1, FM-2), are selectable (FIFO-1 is normally selected).
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PEDL7662-02
¡ Semiconductor
MSM7662
° Compatible pixel frequencies (normal/twice the pixel frequency)
13.5 MHz (13.5/27 MHz)
: NTSC/PAL ITU-RBT.601
12.272727 MHz (12.272727/24.545454 MHz) : NTSC Square pixel
14.31818 MHz (14.31818/28.63636 MHz)
: NTSC 4fsc
14.75 MHz (14.75/29.5 MHz)
: PAL Square Pixel
• Built-in AGC/ACC circuits, compatible with a wide range of input levels
Input level range: –8 dB to +3.5 dB (0.4 V to 1.5 V)
Switchable between AGC/MGC (fixed gain) and ACC/MCC (fixed gain)
° Decimation filter built into input stage, allows easy configuration of filter prior to A/D
converter (when input at twice the pixel frequency)
° Automatic NTSC/PAL recognition (only for ITU-RBT.601)
° Sleep mode
° Multiplex signal recognition (closed caption)
During vertical blanking interval, data is output as 8-bit data.
° I2C-bus interface
° 3.3 V single power supply (I/O 5 V tolerance)
° Package:
100-pin plastic TQFP (TQFP100-P-1414-0.50-K) (Product name: MSM7662TB)
2/62
INS[2:0] GAINS[2:0]
CLKXO
PLLSEL
CLKSEL
VSYNC_L
HSYNC_L
VVALID
HVALID
STATUS1
ODD/EVEN
STATUS3
STATUS2
M[7:4]
Synchronization Block
VRT2
ADIN2
AMPOUT2
CLPOUT2
VRB2
VIN6
VIN5
Decimation
Filter
Luminance Block
DIGITAL
(AGC or MGC + LPF)
Prologue Block
Epilogue
Block
(2 Dim. Y/C separate)
Y ADC
Decimation
Filter
SW Matrix
Output
Formatter
I2C-bus Control Logic
SDA
RESET_L
Test Control Logic
SLEEP
SCAN
TEST[2:0]
8 bits (Y)
8 bits (CbCr)
8 bits (R)
8 bits (G)
8 bits (B)
C[7:0]
(R[7:0])
B[7:0]
MSM7662
3/62
SCL
Y[7:0]
(G[7:0])
Chrominance Block
(ACC or MCC + LPF)
Line Memory
(1 KB) ¥ 2
ANALOG
AGC&
AMP
MODE[3:0]
ITU-656
&
8 bits
(YCbCr)
PEDL7662-02
VIN4
VIN3
VIN2
VIN1
VRB1
CLPOUT1
AMPOUT1
ADIN1
VRCL1
VRT1
M[2:1]
ANALOG
AGC&
AMP
C ADC
¡ Semiconductor
CLKX2
BLOCK DIAGRAM
CLKX2O
PEDL7662-02
,
¡ Semiconductor
MSM7662
76 CLKXO
77 CLKX2O
78 DGND
79 DVDD
80 CLKX2
81 STATUS3
82 STATUS2
83 STATUS1
84 M[7]
85 M[6]
86 M[5]
87 M[4]
88 M[3]
90 M[1]
89 M[2]
91 M[0]
92 DGND
93 DVDD
94 GAINS[2]
95 GAINS[1]
96 GAINS[0]
97 INS[2]
98 INS[1]
99 INS[0]
100 DAGND
PIN CONFIGURATION (TOP VIEW)
DAVDD
1
75 HSYNC_L
VRT2
2
74 VSYNC_L
VIN6
3
73 VVALID
VIN5
4
72 HVALID
ADDD
5
71 ODD/EVEN
AGND
6
70 C[0]
ADIN2
7
69 C[1]
AMPOUT2
8
68 C[2]
CLPOUT2
9
67 C[3]
VRB2 10
66 C[4]
AGND 11
65 C[5]
AGND 12
64 C[6]
VRB1 13
63 C[7]
CLPOUT1 14
62 DGND
AMPOUT1 15
61 DVDD
B[0] 50
B[1] 49
B[2] 48
B[3] 47
B[4] 46
B[5] 45
B[6] 44
B[7] 43
CLKSEL 42
PLLSEL 41
SDA 40
SCL 39
DGND 38
DVDD 37
RESET_L 36
51 DGND
SLEEP 35
52 DVDD
DAVDD 25
TEST[0] 34
53 Y[7]
VRT1 24
TEST[1] 33
54 Y[6]
VIN1 23
TEST[2] 32
55 Y[5]
VIN2 22
SCAN 31
56 Y[4]
VIN3 21
MODE[3] 30
57 Y[3]
VIN4 20
MODE[2] 29
58 Y[2]
AVDD 19
MODE[1] 28
59 Y[1]
AGND 18
DAGND 26
60 Y[0]
VRCL1 17
MODE[0] 27
ADIN1 16
100-Pin Plastic TQFP
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PEDL7662-02
¡ Semiconductor
MSM7662
PIN DESCRIPTIONS
Pin
Symbol
Type
1
DAVDD
—
2
VRT2
O
3
VIN6
I
4
VIN5
I
Description
Digital power supply in A/D converter
A/D converter reference voltage (high side) for S-video chroma signal
S-video 2 chroma signal (C-2) input pin
(leave open or connect to AGND when not used)
Composite-5 or S-video 1 chroma signal (C-1) input pin
(leave open or connect to AGND when not used)
5
AVDD
—
Analog power supply
6
AGND
—
Analog ground
7
ADIN2
I
A/D converter input pin for S-video chroma signal
8
AMPOUT2
O
S-video chroma signal amp output
9
CLPOUT2
O
S-video chroma signal clamp voltage output
10
VRB2
O
A/D converter reference voltage (low side) for S-video chroma signal
11
AGND
—
Analog ground
12
AGND
—
Analog ground
13
VRB1
I
14
CLPOUT1
O
15
AMPOUT1
O
Composite/S-video (luminance signal) amp output
16
ADIN1
I
A/D converter input pin for composite/S-video (luminance signal)
17
VRCL1
I
S-video (luminance signal) clamp voltage input
18
AGND
—
19
AVDD
—
20
VIN4
I
21
VIN3
I
A/D converter reference voltage (low side) for composite/S-video
(luminance signal)
Composite/S-video (luminance signal) clamp voltage output
Analog ground
Analog power supply
Composite-4 input (leave open or connect to AGND when not used)
Composite-3 input (leave open or connect to AGND when not used)
Composite-2 S-video 2 luminance signal (Y-2) input
22
VIN2
I
23
VIN1
I
24
VRT1
O
25
DAVDD
—
Digital power supply in A/D converter
26
DAGND
—
Digital ground in A/D converter
(leave open or connect to AGND when not used)
Composite-1 S-video 1 luminance signal (Y-1) input
(leave open or connect to AGND when not used)
A/D converter reference voltage (high side) for composite/S-video
(luminance signal)
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¡ Semiconductor
MSM7662
PIN DESCRIPTIONS (continued)
Pin
Symbol
Type
27
MODE[0]
I
I/O switching input during external setting mode
Description
28
MODE[1]
I
(pulled-down by internal resistors)
29
MODE[2]
I
Internal/external pins are switched by register MRA[0]
30
MODE[3]
I
The default of register MRA[0] is external pin mode.
MODE [3:2] Output mode selection
00: ITU-RBT.656 (with 8-bit YCbCr SAV, EAV, blank processing)
01: 8-bit (YCbCr)
10: 16-bit (YCbCr) (ITU-RBT.601)
11: 24-bit RGB
MODE [1] Input mode selection
0: NTSC
1: PAL
Invalid if an ITU-RBT.601 signal is input while the register MRC[7] is set
to automatic NTSC/PAL recognition.
MODE [0] Input mode selection
0: ITU-RBT.601 1: Square Pixel
NTSC 4fsc can be set by register MRA [3:1] only.
31
SCAN
I
Not used. Be left open or fixed at "0" (pulled down by internal resistor).
32
TEST[2]
I
Not used. Be left open or fixed at "0" (pulled down by internal resistor).
33
TEST[1]
I
Not used. Be left open or fixed at "0" (pulled down by internal resistor).
34
TEST[0]
I
Not used. Be left open or fixed at "0" (pulled down by internal resistor).
35
SLEEP
I
0: normal operation, 1: sleep operation
36
RESET_L
I
Reset input pin (active "L"). After powering ON, be sure to reset.
37
DVDD
—
Digital power supply
38
DGND
—
Digital ground
39
SCL
I
I2C-bus clock input
40
SDA
I/O
I2C-bus data I/O pin
41
PLLSEL
I
42
CLKSEL
I
Not used. Be left open or fixed at "0" (pulled down by internal resistor).
Clock select input pin (pulled down by internal resistor).
0: double-speed input mode
1: normal input mode
When a double-speed input mode is used, input a double frequency to system clock.
Data output
43 to 50
B[7] to B[0]
O
B[7]: MSB, B[0]: LSB
During RGB output mode: B 8-bit data output
Other than RGB output mode: Hi-Z
Output mode is set by pin 27 or 28, or register MRA [7:6].
51
DGND
—
Digital ground
52
DVDD
—
Digital power supply
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PEDL7662-02
¡ Semiconductor
MSM7662
PIN DESCRIPTIONS (continued)
Pin
Symbol
Type
Description
Data output
Y[7]: MSB, Y[0]: LSB
During ITU-RBT.656 output mode: YCbCr 8-bit data output
53 to 60
Y[7] to Y[0]
O
During 8-bit (YCbCr) output mode: YCbCr 8-bit data output
During 16-bit (YCbCr) output mode: Y 8-bit data output
During 24-bit RGB output mode: G 8-bit data output
Output mode is set by pin 27 or 28, or register MRA [7:6].
61
DVDD
—
Digital power supply
62
DGND
—
Digital ground
Data output
C[7]: MSB, C[0]: LSB
During ITU-RBT.656 output mode: Hi-Z
63 to 70
C[7] to C[0]
O
During 8-bit (YCbCr) output mode: Hi-Z
During 16-bit (YCbCr) output mode: CbCr 8-bit data output
During 24-bit RGB output mode: R 8-bit data output
Output mode is set by pin 27 or 28, or register MRA [7:6].
Field display output
71
ODD/EVEN
O
72
HVALID
O
73
VVALID
O
74
VSYNC_L
O
Vertical sync signal (V sync) output pin
75
HSYNC_L
O
Horizontal sync signal (H sync) output pin
If field is odd, "H" is output.
Horizontal valid pixel timing output pin
If section is valid, "H" is output.
Vertical valid line timing output pin
If section is valid, "H" is output.
Pixel clock output
During double-speed input mode (pin 42 = 0): One half of system clock
76
CLKXO
O
frequency is output.
During normal input mode (pin 42 = 1): The same frequency as system
clock frequency is output.
System clock output
77
CLKX2O
O
78
DGND
—
Digital ground
79
DVDD
—
Digital power supply
System clock input is directly output.
System clock input (selected by operation mode)
80
CLKX2
I
Normal input mode
Double-speed input mode
NTSC ITU-RBT.601
13.5 MHz
27 MHz
NTSC Square Pixel
12.272727 MHz
24.545454 MHz
NTSC 4fsc
14.31818 MHz
28.63636 MHz
PAL ITU-RBT.601
13.5 MHz
27 MHz
PAL Square Pixel
14.75 MHz
29.5 MHz
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PEDL7662-02
¡ Semiconductor
MSM7662
PIN DESCRIPTIONS (continued)
Pin
Symbol
Type
Description
Status signal output
Selected by internal register OMR[0]
81
STATUS[3]
O
OMR[0]: 0
FIFO overflow detection (default)
0: non-detection, 1: detection
OMR[0]: 1
CSYNC output
Status signal output
Selected by internal register OMR[1]
82
STATUS[2]
O
OMR[1]: 0
NTSC-PAL recognition (default)
0: NTSC, 1: PAL
OMR[1]: 1
HLOCK sync detection output
0: non-detection, 1: detection
VBI interval multiplex signal detection output
83
STATUS[1]
O
84
M[7]
O
Field memory control signal; RE output
85
M[6]
O
Field memory control signal; WE output
86
M[5]
O
Field memory control signal; RSTR output
87
M[4]
O
Field memory control signal; RSTW output
88
M[3]
O
Test output pin, normally "L" output
0: non-detection, 1: detection
I2C-bus slave address select
89
M[2]
I
0: 1000001X
1: 1000011X (no internal pull-up or pull-down resistor)
Pin for setting by either external pin or internal register in order to select
analog unit gain value (MGC) and video signal input pin.
(no internal pull-up or pull-down resistor)
0: external pin mode
90
M[1]
I
Gain value setting: pins 94 to 96 (GAINS[2:0]) are used
Input pin setting: pins 97 to 99 (INS[2:0]) are used
1: register mode
Gain value setting: register ADC2[6:4]
Input pin setting: register ADC1[2:0]
Internal register setting is invalid when external pin mode is set.
Selection of external field memory control signal output
91
M[0]
I
If field memory is not used, set M[0] to 0.
0: M[7:4] outputs are invalid
1: M[7:4] outputs are valid
92
DGND
—
Digital ground
93
DVDD
—
Digital power supply
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PEDL7662-02
¡ Semiconductor
MSM7662
PIN DESCRIPTIONS (continued)
Pin
Symbol
Type
94
GAINS[2]
I
Inputs for amplifier gain switch setting during external setting mode
Description
95
GAINS[1]
I
External pin mode: pin 90 (M[1]) = 0
96
GAINS[0]
I
(pulled down by internal resistors)
GAINS[2:0]
Gain value (x times)
[000]
1.00
[001]
1.35
[010]
1.75
[011]
2.30
[100]
3.00
[101]
3.80
[110]
5.00
[111]
Undefined
97
INS[2]
I
Inputs for signal input pin switch setting during external setting mode
98
INS[1]
I
External pin mode: pin 90 (M[1]) = 0
99
INS[0]
I
(pulled down by internal resistors)
INS[2:0]
Input pin
[000]
VIN1 (pin 23) Composite-1
[001]
VIN2 (pin 22) Composite-2
[010]
VIN3 (pin 21) Composite-3
[011]
VIN4 (pin 20) Composite-4
[100]
VIN5 (pin 4) Composite-5
[101]
VIN1 (pin 23) Y-1
VIN5 (pin 4) C-1
[110]
VIN2 (pin 22) Y-2
VIN6 (pin 3) C-2
[111]
100
DAGND
—
Prohibited setting (ADC enters sleep state)
Digital ground in A/D converter
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PEDL7662-02
¡ Semiconductor
MSM7662
ABSOLUTE MAXIMUM RATINGS
Symbol
Condition
Rating
Unit
VDD
Ta = 25˚C
–0.3 to +4.5
V
VI
VDD = 3.3 V
–0.3 to +5.5
V
Power Consumption
PW
—
1
W
Storage Temperature
TSTG
—
–55 to +150
°C
Parameter
Power Supply Voltage
Input Voltage
RECOMMENDED OPERATING CONDITIONS
Symbol
Condition
Min.
Typ.
Max.
Unit
Power Supply Voltage
VDD
—
3.0
3.3
3.6
V
Power Supply Voltage
GND
—
—
0
—
V
VIH1
—
2.2
—
VDD (*2)
V
Parameter
Digital "H" Level Input Voltage
VIH2 (*1)
—
0.8 ¥ VDD
—
VDD (*2)
V
Digital "L" Level Input Voltage
VIL
—
0
—
0.8
V
Analog Video Signal Input
VAIN
0.8
—
1.1
VP-P
0
—
70
°C
Operating Temperature
*1:
*2:
Ta
SYNC tip to white
peak level
—
CLKSEL, SDA, CLKXO
Since the inputs have a tolerance of up to 5.5 V, it is possible to apply 5 V to the inputs.
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PEDL7662-02
¡ Semiconductor
MSM7662
ELECTRICAL CHARACTERISTICS
DC Characteristics
(Ta = 0 to 70°C, VDD (DVDD, ADVDD, AVDD) = 3.3 V ±0.3 V)
Parameter
Symbol
"H" Level Output Voltage
VOH
"L" Level Output Voltage
VOL
Condition
IOH = –4 mA (*1)
IOH = –6 mA (*2)
IOL= 4 mA (*1)
IOL= 6 mA (*2)
VI = GND to VDD
Input Leakage Current
II
Rpull_down =
50 kW (*3)
Min.
Typ.
Max.
Unit
0.7 ¥ VDD
—
VDD
V
0
—
0.4
V
–10
—
+10
mA
20
—
250
mA
IO
VI = GND to VDD
–10
—
+10
mA
SDA Output Voltage
SDAVL
—
0
—
0.4
V
SDA Output Current
SDAIO
—
3
—
—
mA
Output Leakage Current
*1:
*2:
*3:
HSYNC_L, VSYNC_L, SYSSEL, C[7:0], B[7:0], ODD, VVALID, HVALID, CLKXO, HSY,
M[7:0]
Y[7:0], CLKX2O
MODE[3:0], SCAN, TEST[2:0], PLLSEL, CLKSEL, GAINS[2:0], INS[2:0]
DC Characteristics (Analog Unit)
(Ta = 0 to 70°C, VDD (DVDD, ADVDD, AVDD) = 3.3 V ±0.3 V, GND = 0 V)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
AMPOUT Output Voltage
VOAMP
RO = 300 W
0.3
—
2.4
V
CLPOUT Output Voltage
VOCLP
RO = 5 kW
0.2
—
1.6
V
VRT
(*)
2.0
2.3
2.4
V
VRT Output Voltage
VRB Output Voltage
VRB
(*)
0.15
0.3
0.4
V
ADIN
VIADIN
—
VRB
—
VRT
V
VIN
VIVIN
Capacitive coupling
0.4
—
1.3
VP-P
Input Current
IIVIN
VI = 1.5 V
5
—
30
mA
*:
10 kW connected between VRT and VRB
DC Characteristics
(Ta = 0 to 70°C, VDD (DVDD, ADVDD, AVDD) = 3.3 V ±0.3 V, GND = 0 V)
Parameter
Symbol
Condition
Power Supply Current (Operating)
ID1
AD2 off
Min.
Typ.
Max.
Unit
120
150
210
mA
140
170
240
mA
5
mA
AD1 on
CLKX2 = 27 MHz
AD1 on
Power Supply Current (Operating)
ID2
AD2 on
CLKX2 = 27 MHz
Power Supply Current (Sleep)
IDOFF
VI = 1.5 V
0
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PEDL7662-02
¡ Semiconductor
MSM7662
AC Characteristics (Double Speed Mode)
(Ta = 0 to 70°C, VDD (DVDD, ADVDD, AVDD) = 3.3 V ±0.3 V, GND = 0 V)
Parameter
CLKX2 Cycle Frequency
Symbol
1/tCLKX2
Condition
Min.
Typ.
Max.
Unit
ITU-RS601
NTSC 4fsc
—
27.0
—
MHz
—
28.63636
—
MHz
NTSC Square Pixel
—
24.545454
—
MHz
PAL Square Pixel
—
29.5
—
MHz
CLKX2 Duty
tD_D2
—
45
—
55
%
Output Data Delay Time 1 (*)
tOD21
CLKSEL : L
7 (5)
—
26 (24)
ns
Output Data Delay Time 2 (*)
tOD22
CLKSEL : L
6 (4)
—
22 (20)
ns
Output Data Delay Time 3 (*)
tOD23
CLKSEL : L
7 (5)
—
30 (28)
ns
Output Data Delay Time 1X1 (*)
tODX21
CLKSEL : L
2
—
8
ns
Output Data Delay Time 1X2 (*)
tODX22
CLKSEL : L
1
—
5
ns
Output Data Delay Time 1X3 (*)
tODX23
CLKSEL : L
2
—
10
ns
Output Data Delay Time 2X1 (*)
tOD2X21
CLKSEL : L
3 (1)
—
11 (9)
ns
Output Data Delay Time 2X2 (*)
tOD2X22
CLKSEL : L
2 (1)
—
9 (7)
ns
Output Data Delay Time 2X3 (*)
tOD2X23
CLKSEL : L
3 (1)
—
13 (11)
ns
tCXD21
CLKSEL : L
5
—
20
ns
tCXD22
CLKSEL : L
4
—
17
ns
SCL Clock Cycle Time
tC_SCL
Rpull_up = 4.7 kW
200
—
—
ns
SCL Low Level Cycle
tL_SCL
Rpull_up = 4.7 kW
100
—
—
ns
RESET_L Width
tRST_W
200
—
—
ns
Output Clock Delay Time (*)
(CLKX2-CLKXO)
Output Clock Delay Time (*)
(CLKX2-CLKX2O)
(*) Output load: 40 pF
Values in the parentheses indicate the delay time when 8-bit YCbCr format data is output from the Y pin.
The clock frequency accuracy is within ±100 ppm.
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PEDL7662-02
¡ Semiconductor
MSM7662
AC Characteristics (Single Speed Mode)
(Ta = 0 to 70°C, VDD (DVDD, ADVDD, AVDD) = 3.3 V ±0.3 V, GND = 0 V)
Parameter
CLKX2 Cycle Frequency
Symbol
1/tCLKX2
Condition
Min.
Typ.
Max.
Unit
ITU-RS601
NTSC 4fsc
—
13.5
—
MHz
—
14.31818
—
MHz
NTSC Square Pixel
—
12.272727
—
MHz
PAL Square Pixel
—
14.75
—
MHz
CLKX2 Duty
tD_D1
CLKSEL : H
40
60
%
Output Data Delay Time 1 (*)
tOD11
CLKSEL : H
8
—
26
ns
Output Data Delay Time 2 (*)
tOD12
CLKSEL : H
7
—
22
ns
Output Data Delay Time 3 (*)
tOD13
CLKSEL : H
8
—
30
ns
Output Data Delay Time 1X1 (*)
tODX11
CLKSEL : H
2
—
8
ns
Output Data Delay Time 1X2 (*)
tODX12
CLKSEL : H
1
—
5
ns
Output Data Delay Time 1X3 (*)
tODX13
CLKSEL : H
2
—
12
ns
Output Data Delay Time 2X1 (*)
tOD2X11
CLKSEL : H
3
—
11
ns
Output Data Delay Time 2X2 (*)
tOD2X12
CLKSEL : H
2
—
8
ns
Output Data Delay Time 2X3 (*)
tOD2X13
CLKSEL : H
3
—
15
ns
tCXD11
CLKSEL : H
6
—
20
ns
tCXD12
CLKSEL : H
5
—
17
ns
tC_SCL
Rpull_up = 4.7 kW
200
—
—
ns
SCL Low Level Cycle
tL_SCL
Rpull_up = 4.7 kW
RESET_L Width
tRST_W
Output Clock Delay Time (*)
(CLKX2-CLKXO)
Output Clock Delay Time (*)
(CLKX2-CLKX2O)
SCL Clock Cycle Time
100
—
—
ns
200
—
—
ns
(*) Output load: 40 pF
The clock frequency accuracy is within ±100 ppm.
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INPUT AND OUTPUT TIMING
Clock and Output Timing
CLKSEL: H
tCLKX1
CLKSEL: L
tCLKX2
CLKX2
tCXD21
tCXD22
CLKX2O
tCXD11
CLKXO
tCXD21
tOD11
tOD2X11
tOD21
tOD2X21
tODX11
tODX21
tOD12
tOD2X12
tOD22
tOD2X22
HVALID, VVALID,
ODD
HSYNC_L,
VSYNC_L
tODX12
tODX22
tOD13
tOD2X13
tOD23
tOD2X23
STATUS[3:1]
M[7:4]
tODX13
tODX23
Y[7:0], C[7:0]
B[7:0]
Data Delay (when a standard signal is input)
Analog Video In
Data delay
Blank delay
Decoder output
Blank
Active Data
T = 1 pixel rate, a = absorption difference
Video Mode
Input Signal
FIFO/FM Mode
Amount of Delay
NTSC
Composite
FIFO-1
1H + 358T ±a
NTSC
Composite
FM
1H + 358T
PAL
Composite
FIFO-1
1H + 358T ±a
PAL
Composite
FM
1H + 358T
NTSC, PAL
S-Video
FIFO-1
358T ±a
NTSC, PAL
S-Video
FM
358T
The data delay is equal to the blank delay. 1H depends on the sampling mode.
The numeric value (T value) may be changed according to a signal state.
Since the output period is fixed during FIFO mode, the amount of delay is changed.
If Y/C separation is performed using TRAP filter during PAL mode, 1H is not added.
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I2C-bus Interface Input/Output Timing
The basic input/output timing of the I2C-bus is indicated below.
SDA
MSB
SCL
S
1
2
7
8
Start condition
Data line stable: data valid
9
ACK
1
tC_SCL
2
9
ACK
3-8
P
Stop condition
Change of data allowed
I2C-bus Timing
SDA
tBFU
SCL
P
tR
tF
tHD:STA
S
S
P
tSU:STA
tSU:STO
tHD:STA
tLOW
tHD:DAT
tHIGH
Symbol
tSU:DAT
Parameter
Min.
Max.
Unit
0
100
kHz
fSCL
SCL Frequency
tBUF
Bus Open Period
4.7
ms
Start Condition Hold Time
4.0
ms
tLOW
Clock Low Period
4.7
ms
tHIGH
Clock High Period
4.0
ms
tHD: STA
tSU: STA
Start Condition Setup Time
4.7
ms
tHD: DAT
Data Hold Time
300
ns
tSU: DAT
Data Setup Time
250
tR
Line Rise Time
tF
Line Fall Time
tSU: STO
Stop Condition Setup Time
ns
1
300
4.7
ms
ns
ms
The I2C-bus timing conforms to this table. However, the I2C-bus can operate faster than at the
speeds, specified above. Actually, the SCL frequency is up to about 5 MHz. The hold time and
setup time in that case must conform to the ratio described in the above table.
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FUNCTIONAL DESCRIPTION
Analog Unit
1) Analog input select: Compatible with composite video signals and S-video signals. Input
selection can be switched by register control via the I2C-bus or by
external pins. (See the below chart for pin combinations.)
2) Clamp function:
An analog clamp and a digital pulse clamp can be used.
Analog clamp
Analog clamp Æ Digital clamp (hybrid clamp)
Digital clamp
Only the digital clamp can be set as the pedestal clamp.
# Related register MRB[3:2]
3) AGC amp:
The AGC function operates depending upon the input level.
Manual gain setting is also possible. This AGC function operates at 2
stages, the analog unit and digital unit. Digital decoded data is output
in conformance with ITU-RBT.601.
Refer to the explanation of M[1] pin (pin 90).
# Related register ADC2[6:4]
4) A/D converter:
Two internal 8-bit A/D converters sample at twice the pixel frequency.
(Sampling at the pixel frequency is possible by changing the register
setting.)
# Related register ADC1[2:0]
List of Analog Input Conditions
Input Signal
Control Pin Register
Input Pin
INS[2:0] ADC1[2:0] VIN1
Composite-1 Input*
[000]
[000]
Composite-2 Input
[001]
[001]
Composite-3 Input
[010]
[010]
Composite-4 Input
[011]
[011]
Composite-5 Input
[100]
[100]
S-video-1 Input
[101]
[101]
S-video-2 Input
[110]
[110]
All inputs Off
[111]
[111]
VIN2
VIN3
VIN4
ADC Selection
VIN5
VIN6
Composite
Composite
Composite
Composite
Luminance
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
Composite
ON
OFF
Chroma
ON
ON
Luminance
Chroma
OFF (Sleep)
ON
ON
OFF
OFF
Blank spaces: non-selectable
*: register default setting after LSI reset
M[1] pin setting
0: external mode, 1 internal register mode
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Manual Gain Control (analog AMP gain)
Gain Setting Pins
Register
Set Gain Value
GAINS[2:0]
ADC2[6:4]
Typ. Value (multiplication factor)
[000]
[000]
1.0
[001]
[001]
1.35
[010]
[010]
1.75
[011]
[011]
2.3
[100]
[100]
3.0
[101]
[101]
3.8
[110]
[110]
5.0
[111]
[111]
Undefined
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MSM7662
Decoder Unit
1. Prologue Block
The prologue block inputs data and performs Y/C separation.
Data can be input at either the pixel frequency (ITU-RBT.601: 13.5 MHz) or at twice the pixel
frequency (ITU-RBT.601: 27 MHz). If input at twice the pixel frequency, data is processed after
passing through a decimator circuit to convert it to the pixel frequency. The decimator circuit
may be bypassed by changing the register setting, regardless of whether data is input at the
normal pixel frequency or at twice the pixel frequency.
If a composite signal (CVBS) is input, the default setting performs Y/C separation using a 2dimensional adaptive comb filter.
The following operating modes can be selected via the I2C-bus. Default settings are indicated by
an asterisk (*). The default state is selected at reset.
1) Video input mode selection (related register MRC[7])
NTSC/PAL auto-select* (only for ITU-RBT.601)
Dependent upon operating mode selected
When ITU-RBT.601 is selected, the video input mode is automatically set depending upon
the number of lines per field.
2) Operating mode selection (related register MRA[3:1])
NTSC ITU-RBT.601
13.5 MHz*
NTSC Square Pixel
12.272727 MHz
NTSC 4fsc
14.31818 MHz
PAL ITU-RBT.601
13.5 MHz
PAL Square Pixel
14.75 MHz
Even if input at twice the pixel frequency, the internal processing is performed at the pixel
frequency.
3) Decimator circuit pass/bypass selection (related register MRC[4])
Pass through decimator circuit*
Bypass decimator circuit
Compatible only when input at twice the pixel frequency.
4) Y/C separation mode selection (related register MRB[1:0])
Use adaptive comb filter*
Use non-adaptive comb filter
Do not use comb filter (use trap filter)
The adaptive comb filter for a NTSC signal makes the correlation between up to 3 consecutive
lines, and Y/C separation is performed by the 3-line or 2-line comb filter according to the format
of correlation.
The adaptive comb filter for a PAL signal makes the correlation between only 2 lines and
performs Y/C separation by switching between the 2-line comb filter and trap filter.
The non-adaptive comb filter performs Y/C separation by removing the luminance component
based on the average of preceding and following lines (when there is correlation between 3 lines).
(the average of 2 lines in the case of a PAL signal)
When a comb filter is not used, Y/C separation is performed by a trap filter.
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If an S-video signal is input, these Y/C separation circuits are bypassed.
The functions of this block only operate when lines are valid as image information. During the
V blanking interval, CVBS signals are not processed.
2. Luminance Block
The luminance block removes synchronous signals from signals containing luminance components
after Y/C separation. The signals are compensated and then output as luminance signals. Two
modes of gain control functions can be selected for the luminance signal output level: AGC (Auto
Gain Control) and MGC + Pedestal Clamp.
In the AGC mode, luminance level amplification is determined by comparing the SYNC depth
with a reference value. The default is 40IRE and can be changed by the register setting. The input
has a sync tip clamp.
In the MGC + Pedestal Clamp mode, the signal output level is clamped to the pedestal level of
the input. Signal amplification and black level can be changed from the clamped position by
register settings.
This block can select the follwing operating modes.
1) Selection of luminance level limiter usage (related register LUMC[7])
Do not use*
Use
When a limiter is used, the luminance level is limited to 16 to 235.
2) Selection of prefilter and sharp filter usage (related register LUMC[6])
Do not use*
Use
These filters are used to enhance the edges of luminance component signals.
Two filters operate in pairs. For their characteristics, refer to Filter Characteristics described
later.
3) Selection of aperture bandpass filter coefficient (related register LUMC[5:4])
Middle range*
High range
4) Coring range selection (related register LUMC[3:2])
Off*
±4LBS
±5LBS
±7LBS
5) Aperture weighting coefficient selection (related register LUMC[1:0])
0*
0.25
0.75
1.50
Both coring and aperture compensation processes perform contour compensation.
6) Selection of pixel position compensating circuit usage (related register MRC[6])
Use*
Do not use
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7) AGC loop filter time constant selection (related register AGCLF[7:6])
Slow
convergence time
903 ms
Medium
225 ms*
Fast
56 ms
Fixed
0
These are designed times from the input gain being rapidly lowered to 50% (–6 dB) of the
value at a stable state when normal signals are input till the output being returned to –1 dB
(actually these times differ depending on the signal state).
Fixed: manual gain setting is possible by register AGCLF[5:0]
8) Parameter for fine adjustment of AGC sync depth (related register AGCLF[5:0])
AGC reference level is changed.
9) Parameter for fine adjustment of sync removal level (related register SSEPL[6:0])
The black level is adjusted. The default setting outputs the pedestal position as a black level
(=16).
10)Pedestal clamp selection (related register SSEPL[7])
Do not use pedestal clamp*
Use pedestal clamp (at this time, AGC does not operate, MGC operates)
3. Chrominance Block
This block processes the chroma signals.
The following operating modes can be selected.
1) Selection of chroma bandpass filter usage (related register CHRC[2])
Do not use*
Use
2) ACC loop filter time constant selection (related register ACCLF[6:5])
Slow
convergence time
1696 ms
Medium
424 ms*
Fast
106 ms
Fixed
0
These are designed times from the input gain being rapidly lowered to 50% (–6 dB) of the
value at a stable state when normal signals are input till the output being returned to –1 dB
(actually these times differ depending on the signal state).
Fixed: manual gain setting is possible by register ACCLF[4:0]
3) ACC reference level fine adjustment (related register ACCLF[4:0])
ACC reference level is changed.
4) Parameter for burst level fine adjustment (related register CHRC[1:0])
Threshold level at which chroma amplitude becomes valid is selected based upon color burst
ratio.
0.5
0.25*
0.125
Off
Off: The color killer function is turned off. If decoloration occurs while decoding a still picture,
setting the threshold level to "off" will reduce the decoloration.
5) Color killer mode selection (related register MRB[5])
Auto color killer mode*
Forced color killer
6) Parameter for fine adjustment of color subcarrier phase (related register HUE[7:0])
HUE control function
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In this block, chroma signals pass through a bandpass filter to cut out unnecessary band.
To maintain a constant chroma level, these signals then pass through an ACC compensating
circuit and are UV demodulated. (The filter can be bypassed.)
If the demodulated result does not reach a constant level, color killer signals are generated to fix
the ACC gain. This functions as an auto color killer control circuit.
The UV demodulated results pass through a low-pass filter and are output as chrominance
signals.
4. Synchronization Block
This block processes the sync signals. Synchronous signals are generated for chip output and for
internal use. Various signals are output from this block and the following operating modes can
be selected.
1) Adjustment of SYNC threshold level (internal sync) (related register STHR[7:0])
SYNC detection level is set.
2) Fine adjustment of HSY (Horizontal Sync Clamp) signal (related registers HSYT[7:4], HSYT[3:0],
MRB[3:2])
2-1) Fine adjustment of HSY signal (start side)
2-2) Fine adjustment of HSY signal (stop side)
The HSY signal provides the sync-tip and clamp timing to the A/D converter.
This signal is used for digital clamp, but can not be observed from outside.
3) Fine adjustment of HSYNC_L signal (related register HSDL[7:0])
HSYNC_L signal output position is adjusted.
4) HVALID control (related registers HVALT[7:4], HVALT[3:0])
4-1) Fine adjustment of HVALID signal (start side)
4-2) Fine adjustment of HVALID signal (stop side)
Data signals are transferred at the rising edge of the HVALID signal.
5) VVALID control (related registers VVALT[7:4], VVALT[3:0])
5-1) Fine adjustment of VVALID signal (start side)
5-2) Fine adjustment of VVALID signal (stop side)
6) FIFO and Field Memory mode selection (related register MRB[7:6])
FIFO-1 mode*: Sets and outputs a standard value for the number of pixels per 1H from the
internal FIFO.
This mode is also compatible (to a degree) with non-standard VTR signals.
FIFO-2 mode: Sets and outputs a constant pixel number corresponding to the input H
interval for the number of pixels per 1H from the internal FIFO.
FM-1 mode: This mode outputs the decoded results according to the SYNC signal.
Usage of external field memory is required to manage the number of pixels
and to absorb jitter.
Memory control signals are to be generated externally.
FM-2 mode: This mode is compatible with considerably distorted non-standard VTR
signals. Jitter is absorbed by using external field memory (2 Mb ¥ 2) and the
standard value is set as the pixel number.
Field memory control signals are output simultaneously from M[7:4].
7) Field memory control signals
If the FM-2 mode uses external field memory (2 Mb ¥ 2) instead of the internal FIFO, field
memory control signals are supplied from pins M[7:4]. At this time, pin M[0] requires to be
set to "H".
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MSM7662
5. Epilogue Block
The Epilogue Block outputs the UV signal from the Chrominance block and the Y signal from the
Luminance block in a format based on a signal obtained from the control register setting.
This block can select the following modes.
1) Output mode selection (related register MRA[7:6])
1-1) ITU-RBT.656 (SAV, EAV, blank processing)
1-2) * 8-bit (YCbCr) output (2x pixel clock)
synchronization with HSYNC_L, VSYNC_L
1-3) 16-bit (8-bit Y/8-bit CbCr) (pixel clock)
synchronization with HSYNC_L, VSYNC_L
1-4) 24-bit RGB (8 bits each)
synchronization with HSYNC_L, VSYNC_L
2) Enable Blue Back display when synchronization fails (related register MRB[4])
OFF
ON*
If "H" is not input when no signal is output or when synchronization fails, a vertical
synchronizing signal (VSYNC_L) is not output.
3) Selection of YCbCr signal output format (related register MRC[5])
YCbCr
4 : 2 : 2*
YCbCr
4:1:1
The chrominance signal (U, V component) outputs Cb and Cr data to the C pin in an output
format to be described later.
4) Output pin enable selection (related register OMR[2])
High-impedance
Output enable*
This setting is valid during sleep mode only.
All the data output pins and sync signal output pins become high impedance.
5) Multiplex signal (VBI data) detection level adjustment (related register OMR[5:3])
The levels to detect multiplexed signals sent during the vertical blanking period are
configured to be variable. The binary values after input signals are A-to-D converted are
employed as the levels to detect multiplexed signals, and the levels are set in eight steps on
the basis of a value obtained from reducing the SYNC tip level to 0.
6) Various mode detection (related register OMR[1:0])
NTSC/PAL detection
Multiplex signal detection
HSYNC synchronization detection
Internal FIFO overflow detection
7) Output signal phase control (related registers OPCY[1:0], OPCC[1:0])
Y and C phases can each be adjusted in the range of –2 to +1 pixels.
6. I2C Control Block
This serial interface block is based on the I2C standard of the Phillips Corporation.
The registers at up to subaddress Hex14 are write-only registers and the register at subaddress
Hex20 is a read-only register.
The license to use the LSI chip for I2C systems is granted on the basis of the I2C patent of the
Phillips Corporation by purchasing the LSI chip.
7. Test Control Block
This block is used to test the LSI chip. Normally this block is not used.
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MSM7662
Input Signal Level
The figure below shows the recommended range of the input signal, received in an 8-bit straight
binary format.
255
reserved
246
200
chrominance
+DC
Iuminance
NTSC:60
(PAL:63)
input black level
sync
4
0
13
input sync-tip level
CVBS[7:0] input range
The above input conditions are ideal. Because analog signals are normally input at different
levels, the exact settings described above are difficult to achieve. While maintaining the ratio of
White Peak (100%)/SYNC = 100IRE/40IRE (NTSC), if the input signal is set within the A/D
converter's voltage range/the Y digital output will be output by digital AGC operation with the
pedestal position set at the black level (16) and the white peak position (100%) set at the peak level
(235) even if the peak level does not reach 196 (200 – 4).
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MSM7662
Output format
ITU-RBT.656 output, 8-bit (YCbCr) output, and 16-bit (8-bit Y/8-bit CbCr) output have the
following formats.
The YCbCr 4:2:2 format and 4:1:1 format are shown below.
The output format can be changed by register settings.
Output
Pixel Byte Sequence
Output
Pixel Byte Sequence
Y7 (MSB)
Y6
Y5
Y4
Y3
Y2
Y1
Y0 (LSB)
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y7 (MSB)
Y6
Y5
Y4
Y3
Y2
Y1
Y0 (LSB)
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
C7 (MSB)
C6
C5
C4
C3
C2
C1
C0 (LSB)
Cb7
Cb6
Cb5
Cb4
Cb3
Cb2
Cb1
Cb0
Cr7
Cr6
Cr5
Cr4
Cr3
Cr2
Cr1
Cr0
Cb7
Cb6
Cb5
Cb4
Cb3
Cb2
Cb1
Cb0
Cr7
Cr6
Cr5
Cr4
Cr3
Cr2
Cr1
Cr0
Cb7
Cb6
Cb5
Cb4
Cb3
Cb2
Cb1
Cb0
Cr7
Cr6
Cr5
Cr4
Cr3
Cr2
Cr1
Cr0
C7 (MSB)
C6
C5
C4
C3
C2
C1
C0 (LSB)
Cb7
Cb6
Cr7
Cr6
0
0
0
0
Cb5
Cb4
Cr5
Cr4
0
0
0
0
Cb3
Cb2
Cr3
Cr2
0
0
0
0
Cb1
Cb0
Cr1
Cr0
0
0
0
0
Cb7
Cb6
Cr7
Cr6
0
0
0
0
Cb5
Cb4
Cr5
Cr4
0
0
0
0
Cb3
Cb2
Cr3
Cr2
0
0
0
0
Cb1
Cb0
Cr1
Cr0
0
0
0
0
0
1
2
3
4
5
0
1
2
3
4
5
6
7
Y point
C point
0
2
YCbCr 4:2:2 format
4
Y point
C point
0
4
YCbCr 4:1:1 format
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MSM7662
TIMING DESCRIPTION
Vertical Synchronizing Signal
The vertical synchronizing signal timing is as follows. The default output is as shown below, but
the internal processing of the synchronizing signal is performed before 1H.
524
525
1
2
3
4
5
6
7
8
262
263
264
265
266
267
268
269
270
271
9
21
22
284
285
CVBS
HVALID
HSYNC_L
VSYNC_L
CSYNC_L
VVALID
ODD
283
CVBS
HVALID
HSYNC_L
VSYNC_L
CSYNC_L
VVALID
ODD
Vertical Synchronizing Signal (60 Hz)
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MSM7662
621
622
623
624
625
1
2
3
4
5
309
310
311
312
313
314
315
316
317
318
6
23
24
337
338
CVBS
HVALID
HSYNC_L
CSYNC_L
VSYNC_L
VVALID
ODD
336
CVBS
HVALID
HSYNC_L
CSYNC_L
VSYNC_L
VVALID
ODD
Vertical Synchronizing Signal (50 Hz)
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A/D Converter Support Signal
The waveform of the HSY signal, shown below, provides clamp timing to the A/D converter
when HSY clamp (digital clamp) is selected. The start and end edges of the clamp pulse have a
variable range from the sync tip to the pedestal position. (HSY is an internal signal.)
CVBS
BURST
COLOR
BURST
sync tip
Pedestal
HSY
A/D Converter Support Signal
Output Timing
• ITU-RBT.656 output
T : clock periods 37 ns normal (1/27 MHz)
SAV : start of active video timing reference code
EAV : end of active video timing reference code
Digital line {1716T (NTSC, 525), 1728T (PAL, 625)}
EAV
SAV
EAV
4T
Multiplexed video data
Cb0 Y00 Cr0 Cb1 Y10 Cr1 Y11
4T
Digital line blanking
Digital active line
276T (NTSC, 525)
288T (PAL, 625)
Video data block (1440T)
ITU-RBT.656 Output (Data in one line in which video data presents)
During the blanking interval, data is output with the Y value.
Note:
Digital line 1716T (NTSC, 525) and 1728T (PAL, 625) are not maintained at the next line.
Digital active line 1440T of the line immediately after VVALID falls and the 10th or 11th
line after VSYNC_L rises will fluctuate due to pixel compensation. Especially when a
non-standard signal is input, the line immediately after VVALID falls will fluctuate
largely due to instability of the input signal. Due to phenomena such as an increase in
the number of lines for a standard signal and a decrease in the number of lines for a nonstandard signal, it may not be possible to guarantee correct EAV and SAV functionality.
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MSM7662
Contents of SAV and EAV
Both SAV and EAV consist of 4 words. Their configuration is shown below.
Word
First
Bit No.
7 (MSB)
6
5
4
3
2
1
0 (LSB)
1
1
1
1
1
1
1
1
Second
0
0
0
0
0
0
0
0
Third
0
0
0
0
0
0
0
0
Fourth
1
F
V
H
P3
P2
P1
F = 0: during field 1
1: during field 2
V = 0: elsewhere
1: during field blanking
H = 0: SAV H = 1: EAV
P0
P3, P2, P1, P0: Protection bit
The 4th word of SAV and EAV
The relationship between the F, V, H and Protection bits in the 4th word of SAV and EAV
is shown below.
Bit No.
7 (MSB)
6
5
4
3
2
1
0
Function
0
Fixed 1
F
V
H
P3
P2
P1
P0
1
0
0
0
0
0
0
0
1
1
0
0
1
1
1
0
1
2
1
0
1
0
1
0
1
1
3
1
0
1
1
0
1
1
0
4
1
1
0
0
0
1
1
1
5
1
1
0
1
1
0
1
0
6
1
1
1
0
1
1
0
0
7
1
1
1
1
0
0
0
1
Usually, V = 1 during blanking, however when VBI data is detected and V = 0 is the desired
output, set the MRC[3] SAV, EAV V-status of Mode Register C (MRC) to "1".
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Output Data Format
CLKX2
HVALID
Y[7:0]
Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 Cb4
Cr n–4 Y n–3 Cb n–2 Y n–2 Cr n–2 Y n–1
8-bit (YCbCr: 2x clock) Output
CLKX2
CLKO
HVALID
Y[7:0]
Y0
Y1
Y2
Y3
Y(n–2)
Y(n–1)
C(7:0)
Cb0
Cr0
Cb2
Cr2
Cb(n–2) Cr(n–2)
16-bit (Y: 8-bit, CbCr: 8-bit) Output
CLKX2
CLKO
HVALID
R[7:0]
R0
R1
R2
R3
R(n–2)
R(n–1)
G[7:0]
G0
G1
Cb2
Cr3
G(n–2)
G(n–1)
B[7:0]
B0
B1
B2
B3
B(n–2)
B(n–1)
24-bit (R: 8-bit, G: 8-bit, B: 8-bit) Output
Note:
When a single-speed clock (13.5 MHz, etc.) is input in 16-bit or 24-bit (RGB) output
mode, the waveform of CLKX2 changes to a single speed waveform, but the format
after that is not changed.
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• Timing when using external field memory
Field memory timing in the FM-2 mode, using control signals from the decoder
Field memory: MSM51V8222, 2 units are used (Y and C)
Four memory control signals are supplied from the decoder, M[4]: RSTW, M[5]: RSTR, M[6]:
WE:, and M[7]: RE.
NTSC Signal (13.5 MHz)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
hsync_l
vsync_l
hvalid
vvalid
odd-even
y (7:0)
c (7:0)
RSTW
WE
HSYNC_L
VSYNC_L
HVLID
VVALID
ODD/EVEN
RE
RSTR
Y (7:0)
C (7:0)
NTSC: ODD Field
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
hsync_l
vsync_l
hvalid
vvalid
odd-even
y (7:0)
c (7:0)
RSTW
WE
HSYNC_L
VSYNC_L
HVLID
VVALID
ODD/EVEN
RE
RSTR
Y (7:0)
C (7:0)
NTSC: EVEN Field
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PAL Signal (13.5 MHz)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 31 32 33 34 35 36 37 38 39
hsync_l
vsync_l
hvalid
vvalid
odd-even
y (7:0)
c (7:0)
RSTW
WE
HSYNC_L
VSYNC_L
HVLID
VVALID
ODD/EVEN
RE
RSTR
Y (7:0)
C (7:0)
PAL: ODD Field
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 31 32 33 34 35 36 37 38
hsync_l
vsync_l
hvalid
vvalid
odd-even
y (7:0)
c (7:0)
RSTW
WE
HSYNC_L
VSYNC_L
HVLID
VVALID
ODD/EVEN
RE
RSTR
Y (7:0)
C (7:0)
PAL: EVEN Field
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Horizontal Synchronizing Signal
The horizontal synchronizing signal timing is shown below.
Front-porch
Hsync back-porch
Y[7:0]
HVALID
HSYNC_L
60 pixels
Horizontal Timing
Relation between Video Mode and Pixel Number (default settings when standard signal is input)
Video
Mode
NTSC
PAL
Pixel
Pixel Rate
Total
Active
Front-
Hsync Back-
HBLK
Type
(MHz)
Pixels
Pixels
Porch
Porch
Total
ITURBT.601
13.5
858
720
16
122
138
Square pixel
12.272727
780
640
28
112
140
4fsc
14.31818
910
768
8
134
142
ITURBT.601
13.5
864
720
12
132
144
Square pixel
14.75
944
768
34
142
176
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MSM7662
Synchronizing Signal Timing (default timing when standard signal is input)
0
2T
T = 1/13.5 MHz
HVALID
VVALID
60 pixels
HSYNC_L
138 pixels
16 pixels
HVALID
0
HSYNC_L
VSYNC_L
about 10.4 ms
ODD
(ODD)
about 21.6 ms
ODD
(EVEN)
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VBI Data Detection (when a Composite signal is input): STATUS1 Timing
VBI data detection results are output from the STATUS1 pin.
Detection level
OMR[5:3]
80 to 136
video in
STATUS1
HVALID
HSYNC_L
Y[7:0]
VBI Data Detection (when an S-Video signal is input): STATUS1 Timing
VBI data detection results are output from the STATUS1 pin.
Detection level
OMR[5:3]
80 to 136
video in
STATUS1
HVALID
HSYNC_L
Y[7:0]
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I2C BUS FORMAT
The I2C-bus interface input format is shown below.
Write Mode
S
Slave Addres (W)
A
Subaddress
A
A
Subaddress
A
Data 0
A
......
Data n
A
P
A
Data 20
A
P
Read Mode
S
Slave Addres (W)
S
Slave Addres (R)
Symbol
Description
S
Start condition
Slave Address
Slave address 1000001X, 8th bit is write signal ["0"] or read signal ["1"]
Slave address is set at M[2] pin (pin 89).
A
Acknowledge. Generated by slave
Subaddress
Subaddress byte
Data n
Data to write to address designated by subaddress.
P
Stop condition
As mentioned above, the write operation can be executed from subaddress to subaddress
continuously. When the write operation is executed at subaddresses discontinuously, the
Acknowledge and Stop condition formats are input repeatedly after Data 0.
Data can be read at subaddress 0x20 only.
If one of the following matters occurs, the decoder will not return "A" (Acknowledge).
• The slave address does not match.
• A non-existent subaddress is specified.
• The write attribute of a register does not match "X" (read ["1"]/write ["0"] control bit).
The input timing is shown below.
SDA
1
2
8
ACK
1
2
8
ACK
1
2
8
ACK
SCL
S
Start Condition
Slave Address
Sub Address
P
Data
Stop Condition
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OPERATING MODE SETTING
There are two types of video mode settings.
1. External pin mode: direct setting from dedicated pins
2. Register setting mode: specification by internal register settings
These modes can be switched by the mode register MRA[0].
The reset state (default) is the external pin mode.
The following registers can be set in the external pin mode.
MRA[7:6]
Output mode
MRA[3:1]
Sampling mode
Note:
00: ITU-RBT.656 (SAV, EAV, blank processing)
*01: 8 bit (YCbCr)
HSYNC_L and VSYNC_L used for synchronization
10: ITU-RBT.601 16 bit (8 bit Y, 8 bit CbCr)
11: RGB (8 bit R, 8 bit G, 8 bit B)
*000: NTSC ITU-RBT.601
13.5 MHz (27.0 MHz)
001: NTSC Square Pixel 12.272727 MHz (24.545454 MHz)
010: NTSC 4fsc
14.31818 MHz (28.63636 MHz)
100: PAL ITU-RBT.601
13.5 MHz (27.0 MHz)
101: PAL Square Pixel
14.75 MHz (29.5 MHz)
010: NTSC 4fsc cannot be set externally.
Pin Setting Example
NTSC, 27 MHz (ITU-RBT.601), Composite input, 8-bit (YCbCr) Output
Pin name
Condition
Notes
MODE[3]
= low
0 : ITU-RBT.656 01 : 8-bit (YCbCr)
MODE[2]
= high
10 : 16-bit (Y + CbCr) 11 : RGB
MODE[1]
= low
0 : NTSC 1 : PAL
MODE[0]
= low
0 : ITU-RBT.601 1 : Square Pixel
CLKSEL
= low
0 : twice the pixel frequency 1 : pixel frequency
PLLSEL
= low
INS[2:0]
= low
GAINS[2:0]
= low
TEST[2:0]
= low
SCAN
= low
M[2]
= low
M[1]
= low
M[0]
= low
SLEEP
= low
Normally set to a low level
: low = 1000001, : high = 1000011
Normally set to a low level
0 : normal operation 1 : sleep operation
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MSM7662
INTERNAL REGISTERS
Register List
Register Function
Write Sub/Read address
Data byte
D7
D6
D5
D4
D3
D2
D1
D0
Mode Register A (MRA)
Write
0
MRA7 MRA6 MRA5 MRA4 MRA3 MRA2 MRA1 MRA0
Mode Register B (MRB)
Write
1
MRB7 MRB6 MRB5 MRB4 MRB3 MRB2 MRB1 MRB0
Mode Register C (MRC)
Write
2
MRC7 MRC6 MRC5 MRC4 MRC3 MRC2 MRC1 MRC0
Horizontal Sync Trimmer (HSYT)
Write
3
HSYT7 HSYT6 HSYT5 HSYT4 HSYT3 HSYT2 HSYT1 HSYT0
Sync Threshold Level Adjust (STHR)
Write
4
STHR7 STHR6 STHR5 STHR4 STHR3 STHR2 STHR1 STHR0
Horizontal Sync Delay (HSDL)
Write
5
HSDL7 HSDL6 HSDL5 HSDL4 HSDL3 HSDL2 HSDL1 HSDL0
Horizontal Valid Trimmer (HVALT)
Write
6
HVALID7 HVALID6 HVALID5 HVALID4 HVALID3 HVALID2 HVALID1 HVALID0
Vertical Valid Trimmer (VVALT)
Write
7
VVALID7 VVALID6 VVALID5 VVALID4 VVALID3 VVALID2 VVALID1 VVALID0
Luminance Control (LUMC)
Write
8
LUMC7 LUMC6 LUMC5 LUMC4 LUMC3 LUMC2 LUMC1 LUMC0
AGC/Pedestal Loop Filter Control (AGCLF) Write
9
AGCLF7 AGCLF6 AGCLF5 AGCLF4 AGCLF3 AGCLF2 AGCLF1 AGCLF0
Sync Separation Level (SSEPL)
Write
A
SSEPL7 SSEPL6 SSEPL5 SSEPL4 SSEPL3 SSEPL2 SSEPL1 SSEPL0
Chrominance Control (CHRC)
Write
B
CHRC7 CHRC6 CHRC5 CHRC4 CHRC3 CHRC2 CHRC1 CHRC0
ACC Loop Filter Control (ACCLF)
Write
C
ACCLF7 ACCLF6 ACCLF5 ACCLF4 ACCLF3 ACCLF2 ACCLF1 ACCLF0
Hue Control (HUE)
Write
D
HUE7 HUE6 HUE5 HUE4 HUE3 HUE2 HUE1 HUE0
Output Phase Control for Data Y (OPCY) Write
E
OPCY7 OPCY6 OPCY5 OPCY4 OPCY3 OPCY2 OPCY1 OPCY0
Output Phase Control for Data C (OPCC) Write
F
OPCC7 OPCC6 OPCC5 OPCC4 OPCC3 OPCC2 OPCC1 OPCC0
Optional Mode Register (OMR)
Write
10
OMR7 OMR6 OMR5 OMR4 OMR3 OMR2 OMR1 OMR0
ADC Register (ADC1)
Write
11
ADC17 ADC16 ADC15 ADC14 ADC13 ADC12 ADC11 ADC10
ADC Register (ADC2)
Write
12
ADC27 ADC26 ADC25 ADC24 ADC23 ADC22 ADC21 ADC20
ADC Register (ADC3)
Write
13
ADC37 ADC36 ADC35 ADC34 ADC33 ADC32 ADC31 ADC30
0 Level Detect Register (ZLD)
Write
14
ZLD7
Stataus Register (STATUS)
Read
20
STATUS7 STATUS6 STATUS5 STATUS4 STATUS3 STATUS2 STATUS1 STATUS0
ZLD6
ZLD5
ZLD4
ZLD3
ZLD2
ZLD1
ZLD0
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Register Parameters
Registers controlled from the I2C-bus are listed below.
An asterisk (*) indicates that the register setting value is the default value.
Mode Register A (MRA)
Register Name
Write only
<address: $00>
MRA[7] MRA[6] MRA[5] MRA[4] MRA[3] MRA[2] MRA[1] MRA[0]
Default
0
1
0
0
0
0
0
0
Recommended Value
—
—
—
0
—
—
—
—
MRA[7:6]
Video output mode
00: ITU-RBT.656
*01: Y, C 8 bits
10: Y, C 16 bits
11: RGB 24 bits
Video output mode is selected.
MRA[5]
Chroma format
*0: Offset binary
1: 2's complement
MRA[4]
Undefined
Set to 0
1: S-video input
MRA[3:1]
Input Sampling mode
*000: NTSC ITU-RBT.601 13.5 MHz
001: NTSC Square Pixel 12.272727 MHz
010: NTSC 4fsc
14.31818 MHz
100: PAL ITU-RBT.601
13.5 MHz
101: PAL Square Pixel
14.75 MHz
110, 111: Undefined
Sampling rate is selected
MRA[0]
MODE[3:0] pin select
*0: External pin mode
1: Register mode
Note:
Only the setting of MODE[3:0] is valid in this external pin mode.
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Mode Register B (MRB)
Register Name
MSM7662
Write only
<address: $01>
MRB[7] MRB[6] MRB[5] MRB[4] MRB[3] MRB[2] MRB[1] MRB[0]
Default
0
0
0
1
0
0
0
0
Recommended Value
0
0
0
1
0
0
0
0
MRB[7:6]
Synchronization mode
*00: FIFO-1 (use internal memory)
01: FIFO-2 (use internal memory)
10: FM-1 (use external memory, external control)
11: FM-2 (use external memory, control signals
supplied from M[7:4])
Note:
In the FIFO-1 mode, the number of pixels per 1H is output at the standard setting value.
In the FIFO-2 mode, the number of pixels per 1H is fixed in accordance with an input
H period and output.
In the FM-1 and FM-2 modes, a decoded result is output without any changes
according to the SYNC signal. A field memory is required externally to output the fixed
number of pixels in those modes. In the FM-2 mode, a field memory control signal is
output from the pin M[7:4].
MRB[5]
Color killer mode
*0: Auto color killer (Chrominance signal level is
set to "0" if the color burst level is below the
specified value.)
*1: Forced color killer (Chrominance signal level
is forced to "0".)
MRB[4]
Blue Back
0: OFF (Video signal is demodulated and output
regardless of synchronization detection.)
*1: AUTO (Blue Back is output when synchronization is not detected.)
Note:
When Blue Back output is selected, if "H" level is not input during no signal output, a
vertical synchronizing signal (VSYNC_L) is not output.
MRB[3:2]
Clamp mode
*00: Analog clamp
01: Analog, Digital hybrid clamp
10: Digital clamp (HSY clamp)
11: Undefined
Clamp mode is selected.
MRB[1:0]
Y/C separation mode
*00: Adaptive comb filter (Correlation of 3 lines is
monitored and operating mode is selected.)
01: Non-adaptive comb filter (Operating mode is
always fixed.)
10: Use trap filter. (Comb filter is not used.)
11: Undefined
Note: Adaptive comb filter
2/3-line comb filter for NTSC
Comb filter/trap filter for PAL
Non-adaptive comb filter
3-line comb filter for NTSC
2-line cosine comb filter for PAL
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Mode Register C (MRC)
Register Name
Write only
<address: $02>
MRC[7] MRC[6] MRC[5] MRC[4] MRC[3] MRC[2] MRC[1] MRC[0]
Default
1
0
0
0
0
0
0
0
Recommended Value
1
0
—
0
—
—
0
0
MRC[7]
NTSC/PAL auto select
0: Fix
*1: Auto
Note:
This register decides automatically when the sampling frequency of input signals is
ITU-RBT.601.
MRC[6]
Sub pixel alignment
*0: Use pixel position compensating circuit.
1: Do not use pixel position compensating circuit.
MRC[5]
Pixel sampling rate
*0: (4:2:2)
1: (4:1:1)
MRC[4]
Data-pass control
*0: Use DECIMATOR at 2x sampling.
1: Do not use DECIMATER.
Note: This register is valid when a 2x clock (27 MHz) is input.
MRC[3]
SAV, EAV V-status
*0: During blanking, V = 1
1: During blanking, while VBI data is not
detected, V = 1
MRC[2]
RGB output level
*0: 0 to 255
1: 16 to 235
MRC[1:0]
Undefined
Set to 0
Horizontal Sync Trimmer (HSYT)
Register Name
Write only
<address: $03>
HSYT[7] HSYT[6] HSYT[5] HSYT[4] HSYT[3] HSYT[2] HSYT[1] HSYT[0]
Default
0
0
0
0
0
0
0
0
Recommended Value
0
0
0
0
0
0
0
0
HSYT[7:4]
HSY start trimmer (¥ 8 pixels)
$C to $B (*$0): –4 to +11 (–32 to +88 pixels)
HSYT[3:0]
HSY stop trimmer (¥ 8 pixels)
$C to $B (*$0): –4 to +11 (–32 to +88 pixels)
Note:
The HSYT signal provides the clamp timing to the A/D converter during digital clamp
or hybrid clamp mode. Because this signal can move to the pedestal position, the
pedestal clamp can be used. However, this signal can not be observed from outside.
Sync. Threshold level adjust (STHR)
Register Name
Write only
<address: $04>
STHR[7] STHR[6] STHR[5] STHR[4] STHR[3] STHR[2] STHR[1] STHR[0]
Default
0
0
0
1
1
1
1
0
Recommended Value
0
0
1
1
0
1
1
1
STHR[7:0]
Sync. depth
$00 to $FF (*$1E): 0 to 255
Note:
The STHR signal changes the HSYNC_L detection level. The numerical unit described
here is determined based on 80IRE obtained from doubling the pedestal value of
standard signal, if set to 40IRE. For example, the default 0x1E is 30 in digital value,
which is reduced to 15IRE.
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Horizontal Sync Delay (HSDL)
Register Name
Write only
<address: $05>
HSDL[7] HSDL[6] HSDL[5] HSDL[4] HSDL[3] HSDL[2] HSDL[1] HSDL[0]
Default
0
0
0
0
0
0
0
0
Recommended Value
0
0
0
0
0
0
0
0
HSDL[7:0]
Note:
HSYNC_L delay trimmer (¥ 1 pixel)
$80 to $7F (*$00): –128 to +127 (–128 to +127
pixels)
The HSYNC_L sync signal output position is adjusted.
Horizontal Valid Trimmer (HVALT) Write only
<address: $06>
HVALT
HVALT
HVALT
HVALT
HVALT
HVALT
HVALT
HVALT
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Default
0
0
0
0
0
0
0
0
Recommended Value
0
0
0
0
0
0
0
0
Register Name
HVALT[7:4] HVALID start trimmer (¥ 2 pixels) $8 to $7 (*$0): –8 to +7 (–16 to +14 pixels)
HVALT[3:0] HVALID stop trimmer (¥ 2 pixels) $8 to $7 (*$0): –8 to +7 (–16 to +14 pixels)
Note:
HVALID start position and end position are changed.
Vertical Valid Trimmer (VVALT)
Write only
<address: $07>
VVALT
VVALT
VVALT
VVALT
VVALT
VVALT
VVALT
VVALT
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Default
0
0
0
0
0
0
0
0
Recommended Value
0
0
0
0
0
0
0
0
Register Name
VVALT[7:4] VVALID start trimmer (¥ 1 line)
$8 to $7 (*$0): –8 to +7
VVALT[3:0] VVALID stop trimmer (¥ 1 line)
$8 to $7 (*$0): –8 to +7
Note:
VVALID start position and end position are changed.
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MSM7662
Luminance Control (LUMC)
Register Name
Write only
<address: $08>
LUMC[7] LUMC[6] LUMC[5] LUMC[4] LUMC[3] LUMC[2] LUMC[1] LUMC[0]
Default
0
0
0
0
0
0
0
0
Recommended Value
0
0
0
0
0
0
0
0
LUMC[7]
Output level limiter
*0: OFF
1: ON
Note: Control range while limiter is ON: 16 to 235
LUMC[6]
Use of prefilter
*0: Do not use prefilter.
1: Use prefilter.
LUMC[5:4] Aperture bandpass select *00: range0 (middle)
01: range1
10: range2
11: range3 (high)
LUMC[3:2] Coring range select
*00: coring off
01: ±4LSB
10: ±5LSB
11: ±7LSB
LUMC[1:0] Aperture filter weighting factor
*00: 0.00
01: 0.25
10: 0.75
11: 1.50
Note:
These registers are used for contour compensation.
AGC/Pedestal Loop filter control (AGCLF)
Write only
Register Name
<address: $09>
AGCLF AGCLF AGCLF AGCLF AGCLF AGCLF AGCLF AGCLF
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Default
0
1
0
0
0
0
0
0
Recommended Value
0
1
0
0
0
0
0
0
AGCLF[7:6] AGC loop filter time constant
00: slow
*01: medium
10: fast
11: MGC mode
Note:
The AGC convergence time is determined. These registers converge about 4 times
faster by slow-medium-fast steps. In the MGC mode, the amplification is determined
by reference level.
AGCLF[5:0] AGC reference level
$20 to $1F (*$00): –32 to +31
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MSM7662
Sync separation level (SSEPL) Write only
<address: $0A>
SSEPL
SSEPL
SSEPL
SSEPL
SSEPL
SSEPL
SSEPL
SSEPL
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Default
0
0
0
0
0
0
0
0
Recommended Value
0
0
0
0
0
0
0
0
Register Name
SSEPL[7]
Pedestal Clamp on/off
*0: Do not use pedestal clamp.
1: Use pedestal clamp (AGC stops operating).
SSEPL[6:0] Sync. separation level
$40 to $3F (*$00): –64 to +63
Note:
The default setting outputs the pedestal position as a black level.
Chrominance Control (CHRC) Write only
Register Name
<address: $0B>
CHRC[7] CHRC[6] CHRC[5] CHRC[4] CHRC[3] CHRC[2] CHRC[1] CHRC[0]
Default
0
0
0
0
0
1
0
1
Recommended Value
0
0
0
0
0
1
0
1
CHRC[7:4]
CHRC[3]
Undefined
C-Output level limiter
Set to 0
*0: OFF
1: ON
Note: Control range while limiter is ON: 16 to 224
CHRC[2]
Chroma bandpass filter
0: OFF
*1: ON
CHRC[1:0] Color kill threshold factor 00: 0.500 color burst level
*01: 0.250 color burst level
10: 0.125 color burst level
11: Color killer off
Note:
The color killer decision level is selected based upon color burst ratio.
ACC Loop filter control (ACCLF)
Write only
Register Name
<address: $0C>
ACCLF ACCLF ACCLF ACCLF ACCLF ACCLF ACCLF ACCLF
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Default
0
0
1
0
0
0
0
0
Recommended Value
0
0
1
0
0
0
0
0
ACCLF[7]
Undefined
Set to 0
ACCLF[6:5] ACC loop filter time constant
00: slow
*01: medium
10: fast
11: MCC mode
Note:
The ACC convergence time is determined. These registers converge about 4 times
faster by slow-medium-fast steps. In the MCC mode, the amplification is determined
by reference level.
ACCLF[4:0] ACC reference level
$10 to $0F (*$00): –16 to +15
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MSM7662
Hue control (HUE)
Register Name
Write only
<address: $0D>
HUE[7] HUE[6] HUE[5] HUE[4] HUE[3] HUE[2] HUE[1] HUE[0]
Default
0
0
0
0
0
0
0
0
Recommended Value
0
0
0
0
0
0
0
0
HUE[7:0]
Hue control
$80 to $7F (*$00): –180 to +178.6 degrees
Note:
The phase is controlled. It changes about 1.4 degrees per bit.
Output phase control for data Y (OPCY)
Write only
Register Name
<address: $0E>
OPCY[7] OPCY[6] OPCY[5] OPCY[4] OPCY[3] OPCY[2] OPCY[1] OPCY[0]
Default
0
0
0
0
0
0
0
0
Recommended Value
0
0
0
0
0
0
0
0
OPCY[7:2]
OPCY[1:0]
Note:
Undefined
Set to 0
Output phase control for data Y
*00: normal
01: forward l clock
10: backward 2 clock
11: backward l clock
The output phase of data Y is controlled.
Output phase control for data C (OPCC)
Write only
Register Name
<address: $0F>
OPCC[7] OPCC[6] OPCC[5] OPCC[4] OPCC[3] OPCC[2] OPCC[1] OPCC[0]
Default
0
0
0
0
0
0
0
0
Recommended Value
0
0
0
0
0
0
0
0
OPCC[7:2]
OPCC[1:0]
Note:
Undefined
Set to 0
Output phase control for data C
*00: normal
01: forward l clock
10: backward 2 clock
11: backward l clock
The output phase of data C is controlled.
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MSM7662
Optional Mode Register (OMR)
Write only
Register Name
<address: $10>
OMR[7] OMR[6] OMR[5] OMR[4] OMR[3] OMR[2] OMR[1] OMR[0]
Default
0
0
0
1
0
0
0
0
Recommended Value
1
1
0
1
0
0
0
0
OMR[7]
HSYNC output timing select *0: HSYNC output signal is detected near sync
threshold and sync tip.
1: HSYNC output signal is detected at sync
threshold setting position.
Note:
When the HSYNC output signal is detected at sync threshold setting position, it is
hardly affected by noise.
OMR[6]
VSYNC output timing select *0: VSYNC_L is synchronized to HSYNC_L and
then output
1: VSYNC_L is output when a VSYNC input
signal is detected.
Note:
When a non-standard signal is decoded, the output is stabilized after the VSYNC_L
input signal is detected (setting 1).
OMR[5:3]
Multiplex signal detection level
(VBID etc.)
000: 80
001: 88
*010: 96
011: 104
100: 112
101: 120
110: 128
111: 136
Note:
The levels to detect multiplexed signals sent during the vertical blanking period are set.
The result is output from the STATUS[1] pin or STATUS[4] register.
OMR[2]
Hi-Z output in SLEEP mode
*0: Active
1: Hi-Z
Note:
This register selects either normal or Hi-Z as the output pin status in SLEEP mode.
OMR[1]
Status2 output mode
*0: NTSC/PAL identification
1: HLOCK sync detection
OMR[0]
Status3 output mode
*0: TV/VCR identification
1: CSYNC
Note:
OMR[1:0] correspond to the STATUS[2:3] output of output pins.
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MSM7662
ADC register 1 (ADC1)
Register Name
Write only
<address: $11>
ADC1[7] ADC1[6] ADC1[5] ADC1[4] ADC1[3] ADC1[2] ADC1[1] ADC1[0]
Default
0
0
0
0
0
0
0
0
Recommended Value
0
0
1
1
0
—
—
—
ADC1[7]
Video amp select
ADC1[6]
ADC1[5:4]
Undefined
Clamp current select
ADC1[3]
ADC1[2:0]
Undefined
ADC input select
ADC register 2 (ADC2)
Register Name
*0: Use
1: Do not use
Set to 0
*00: 1.0
01: 0.75
10: 0.25
11: 0.1
Set to 0
*000: ADI-VIN1 (composite-1)
001: ADI-VIN2 (composite-2)
010: ADI-VIN3 (composite-3)
011: ADI-VIN4 (composite-4)
100: ADI-VIN5 (composite-5)
101: ADI-VIN1 (Y-1), AD2-VIN5 (C-1)
110: ADI-VIN2 (Y-1), AD2-VIN6 (C-1)
111: Prohibited setting (ADC enters sleep state)
Write only
<address: $12>
ADC2[7] ADC2[6] ADC2[5] ADC2[4] ADC2[3] ADC2[2] ADC2[1] ADC2[0]
Default
1
0
0
1
1
1
1
0
Recommended Value
0
0
0
1
1
1
1
0
ADC2[7]
ADC2[6:4]
ADC2[3]
ADC[2]
ADC2[1:0]
ADC gain control mode select
0: manual
*1: auto
ADC gain manual select
000: 1.00
*001: 1.35
010: 1.75
011: 2.30
100: 3.00
101: 3.80
110: 5.00
111: Undefined
ADC initialize condition gain select
0: not initialize
*1: initialize
Undefined
Set to 0
ADC gain control and stage select
00: 2nd change end
01: 3rd change end
*10: 3rd change loop
11: Undefined
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MSM7662
ADC register 3 (ADC3)
Register Name
Write only
<address: $13>
ADC3[7] ADC3[6] ADC3[5] ADC3[4] ADC3[3] ADC3[2] ADC3[1] ADC3[0]
Default
0
0
1
0
0
0
1
0
Recommended Value
0
0
1
0
0
0
1
0
ADC3[7]
ADC3[6:4]
Undefined
Set to 0
ADC gain control margin level select
000: 10 mV
001: 20 mV
*010: 40 mV
011: 80 mV
100: 160 mV
ADC3[3]
Undefined
Set to 0
ADC3[2:0]
ADC gain control line select
000: 1 line
001: 2 lines
*010: 4 lines
011: 8 lines
100: 16 lines
Note:
These registers determine the analog gain control decision level. The stability can be
obtained from higher values.
0 level detect register (ZLD)
Register Name
Write only
<address: $14>
ZLD[7]
ZLD[6]
ZLD[5]
ZLD[4]
ZLD[3]
ZLD[2]
ZLD[1]
ZLD[0]
Default
0
0
0
0
0
0
1
0
Recommended Value
0
0
0
0
0
0
1
0
ZLD[7:3]
ZLD[2:0]
Note:
Undefined
Set to 0
0 level detect width (¥ 8 pixel)
000: Undefined
001: 8 pixels
*010: 16 pixels
011: 24 pixels
100: 32 pixels
101: 40 pixels
110: 48 pixels
111: 56 pixels
These registers decide the continuance of sync tip level and its result is reflected in AGC
gain. The stability can be obtained from higher values.
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MSM7662
Status register (STATUS)
Register Name
Read only
<address: $20>
STATUS STATUS STATUS STATUS STATUS STATUS STATUS STATUS
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Default
—
—
—
—
—
—
—
—
Recommended Value
—
—
—
—
—
—
—
—
STATUS[7:5]
STATUS[4]
STATUS[3]
STATUS[2]
STATUS[1]
STATUS[0]
Undefined
VBI interval multiplex signal detection
0: Non-detection, 1: Detection
HLOCK sync detection
0: Non-detection, 1: Detection
NTSC/PAL identification
0: NTSC, 1: PAL
Fifo1/Fifo2 identification Mode Register B (bit 6)
0: Fifo1, 1: Fifo2
FTFO overflow detection
0: Non-detection, 1: Detection
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MSM7662
Relationship between Register Setting Value and Adjusted Value
Horizontal Sync Trimmer
Position adjustment of sync tip clamp timing signal
HSYT [7:4]
:Adjusting the starting position
F
0*
1
Adjusted Value (Pixel) –32 –24 –16 –8
0
+8 +16 +24 +32 +40 +48 +56 +64 +72 +80 +88
Register Setting Value (0x)
HSYT [3:0]
C
D
E
2
3
4
5
6
7
8
9
A
B
:Adjusting the end position
F
0*
1
Adjusted Value (Pixel) –32 –24 –16 –8
0
+8 +16 +24 +32 +40 +48 +56 +64 +72 +80 +88
Register Setting Value (0x)
C
D
E
2
3
4
5
6
7
8
9
A
B
Horizontal Sync Delay
Adjustment of the starting position of horizontal sync signal
HSDL [7:0]
Unit: [pixel]
Register Setting
Value
(0x)
MSB[7 : 4]
B
C
D
E
F
0*
1
2
3
4
5
0* –128 –112 –96
8
9
A
–80
–64
–48
–32
–16
0
+16
+32
+48
+64
+80
+96 +112
6
7
1
–127 –111 –95
–79
–63
–47
–31
–15
+1
+17
+33
+49
+65
+81
+97 +113
2
–126 –110 –94
–78
–62
–46
–30
–14
+2
+18
+34
+50
+66
+82
+98 +114
3
–125 –109 –93
–77
–61
–45
–29
–13
+3
+19
+35
+51
+67
+83
+99 +115
4
–124 –108 –92
–76
–60
–44
–28
–12
+4
+20
+36
+52
+68
+84 +100 +116
5
–123 –107 –91
–75
–59
–43
–27
–11
+5
+21
+37
+53
+69
+85 +101 +117
6
–122 –106 –90
–74
–58
–42
–26
–10
+6
+22
+38
+54
+70
+86 +102 +118
LSB
7
–121 –105 –89
–73
–57
–41
–25
–9
+7
+23
+39
+55
+71
+87 +103 +119
[3 : 0]
8
–120 –104 –88
–72
–56
–40
–24
–8
+8
+24
+40
+56
+72
+88 +104 +120
9
–119 –103 –87
–71
–55
–39
–23
–7
+9
+25
+41
+57
+73
+89 +105 +121
A
–118 –102 –86
–70
–54
–38
–22
–6
+10
+26
+42
+58
+74
+90 +106 +122
B
–117 –101 –85
–69
–53
–37
–21
–5
+11
+27
+43
+59
+75
+91 +107 +123
C
–116 –100 –84
–68
–52
–36
–20
–4
+12
+28
+44
+60
+76
+92 +108 +124
D
–115 –99
–83
–67
–51
–35
–19
–3
+13
+29
+45
+61
+77
+93 +109 +125
E
–114 –98
–82
–66
–50
–34
–18
–2
+14
+30
+46
+62
+78
+94 +110 +126
F
–113 –97
–81
–65
–49
–33
–17
–1
+15
+31
+47
+63
+79
+95 +111 +127
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MSM7662
Horizontal Valid Trimmer
Position adjustment of horizontal valid pixel timing signal
HVALT [7:4]
:Adjusting the starting position
C
D
E
F
0*
1
2
3
4
Adjusted Value (Pixel) –16 –14 –12 –10 –8
–6
–4
–2
0
+2
+4
+6
+8 +10 +12 +14
Register Setting Value (0x)
HVALT [3:0]
8
9
A
B
5
6
7
:Adjusting the end position
C
D
E
F
0*
1
2
3
4
Adjusted Value (Pixel) –16 –14 –12 –10 –8
–6
–4
–2
0
+2
+4
+6
+8 +10 +12 +14
Register Setting Value (0x)
8
9
A
B
5
6
7
Vertical Valid Trimmer
Position adjustment of vertical valid line timing signal
VVALT [7:4]
:Adjusting the starting position
Register Setting Value (0x)
8
9
A
B
C
D
E
F
0*
1
2
3
4
5
6
7
Adjusted Value (Line)
–8
–7
–6
–5
–4
–3
–2
–1
0
+1
+2
+3
+4
+5
+6
+7
VVALT [3:0]
:Adjusting the end position
Register Setting Value (0x)
8
9
A
B
C
D
E
F
0*
1
2
3
4
5
6
7
Adjusted Value (Line)
–8
–7
–6
–5
–4
–3
–2
–1
0
+1
+2
+3
+4
+5
+6
+7
AGC Loop Filter Control
AGCLF [5:0]
:Adjusting AGC sync level
Unit: [IRE], Default: 40 IRE
Register Setting
Value
(0x)
MSB [5 : 4]
2
3
0*
1
0*
–32
–16
0
+16
1
–31
–15
+1
+17
2
–30
–14
+2
+18
3
–29
–13
+3
+19
4
–28
–12
+4
+20
5
–27
–11
+5
+21
6
–26
–10
+6
+22
LSB
7
–25
–9
+7
+23
[3 : 0]
8
–24
–8
+8
+24
9
–23
–7
+9
+25
A
–22
–6
+10
+26
B
–21
–5
+11
+27
C
–20
–4
+12
+28
D
–19
–3
+13
+29
E
–18
–2
+14
+30
F
–17
–1
+15
+31
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MSM7662
Sync Separation Level
SSEPL [6:0]
:Adjusting the blanking level
Unit: [IRE], Default: 40 IRE
Register Setting
Value
(0x)
MSB [6 : 4]
4
5
6
7
0*
1
2
3
0*
–64
–48
–32
1
–63
–47
–31
–16
0
+16
+32
+48
–15
+1
+17
+33
+49
2
–62
–46
–30
–14
+2
+18
+34
+50
3
–61
4
–60
–45
–29
–13
+3
+19
+35
+51
–44
–28
–12
+4
+20
+36
+52
5
6
–59
–43
–27
–11
+5
+21
+37
+53
–58
–42
–26
–10
+6
+22
+38
+54
LSB
[3 : 0]
7
–57
–41
–25
–9
+7
+23
+39
+55
8
–56
–40
–24
–8
+8
+24
+40
+56
9
–55
–39
–23
–7
+9
+25
+41
+57
A
–54
–38
–22
–6
+10
+26
+42
+58
B
–53
–37
–21
–5
+11
+27
+43
+59
C
–52
–36
–20
–4
+12
+28
+44
+60
D
–51
–35
–19
–3
+13
+29
+45
+61
E
–50
–34
–18
–2
+14
+30
+46
+62
F
–49
–33
–17
–1
+15
+31
+47
+63
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MSM7662
ACC Loop Filter Control
ACCLF [4:0]
:Adjusting the color burst level
Unit: [IRE], Default: 40 IRE
Register Setting
Value
(0x)
MSB [4]
1
0*
0*
–16
0
1
–15
+1
2
–14
+2
3
–13
+3
4
–12
+4
5
–11
+5
6
–10
+6
LSB
7
–9
+7
[3 : 0]
8
–8
+8
9
–7
+9
A
–6
+10
B
–5
+11
C
–4
+12
D
–3
+13
E
–2
+14
F
–1
+15
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MSM7662
Hue Control
Adjustment of color subcarrier phase
HUE [7:0]
Unit: [degree]
Register Setting
Value
(0x)
MSB [7 : 4]
8
9
A
B
C
D
E
F
0*
1
2
3
4
5
6
7
0* –180.0 –157.5 –135.0 –112.5 –90.0 –67.5 –45.0 –22.5 +0.0 +22.5 +45.0 +67.5 +90.0 +112.5 +135.0 +157.5
1
–178.6 –156.1 –133.6 –111.1 –88.6 –66.1 –43.6 –21.1 +1.4 +23.9 +46.4 +68.9 +91.4 +113.9 +136.4 +158.9
2
–177.2 –154.7 –132.2 –109.7 –87.2 –64.7 –42.2 –19.7 +2.8 +25.3 +47.8 +70.3 +92.8 +115.3 +137.8 +160.3
3
–175.8 –153.3 –130.8 –108.3 –85.8 –63.3 –40.8 –18.3 +4.2 +26.7 +49.2 +71.7 +94.2 +116.7 +139.2 +161.7
4
–174.4 –151.9 –129.4 –106.9 –84.4 –61.9 –39.4 –16.9 +5.6 +28.1 +50.6 +73.1 +95.6 +118.1 +140.6 +163.1
5
–173.0 –150.5 –128.0 –105.5 –83.0 –60.5 –38.0 –15.5 +7.0 +29.5 +52.0 +74.5 +97.0 +119.5 +142.0 +164.5
6
–171.6 –149.1 –126.6 –104.1 –81.6 –59.1 –36.6 –14.1 +8.4 +30.9 +53.4 +75.9 +98.4 +120.9 +143.4 +165.9
LSB
7
–170.2 –147.7 –125.2 –102.7 –80.2 –57.7 –35.2 –12.7 +9.8 +32.3 +54.8 +77.3 +99.8 +122.3 +144.8 +167.3
[3 : 0]
8
–168.8 –146.3 –123.8 –101.3 –78.8 –56.3 –33.8 –11.3 +11.3 +33.8 +56.3 +78.8 +101.3 +123.8 +146.3 +168.8
9
–167.3 –144.8 –122.3 –99.8 –77.3 –54.8 –32.3 –9.8 +12.7 +35.2 +57.7 +80.2 +102.7 +125.2 +147.7 +170.2
A –165.9 –143.4 –120.9 –98.4 –75.9 –53.4 –30.9 –8.4 +14.1 +36.6 +59.1 +81.6 +104.1 +126.6 +149.1 +171.6
B –164.5 –142.0 –119.5 –97.0 –74.5 –52.0 –29.5 –7.0 +15.5 +38.0 +60.5 +83.0 +105.5 +128.0 +150.5 +173.0
C –163.1 –140.6 –118.1 –95.6 –73.1 –50.6 –28.1 –5.6 +16.9 +39.4 +61.9 +84.4 +106.9 +129.4 +151.9 +174.4
D –161.7 –139.2 –116.7 –94.2 –71.7 –49.2 –26.7 –4.2 +18.3 +40.8 +63.3 +85.8 +108.3 +130.8 +153.3 +175.8
E
–160.3 –137.8 –115.3 –92.8 –70.3 –47.8 –25.3 –2.8 +19.7 +42.2 +64.7 +87.2 +109.7 +132.2 +154.7 +177.2
F
–158.9 –136.4 –113.9 –91.4 –68.9 –46.4 –23.9 –1.4 +21.1 +43.6 +66.1 +88.6 +111.1 +133.6 +156.1 +178.6
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PEDL7662-02
¡ Semiconductor
MSM7662
Sync. Threshold Level Adjust
Adjustment of the detection threshold of horizontal sync signal
SHTR [7:0]
Unit: [IRE]/2
Register Setting
Value
(0x)
MSB [7 : 4]
0
1*
2
3
4
5
6
0
0
16
32
48
64
80
96
112 128 144 160 176 192 208 224 240
7
8
9
A
B
C
D
E
F
1
1
17
33
49
65
81
97
113 129 145 161 177 193 209 225 241
2
2
18
34
50
66
82
98
114 130 146 162 178 194 210 226 242
3
3
19
35
51
67
83
99
115 131 147 163 179 195 211 227 243
4
4
20
36
52
68
84
100 116 132 148 164 180 196 212 228 244
5
5
21
37
53
69
85
101 117 133 149 165 181 197 213 229 245
6
6
22
38
54
70
86
102 118 134 150 166 182 198 214 230 246
LSB
7
7
23
39
55
71
87
103 119 135 151 167 183 199 215 231 247
[3 : 0]
8
8
24
40
56
72
88
104 120 136 152 168 184 200 216 232 248
9
9
25
41
57
73
89
105 121 137 153 169 185 201 217 233 249
A
10
26
42
58
74
90
106 122 138 154 170 186 202 218 234 250
B
11
27
43
59
75
91
107 123 139 155 171 187 203 219 235 251
C
12
28
44
60
76
92
108 124 140 156 172 188 204 220 236 252
D
13
29
45
61
77
93
109 125 141 157 173 189 205 221 237 253
E*
14
30
46
62
78
94
110 126 142 158 174 190 206 222 238 254
F
15
31
47
63
79
95
111 127 143 159 175 191 207 223 239 255
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PEDL7662-02
¡ Semiconductor
MSM7662
Filter Characteristics
Band Pass Filter (NTSC ITU-RBT.601)
0
Level [dB]
–20
–40
–60
–80
–100
0
1
2
3
4
5
6
5
6
Frequency [MHz]
Band Pass Filter (PAL ITU-RBT.601)
0
Level [dB]
–20
–40
–60
–80
–100
0
1
2
3
4
Frequency [MHz]
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PEDL7662-02
¡ Semiconductor
MSM7662
Trap Filter (NTSC ITU-RBT.601)
0
Level [dB]
–20
–40
–60
–80
–100
0
1
2
3
4
5
6
5
6
Frequency [MHz]
Trap Filter (PAL ITU-RBT.601)
0
Level [dB]
–20
–40
–60
–80
–100
0
1
2
3
4
Frequency [MHz]
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PEDL7662-02
¡ Semiconductor
MSM7662
Pre Filter
0
Level [dB]
–20
–40
–60
–80
–100
0
1
2
3
4
5
6
5
6
Frequency [MHz]
Sharp Filter
0
Level [dB]
–20
–40
–60
–80
–100
0
1
2
3
4
Frequency [MHz]
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PEDL7662-02
¡ Semiconductor
MSM7662
Decimation Filter
0
Level [dB]
–20
–40
–60
–80
–100
0
2
4
6
8
10
12
Frequency [MHz]
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PEDL7662-02
¡ Semiconductor
MSM7662
BASIC APPLICATION CIRCUIT EXAMPLES
1) Application Circuit for FIFO-1 and FIFO-2 Modes
3.3 V or 5 V
4.7 kW
1000 pF 1000 pF 1000 pF
47 mF 47 mF 47 mF
4.7 kW
I2C
Controller
Video in
(Composite
Y input)
SDA SCL RESET_L AVDD
VIN(1:4)
VRT1
AMPOUT
LPF
ADIN1
1 mF 75 W 4
75 W
10 mF
10 mF
1 mF
75 W
VRB1
10 mF
Y(7:0)
C(7:0)
HVALID
VVALID
2
VIN(5:6)
VRT2
AMPOUT2
LPF
ADIN2
1 mF CLPOUT2
VRB2
Video LSI
B(7:0)
MSM7662
10 mF
1 mF
75 W
DVDD
CLPOUT1
VRCL1
10 kW
Video in
(C input)
DAVDD
ODD
HSYNC_L
VSYNC_L
CLKX2O
CLKXO
AGND
DAGND DGND
MODE[3:0]
CLKX2
OSC
AMPOUT
LPF
ADIN
100 W
250 pF
• Connect the M7662 decoder and a video LSI device according to the output interface (ITURBT.656, 8-bit [YCbCr], 16-bit [YCbCr], RGB).
• Video input can be four composite inputs or two S-Video inputs.
• Connect unused video input pins to AGND. If a composite signal is input, the C input side
(video amp, A/D converter, etc.) will be in the OFF operation state.
• If the input is limited by the composite signal, connect VIN (5:6), VRT2, VRB2, AMPOUT2,
ADIN2, and CLPOUT2 pins to AGND. Externally attached components such as capacitors
may be removed.
• Set the MODE[3:0] pins to the prescribed setting.
• Supply power and GND for analog, A/D, and digital circuits on the circuit board should be
separated at the power source wherever possible. Power and GND lines for analog and A/D
circuits must be wide and low impedance.
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PEDL7662-02
¡ Semiconductor
MSM7662
2) Application Circuit for FM-1 and FM-2 Modes
3.3 V or 5 V
4.7 kW
1000 pF 1000 pF 1000 pF
47 mF 47 mF 47 mF
4.7 kW
Memory
control signal
I2 C
Controller
Video in
(Composite
Y input)
1 mF 75 W 4
75 W
10 mF
10 mF
SDA SCL RESET_L AVDD
VIN(1:4)
VRT1
AMPOUT
LPF
ADIN1
1 mF
75 W
DVDD
Y(7:0)
C(7:0)
B(7:0)
VRB1
MSM7662
2
VIN(5:6)
VRT2
AMPOUT2
LPF
ADIN2
1 mF CLPOUT2
VRB2
10 mF
1 mF
10 mF
M[7:4]
CLPOUT1
VRCL1
10 kW
Video in
(C input)75 W
DAVDD
AGND
Field
memory
Field
memory
Video LSI
CLKXO
HVALID
VVALID
ODD
HSYNC_L
VSYNC_L
CLKX2O
DAGND DGND
MODE[3:0]
CLKX2
OSC
AMPOUT
LPF
ADIN
100 W
250 pF
• Select either 16-bit [YCbCr] or RGB output as the output interface.
• Number of field memories utilized
16-bit [YCbCr]: Use 2 field memories.
RGB: Use 3 field memories.
• Video input can be four composite inputs or two S-Video inputs.
• Connect unused video input pins to AGND. If a composite signal is input, the C input side
(video amp, A/D converter, etc.) will be in the OFF operation state.
• If the input is limited by the composite signal, connect VIN (5:6), VRT2, VRB2, AMPOUT2,
ADIN2, and CLPOUT2 pins to AGND. Externally attached components such as capacitors
may be removed.
• Set the MODE[3:0] pins to the prescribed setting.
• For the FM-1 mode setting, externally generate and supply control signals for the field
memory.
• For the FM-2 mode setting, memory control signals from M[7:4] can be supplied to the field
memory.
• For the FM-2 mode setting, the output timing for HSYNC_L, VSYNC_L, ODD, VVALID, and
HVALID becomes the memory read timing. Data output from memory is aligned with the
various sync signal timings. (See page 30 and page 31)
• Supply power and GND for analog, A/D, and digital circuits on the circuit board should be
separated at the power source wherever possible. Power and GND lines for analog and A/D
circuits must be wide and low impedance.
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PEDL7662-02
¡ Semiconductor
MSM7662
PACKAGE DIMENSIONS
(Unit : mm)
TQFP100-P-1414-0.50-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.55 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
on the product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
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PEDL7662-02
¡ Semiconductor
MSM7662
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
6.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan
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