E2U0044-16-X2 ¡ Semiconductor MSM7708-02 ¡ Semiconductor This version: Jan. 1998 MSM7708-02 Previous version: Nov. 1996 Serial Register Interface ADPCM CODEC for Telephone Recording GENERAL DESCRIPTION The MSM7708-02 is a CMOS IC developed for applying to PHS (Personal Handyphone System). This device provides a CODEC function which performs transcoding between the voice band analog signal and 32 kbps ADPCM data. It also provides a serial register interface function for telephone call recording. Provided with such functions as DTMF tone and several kinds of tone generation, transmit/ receive data mute and gain control, side-tone pass, and voice/silence detection, the MSM770802 is best suited for PHS handsets. FEATURES • Single 3 V power supply operation (VDD: 2.7 V to 3.6 V) • Low power consumption When system is operating: 6 mA typ. When powered down: 0.02 mA typ. (ADPCM CODEC) • ADPCM: ITU-T Recommendations G.721 (32 kbps) • Transmit/receive full duplex capability • PCM interface code format: m-law or A-law selectable • Serial ADPCM and PCM transmission rate: 64 kbps to 2,048 kbps • Transmit/receive mute function; transmit/receive programmable gain setting • Side tone generator (8-step level adjustment) • Built-in DTMF tone, ringing tone, and various tone generators • Built-in VOX function (Serial Register Interface) • Interface for a serial register: 1 Mb (MSM63V89C), 4 Mb (MSM6684), 8 Mb (MSM6685) • Interface for a serial voice ROM: 1 Mb (MSM6595A), 2 Mb (MSM6596A), 3 Mb (MSM6597A) • Maximum recording time: 32 s (1 Mb), 128 s (4 Mb), 256 s (8 Mb) • Maximum recording channels: 32 ch • Playback data transmit/receive selectable • Package: 64-pin plastic TQFP (TQFP64-P-1010-0.50-K) (Product name : MSM7708-02TS-K) 1/38 ¡ Semiconductor MSM7708-02 BLOCK DIAGRAM To various units SGR MCU Interface VREF SGT T AIN1– AIN1+ GSX1 AIN2 – + Voice Detect A/D Converter RC Filter – + T BPF GSX2 – + ADPCM Coder P/S & S/P ATT LPF + + ATT Noise Generator Power Detect Expander ADPCM Decoder Serial Register Controller IS PCMSI PCMSO XSYNC BCLK RSYNC PCMRI PCMRO IR DIO WE SAD SAS TAS RWCK CS1 CS2 VOXI To receive unit D/A Converter RC Filter MLV0 MLV1 MLV2 MUTE PWI VFRO SAO 1.2 kW To various units AOUT– VOXO DTMF /Tone Generator –1 VDD DG AG PDN MCK AOUT+ ATT 1.2 kW Compander EXCK DEN DIN DOUT RESET 2/38 ¡ Semiconductor MSM7708-02 49 DG 50 NC 51 XSYNC 52 RSYNC 53 BCLK 54 NC 55 CS2 56 CS1 57 RWCK 58 TAS 59 SAS 60 SAD 61 NC 62 WE 63 DIO 64 NC PIN CONFIGURATION (TOP VIEW) AG 1 48 NC NC 2 47 PCMSO SAO 3 46 PCMSI NC 4 45 NC NC 5 44 IS VFRO 6 43 IR PWI 7 42 NC AOUT– 8 41 PCMRO AOUT+ 9 40 PCMRI 39 NC SGR 10 NC 11 38 MCK SGT 12 37 PDN AIN1– 13 36 RESET GSX1 14 35 DOUT AIN+ 15 34 DIN 33 NC NC 32 EXCK 31 DEN 30 NC 29 VOXO 28 VOXI 27 NC 26 MUTE 25 MLV0 24 MLV1 23 MLV2 22 NC 21 VDD 20 AIN2 19 NC 17 GSX2 18 NC 16 64-Pin Plastic TQFP NC : No connect pin 3/38 ¡ Semiconductor MSM7708-02 PIN DESCRIPTIONS Pin Symbol Type Description 1 AG I Analog ground 2 NC — No connection 3 SAO O Receive side sounder amplifier output 4 NC — No connection 5 NC — No connection 6 VFRO O Receive side voice output 7 PWI I Receive side voice amplifier input 8 AOUT– O Receive side voice amplifier output (–) 9 AOUT+ O Receive side voice amplifier output (+) 10 SGR O Receive side analog signal ground 11 NC — No connection 12 SGT O Transmit side analog signal ground 13 AIN1– I Transmit side amplifier 1 inverting input 14 GSX1 O Transmit side amplifier 1 output 15 AIN1+ I 16 NC — No connection 17 NC — No connection 18 GSX2 O Transmit side amplifier 2 output 19 AIN2 I Transmit side amplifier 2 inverting input 20 VDD I Power supply 21 NC — No connection 22 MLV2 I Receive side voice path mute level set 23 MLV1 I Receive side voice path mute level set 24 MLV0 I Receive side voice path mute level set 25 MUTE I 26 NC — Transmit side amplifier 1 non-inverting input Receive side voice path mute enable signal input No connection 27 VOXI I Receive side voice/silence detect function input 28 VOXO O Transmit side voice/silence detect function output 29 NC — No connection 30 DEN I 31 EXCK I 32 NC — No connection 33 NC — No connection 34 DIN I 35 DOUT O Data output for control register 36 RESET I RESET control input for control register 37 PDN I Power down control input 38 MCK I Master clock input 39 NC — 40 PCMRI I Enable signal input for control register Clock signal input for control register Address and data input for control No connection Receive side PCM signal input 4/38 ¡ Semiconductor MSM7708-02 PIN DESCRIPTIONS (Continued) Pin Symbol Type Description 41 PCMRO O Receive side PCM signal output 42 NC — No connection 43 IR I Receive side ADPCM signal input 44 IS O Transmit side ADPCM signal output 45 NC — No connection 46 PCMSI I 47 PCMSO O Transmit side PCM signal output 48 NC — No connection 49 DG I Digital ground 50 NC — No connection 51 XSYNC I Transmit side PCM and ADPCM data sync signal input 52 RSYNC I Receive side PCM and ADPCM data sync signal input 53 BCLK I 54 NC — No connection 55 CS2 O Voice ROM chip select output 56 CS1 O Serial register chip select output 57 RWCK O Serial register data clock output 58 TAS O Serial register transfer address-strobe output 59 SAS O Serial register address-strobe output 60 SAD O Serial register address data output 61 NC — No connection 62 WE O Serial register write enable output 63 DIO I/O Serial register data input/output 64 NC — No connection Transmit side PCM signal input PCM and ADPCM data shift clock input 5/38 ¡ Semiconductor MSM7708-02 PIN AND FUNCTIONAL DESCRIPTIONS AIN1+, AIN1-, AIN2, GSX1, GSX2 The transmit analog input and the output for transmit gain adjustment. The pin AIN1– (AIN2) connects to inverting input of the internal transmit amplifier, and the pin AIN1+ connects to non-inverting input of the internal transmit amplifier. The pin GSX1 (GSX2) connects to output of the internal transmit amplifier. Gain adjustment should be referred to Fig. 1. VFRO, AOUT+, AOUT-, PWI Used for the receive analog output and the output for receive gain adjustment. VFRO is an output of the receive filter. AOUT+ and AOUT– are differential analog signal outputs which can directly drive ZL = 350 W+120 nF or the 1.2 kW load. Gain adjustment should be referred to Fig. 1. These outputs are in high impedance state during power down. 6/38 ¡ Semiconductor MSM7708-02 SAO Differential analog output for a sounder. Variable tones including "Audio sound", "DTMF tone", "S tone", "F tone", and "R tone", and telephone call signals can be output to either VFRO pin or SAO pin by CR0 - B1 of the control register. These output pins are in the high impedance state during power down. AIN1– Vi C1 R1 Differential analog input signal C1 R2 – Reference voltage generator + AIN1+ R1 R2 GSX1 SGT + – AIN2 C2 R3 – to ENCODER + R4 GSX2 AOUT+ –1 Z L = 120 nF + 350 W Analog output signal Vo Transmit gain : (V GSX2 /V I ) = (R2/R1) ¥ (R4/R3) Receive gain : (V O /V VFRO ) = 2 ¥ (R6/R5) R6 – AOUT– + PWI R5 VFRO Sounder output signal from DECODER SAO Figure 1 Analog Interface 7/38 ¡ Semiconductor MSM7708-02 SGT, SGR Outputs of the analog signal ground voltage. SGT outputs the analog signal ground voltage of the transmit system, and SGR outputs the same for the receive system. The output voltage value is approximately 1.4 V. Connect bypass 10 mF and 0.1 mF (ceramic type) capacitors between these pins and the AG pin. To reduce the response time of the receiver power on, it is recommended to apply 1 mF and 0.1 mF bypass capacitors. During power down, the output changes to 0 V. VDD Power supply. DG, AG Ground. DG is the digital system ground. AG is the analog system ground. Since DG and AG are separated in the device, connect them as close as possible on the circuit board. PDN Power down control input. When set to a digital "0", the system changes to the power down state and control register is not reset. Since the power down mode is controlled by CRC0 - B5 of the control register ORed with the signal from the PDN pin, set CRC0 - B5 to digital "0" when using this pin. RESET Reset control input of the CODEC control register. When set to digital "0," each bit of the control register is reset and the internal circuit changes to the power down state. During normal operation, set this pin to digital "1". MCK Master clock input. The clock frequency is 19.2 MHz. MCK can be asynchronous with XSYNC, RSYNC, and BCLK. 8/38 ¡ Semiconductor MSM7708-02 PCMSO Transmit PCM data output. This PCM output signal is output from MSB synchronously with the rising edge of BCLK and XSYNC. PCMSI Transmit PCM data input. This signal is converted to the ADPCM data. The PCM signal is shifted in on the falling edge of BCLK. Normally, this pin is connected to PCMSO. PCMRO Receive PCM data output. This PCM signal is the output signal after ADPCM decoder processing. This signal is serially output from MSB synchronously with the rising edge of BCLK and RSYNC. PCMRI Receive PCM data input. This PCM input signal is shifted in on the rising edge of BCLK and is input from MSB. Normally, this pin is connected to PCMRO. IS Transmit ADPCM signal output. This signal is the output signal after ADPCM encoding, and is serially output from MSB synchronously with the rising edge of BCLK and XSYNC. This pin is an open drain output which remains in a high impedence state during power down. It requires pull-up resistor. IR Receive ADPCM signal input. This input signal is shifted in serially on the rising edge of BCLK synchronously with RSYNC and is input from MSB. BCLK Shift clock input for the PCM data (PCMSO, PCMSI, PCMRO, PCMRI) and the ADPCM data(IS, IR) . The frequency is in the 64 kHz to 2048 kHz range. XSYNC 8 kHz synchronous signal input for transmit PCM and ADPCM data. This signal should be synchronized with BCLK. XSYNC is used for indicating the MSB of the transmit serial PCM and ADPCM data stream. RSYNC 8 kHz synchronous signal input for receive PCM and ADPCM data. This signal should be synchronized with BCLK signal. RSYNC is used for indicating the MSB of the receive serial PCM and ADPCM data stream. 9/38 ¡ Semiconductor MSM7708-02 VOXO Transmit side voice/silence detect signal output. This output is valid when CR6 - B7 is set to "1". VOXO shows the presence or absence of the transmit voice signal by detecting the signal. "1" and "0" set to this pin correspond to the presence and the absence, respectively. This result also appears at the register data CR7 - B7. The signal detect threshold is set by the control register CR6 - B6, B5. When control register CR0 - B6 is set to "1" and VOXI input is "1" during the voice detection (VOXO = "1"), receive signal is automatically suppressed by 6 dB. VOXI Receive side voice/silence detect signal input. This output is valid when CR6 - B7 is set to "1". A "1" level at VOXI indicates the presence of voice signal, in which case the decoder block processes normal receive signal and the voice signal appears at analog output pins. A "0" level indicates the absence of voice signal, in which case the background noise generated in this device is transferred to the analog output pins. The background noise amplitude is set by the control register CR6 - B1, B0. Since this signal is ORed with the register CR6 - B3, set the control register CR6 - B3 to "0" when using this pin. When control register CR0 - B6 is set to "1" and VOXI input is "1" during the voice detection (VOXO = "1") receive signal is automatically suppressed by 6 dB. Input voice signal GSX2 pin Voice VOXO pin Silence Voice Detection Time TVXON Voice Silence Detection Time (Hangover Time) TVXOFF (a) Transmission Side Voice/Silence Detect Function Timing Diagram VOXI pin Voice Silence Regenerated Voice Signal Generation Time Internal Background Noise Generation Time Voice Regenerated voice VFRO pin (b) Receive Side Voice/Silence Detect Function Timing Diagram Note: The VOXO and VOXI pin functions are enabled when CR6 - B7 is set to "1". Figure 2 Voice/Silence Detect Function 10/38 ¡ Semiconductor MSM7708-02 , , DEN, EXCK, DIN, DOUT Serial control ports for MCU interface. Reading and writing data is performed by an external CPU through these pins. 14-byte control registers (CR0 - 13) are provided in this device. DEN is the "Enable" control signal input, EXCK is the data shift clock input, DIN is the address and data input, and DOUT is the data output. Input/output timing is shown in Fig. 3. DEN EXCK DIN W A3 A2 A1 DOUT A0 B7 B6 B5 B4 B3 B2 B1 B0 B3 B2 B1 B0 High Impedance (a) Write Data Timing Diagram DEN EXCK DIN DOUT R A3 High Impedance A2 A1 A0 B7 B6 B5 B4 (b) Read Data Timing Diagram Figure 3 MCU Interface Input/Output Timing MUTE This pin is used to enable the receive side voice path mute level. To set the mute level, set this pin to "1". MLV0, MLV1, MLV2 This pin is used to set the receive side voice path mute level. For the control method, refer to the control register description (CR1). Since these signals are ORed with CR1 - B2, B1, and B0 internally, set these register data to "0" when using this pin. 11/38 ¡ Semiconductor MSM7708-02 The register map is shown in Table 1. Table 1 Control Register (CR0 to CR13) Map Address Register Name A3 A2 A1 A0 Data Description B7 A/m Spprs SEL ON TX RX MUTE ON/OFF TX TX GAIN3 GAIN2 Side Tone Side Tone GAIN2 GAIN1 DTMF/ TONE OTHERS SEL SEND SEND/ ROW/ REC SR VOX ON ON/OFF LVL1 VOX SILENCE OUT LVL1 CR0 0 0 0 0 CR1 0 0 0 1 CR2 0 0 1 0 CR3 0 0 1 1 CR4 0 1 0 0 CR5 0 1 0 1 CR6 0 1 1 0 CR7 0 1 1 1 CR8 1 0 0 0 ST0 CR9 1 0 0 1 CR10 1 0 1 CR11 1 0 CR12 1 CR13 1 Note : B6 B5 R/W B3 B2 B1 B0 PDN PDN ALL TX ADPCM TX RESET ON/OFF TX TX GAIN1 GAIN0 Side Tone TONE GAIN0 ON/OFF PDN RX RX MUTE RX GAIN3 TONE GAIN3 SA,VF OUT RX MLV2 RX GAIN2 TONE GAIN2 SAO/ VFRO RX MLV1 RX GAIN1 TONE GAIN1 AOUT PON RX MLV0 RX GAIN0 TONE GAIN0 TONE4 TONE3 TONE2 TONE1 TONE0 R/W — CMD1 CMD0 R/W TONE5 B4 R/W R/W R/W R/W 4M8M/ 1M ON LVL0 SILENCE LVL0 — — OFF TIME VOX IN — — — BUSY RPM R ST1 ST2 ST3 ST4 ST5 ST6 ST7 R/W ST8 ST9 ST10 ST11 ST12 — — — R/W 0 SPY0 SPY1 SPY2 SPY3 SPY4 SPY5 SPY6 SPY7 R/W 1 1 SP0 SP1 SP2 SP3 SP4 SP5 SP6 SP7 R/W 1 0 0 SP8 SP9 SP10 SP11 SP12 — — — R/W 1 0 1 CH0 CH1 CH2 CH3 CH4 — ADRD ADWT R/W RX NOISE RX NOISE RX NOISE LEVEL SEL LVL1 LVL0 R/W Details are explained in the Control Register Description. R/W: Both read and write are supported R: Read-only register 12/38 ¡ Semiconductor MSM7708-02 (Register Controllers) DIO This I/O pin is used to output the write data and fetch the read data. Connect this pin to the DIN and DOUT pins of the serial register and to the DOUT pin of the serial voice ROM. WE This output pin is used to select the read or write mode. Connect this pin to the WE pin of the serial register. SAD This pin is used to output the read/write start address data. Connect this pin to the SAD pin of the serial register and to the SADX pin of the serial voice ROM. SAS This clock output pin is used to write the serial address. Connect this pin to the SAS pin of the serial register and to the SASX and SASY pins of the serial voice ROM. TAS This output pin is used to set the serial address input from the SAD pin into the address counter inside the serial register/serial voice ROM. Connect this pin to the TAS pin of the serial register/serial voice ROM. RWCK This clock output pin is used to write or read data to or from the serial register. Connect this pin to the RWCK pin of the serial register and to the RDCK pin of the serial voice ROM. CS1, CS2 CS1 and CS2 are chip select pins. Connect CS1 to the CS pin of the serial register, and CS2 to the CS pin of the serial voice ROM. 13/38 ¡ Semiconductor MSM7708-02 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit Power Supply Voltage VDD Analog Input Voltage VAIN — –0.3 to +5 V — –0.3 to VDD + 0.3 V Digital Input Voltage –0.3 to VDD + 0.3 V VDIN — Operating Temperature Top — –25 to +70 °C Storage Temperature TSTG — –55 to +150 °C RECOMMENDED OPERATING CONDITIONS Parameter Symbol (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Typ. Min. Max. Unit Condition Power Supply Voltage VDD Voltage must be fixed High Level Input Voltage VIH To all digital input pins Low Level Input Voltage VIL To all digital input pins 0 — Digital Input Rise Time tIr To all digital input pins — — 50 ns Digital Input Fall Time tIf To all digital input pins — — 50 ns RDL IS (Pull-up resistor) 500 — — W CDL To all digital output pins — — 100 pF Digital Output Load 2.7 0.45 ¥ VDD — 3.6 V — VDD V 0.16 ¥ VDD V CSGT Between SGT and AG 10 + 0.1 — — mF CSGR Between SGR and AG 1 — — mF Master Clock Frequency FMCK MCK –0.01% 19.2 0.01% MHz Master Clock Duty Ratio DMCK MCK 40 50 60 % Bit Clock Frequency FBCK 64 — 2048 kHz Synchronous Signal Frequency FSYNC XSYNC, RSYNC — 8.0 — kHz Clock Duty Ratio DCK 40 50 60 % Bypass Capacitor for SG BCLK BCLK, EXCK Transmit Sync Pulse Setting Time tXS, tSX BCLK´XSYNC 100 — — ns Receive Sync Pulse Setting Time tRS, tSR BCLK´RSYNC 100 — — ns Synchronous Signal Width tWS 1 BCLK — 100 ms PCM, ADPCM Setup Time tDS — 100 — — ns PCM, ADPCM Hold Time tDH — 100 — — ns XSYNC, RSYNC Fig.4 14/38 ¡ Semiconductor MSM7708-02 ELECTRICAL CHARACTERISTICS DC Characteristics (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Parameter Symbol IDD1 Power Supply Current IDD2 Input Leakage Current High Level Output Voltage Condition When operating (When no signal, and VDD = 3.0 V) When powered down (When VDD = 3.0 V) IIH VI = VDD IIL VI = 0 V Min. Typ. Max. Unit — 6.0 11.0 mA — 0.02 0.1 mA — — 2.0 mA — — 0.5 mA VOH1 IOH = 0.4 mA 0.5 ¥ VDD — VDD V VOH2 IOH = 1 mA 0.8 ¥ VDD — VDD V (IS pin is pulled up with 0 0.2 0.4 V 500 W resistor) IS pin — — 10 mA — 5 — pF IOL = –1.2 mA Low Level Output Voltage VOL Output Leakage Current IO Input Capacitance CIN — 15/38 ¡ Semiconductor MSM7708-02 Analog Interface Characteristics (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Parameter Input Resistance Output Resistance Load Output Capacitance Load Symbol Condition Min. Typ. Max. Unit RIN AIN+, AIN–, AIN2, PWI 10 — — MW RL1 GSX1, GSX2, VFRO, SAO 20 — — kW RL2 AOUT+, AOUT– 1.2 — — kW CL1 GSX1, GSX2, VFRO, SAO — — 100 pF CL2 AOUT+, AOUT– — — 100 pF — — 1.3 VPP — — 1.3 VPP VO1 Output Voltage Level (*1) VO2 GSX1, GSX2, VFRO, SAO(RL = 20 kW) AOUT+, AOUT– (RL = 1.2 kW) VOF1 VFRO, SAO –100 — +100 mV VOF2 GSX1, GSX2, AOUT+, AOUT– –20 — +20 mV SGT, SGR Output Voltage VSG SGT, SGR — 1.4 — V SGT Output Impedance RSGT SGT — 40 80 kW SGR Output Impedance RSGR SGR — 8 12 kW Offset Voltage *1 –7.7 dBm (600 W) = 0 dBm0, +3.14 dBm0 = 1.30 VPP. Digital Interface Characteristics (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Parameter Digital Output Delay Time PCM, ADPCM Interface Serial Port Digital I/O Timing Characteristics EXCK Clock Frequency Symbol Condition Reference tSDX, tSDR 1 LSTTL + 100 pF tXD1, tRD1 pull-up resistor : 500 W Fig. 4 Items in parenthesis tXD2, tRD2 mean C load = 10 pF, and tXD3, tRD3 the pull-up resistor £ 2 kW t1 Min. Typ. Max. Unit 0 — 200 (100) ns 0 — 200 (100) ns 0 — 200 (100) ns 0 — 200 (100) ns 50 — — ns t2 50 — — ns t3 50 — — ns t4 50 — — ns t5 100 — — ns 50 — — ns t6 t7 C load = 50 pF Fig. 5 50 — — ns t8 0 — 100 ns t9 50 — — ns t10 50 — — ns t11 0 — 50 ns t12 200 — — ns — — 10 MHz FEXCK EXCK — 16/38 ¡ Semiconductor MSM7708-02 Serial Register Interface Characteristics (VDD = 2.7 V to 3.6 V, Ta = –25˚C to +70˚C) Parameter Symbol Condition Reference Min. Typ. Max. Unit — — 200 ns — — 200 ns — — 10 ms Control Register Data Input tCRW Write tCRR Reset Busy Bit tBSR tBSH Setup time Valid time — — 450 ms tRPR Setup time — — 15 ms tRPF Hold time after stop command — — 140 ms RPM Bit Fig. 6 17/38 ¡ Semiconductor MSM7708-02 AC Characteristics (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Parameter Symbol Condition Frequency (Hz) Level dBm0 Min. Typ. Max. Unit LOSS T1 0 to 60 25 — — dB LOSS T2 300 to 3000 –0.15 — +0.20 dB Transmit Frequency LOSS T3 1020 Response LOSS T4 3300 dB Receive Frequency Response Transmit Signal to Distortion Ratio (*1) Receive Signal to Distortion Ratio (*1) Transmit Gain Tracking Receive Gain Tracking 0 Reference dB –0.15 — +0.80 LOSS T5 3400 0 — 0.80 dB LOSS T6 3968.75 13 — — dB LOSS R1 0 to 3000 –0.15 — +0.20 dB LOSS R2 1020 LOSS R3 3300 dB Reference 0 dB –0.15 — +0.80 LOSS R4 3400 0 — 0.80 dB LOSS R5 3968.75 13 — — dB SD T1 3 35 — — dB SD T2 0 35 — — dB SD T3 –30 35 — — dB SD T4 –40 28 — — dB 1020 SD T5 –45 23 — — dB SD R1 3 35 — — dB SD R2 0 35 — — dB –30 35 — — dB SD R4 –40 28 — — dB SD R5 –45 23 — — dB GT T1 3 –0.2 — +0.2 dB SD R3 1020 GT T2 dB Reference –10 –40 –0.2 — +0.2 dB GT T4 –50 –0.5 — +0.5 dB GT T5 –55 –1.2 — +1.2 dB GT R1 3 –0.2 — +0.2 dB GT R2 –10 GT T3 1020 dB Reference –40 –0.2 — +0.2 dB GT R4 –50 –0.5 — +0.5 dB GT R5 –55 –1.2 — +1.2 dB GT R3 1020 *1 P-message filter used 18/38 ¡ Semiconductor MSM7708-02 AC Characteristics (Continued) (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Parameter Idle Channel Noise (*1) Absolute Level (*3) Symbol Condition Min. Typ. — — — — — — GSX2 0.285 0.320 0.359 Vrms VFRO 0.285 0.320 0.359 Vrms 30 — — dB 30 — — dB Frequency (Hz) Level dBm0 Other NIDLT — AIN = SG NIDLR — (*2) 1020 0 AVT AVR Power Supply Noise PSRRT Noise frequency: Rejection Ratio PSRRR Noise level: 0 to 50 kHz 50 mVpp — Max. Unit –68 (–75.7) dBmOp –72 (dBmp) (–79.7) *1 P-message filter used *2 PCMRI input: "11010101" (A-law), "11111111" (m-law) *3 0.320 Vrms = 0 dBm0 = –7.7 dBm (600 W) ADPCM unit characteristics are fully compliant with ITU-T Recommendation G.721. AC Characteristics (DTMF and Other Tones) Parameter Frequency Deviation Tone Reference Output Level (*1) (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Condition Symbol Min. Typ. Max. Unit DFT1 DTMF tones, Other various tones –1.5 — +1.5 % DFT2 Tone scale –1.0 — +1.0 % VTL Transmit side tone DTMF (low group) –18 –16 –14 dBm0 VTH (Gain setting 0 dB) DTMF (high group), other –16 –14 –12 dBm0 VRL Receive side tone –10 –8 –6 dBm0 VRH (Gain setting –6 dB) DTMF (high group), other –8 –6 –4 dBm0 VTH/VTL, VRH/VRL 1 2 3 dB DTMF Tone Level Relative Value RDTMF DTMF (low group) *1. Not including programmable gain set values AC Characteristics (Gain Settings) (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Parameter Transmit/Receive Gain Setting Accuracy Condition Symbol DG For all gain set values AC Characteristics (Voice/Silence Detect Function) Parameter Transmit Voice/Silence Detection Time Transmit Voice Detection Level Accuracy Condition Symbol TVXON SilenceÆvoice VOXO pin: See Fig. 2 TVXOF VoiceÆsilence DVX Voice/silence differential: 10 dB For detection level set values by CRM6 - B6, B5 Min. Typ. Max. Unit –1 0 +1 dB (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Min. Typ. Max. Unit — 5 — ms 140/300 160/320 180/340 –2.5 0 2.5 ms dB 19/38 ¡ Semiconductor MSM7708-02 TIMING DIAGRAM Transmit Side PCM, ADPCM Timing 0 BCLK tXS XSYNC 1 tSX 2 tWS tXD1 tXD2 3 4 5 6 7 8 10 tXD3 LSB MSB PCMSO 9 tSDX BCLK 0 tXS XSYNC 1 tSX 2 tXD1 tXD2 IS 3 4 5 6 7 8 9 10 5 6 7 8 9 10 9 10 tXD3 LSB MSB tSDX Receive Side PCM, ADPCM Timing 0 tRS BCLK 1 tSR 2 3 4 tWS RSYNC tDS tDH IR tXD3 MSB BCLK 0 tRS LSB 1 tSR 2 3 tRD1 tRD2 4 5 6 7 8 RSYNC tRD3 LSB MSB PCMRO tSDX Figure 4 PCM, ADPCM Interface Serial Port Timing for Microcontroller Interface DEN 1 EXCK t1 DIN 2 3 4 t3 5 t6 t4 W/R t12 t10 t5 t2 A3 A2 6 11 12 t9 t7 A1 A0 B7 B1 B0 t11 t8 DOUT B7 B1 B0 Figure 5 Serial Control Port Interface 20/38 ¡ Semiconductor MSM7708-02 Address Write/Read Mode Timing DEN EXCK DIN (CR13) X X (ADWT, ADRD) CR13-(B1, B0) tCRW (X, X) (0, 0) tCRR BUSY tBSR Serial Register I/F Address Data Transfer tBSH Record/Playback Mode Timing DEN EXCK DIN (CR5) CR5-(B1, B0) X X "1" (PLAY/REC) "1" (STOP) tCRW (X, X) (0, 0) tCRR tRPF RPM tRPR Serial Register I/F Record/Playback Data Transfer Figure 6 Serial Register Interface 21/38 ¡ Semiconductor MSM7708-02 FUNCTIONAL DESCRIPTION Control Register Description (1) CR0 (Basic Operation Mode Settings) B7 A/m CR0 SEL Initial value 0 B6 — 0 B5 B4 B3 B2 B1 B0 PDN PDN PDN SA, VF SAO/ AOUT ALL TX RX OUT VFRO PON 0 0 0 0 0 0 B7: .............. PCM interface companding law selection 0: m-law1: A-law B6: .............. Automatic suppression function control 0: suppression off 1: suppression on When transmit voice is detected, receive level is suppressed automatically by 6 dB. B5: .............. Power down (entire unit) 0: Power ON 1: Power down ORed with the inverted external power down signal. When using this data, set PDN to "1". B4: .............. Power down (transmit side only) 0: Power ON 1: Power down B3: .............. Power down (receive side only) 0: Power ON 1: Power down B2: .............. The sounder output amp (SAO) and receiver system output amp (VFRO) operation control 0: The output pin selected by CR0 - B1 operates. 1: The sounder system output (SAO) and receiver system output (VFRO) both operate. B1: .............. Selection of sounder system output (SAO) or receiver system output 0: VFRO 1: SAO SGR potential is output to the non selected pin. B0: .............. AOUT+, AOUT– power on control 0: AOUT+, – power down 1: AOUT+, – power on 22/38 ¡ Semiconductor MSM7708-02 (2) CR1 (ADPCM Operation Mode Settings) B7 CR1 Initial value B6 B5 B4 B3 B2 B1 B0 TX RX ADPCM TX RX RX RX RX MUTE ON/OFF RESET ON/OFF MUTE MLV2 MLV1 MLV0 0 0 0 0 0 0 0 0 B7: .............. Transmit side ADPCM data MUTE 1: MUTE B6: .............. Receive side PCM signal ON/OFF 0: ON 1: OFF B5: .............. Transmit/Receive side ADPCM RESET (in accordance with the G.721) 1: RESET B4: .............. Transmit side PCM signal ON/OFF 0: ON 1: OFF PCM idle pattern is transmitted when set OFF B3: .............. Receive side ADPCM data MUTE 1: MUTE Mute operation set by B2, 1, 0 is available, provided this bit is valid when MUTE pin is "0". B2, 1, 0: ......Receive side voice path mute level settings (MLV2, MLV1, MLV0) = (0, 0, 0) : through (0, 0, 1) : –6 dB (0, 1, 0) : –12 dB (0, 1, 1) : –18 dB (1, 0, 0) : –24 dB (1, 0, 1) : –30 dB (1, 1, 0) : –36 dB (1, 1, 1) : MUTE Note: The above settings are not applied to various tone, side tone, and background noise. 23/38 ¡ Semiconductor MSM7708-02 (3) CR2 (PCM CODEC Operation Mode Settings and Transmit/Receive Gain Adjustment) B7 CR2 Initial value B5 B6 B2 B3 B4 B0 B1 TX TX TX TX RX RX RX RX GAIN3 GAIN2 GAIN1 GAIN0 GAIN3 GAIN2 GAIN1 GAIN0 0 0 0 0 0 0 0 0 B7, B6, B5, B4: .... Transmit side signal gain adjustment (refer to Table 2) B3, B2, B1, B0: .... Receive side signal gain adjustment (refer to Table 2) Table 2 Transmit/Receive Gain Settings B7 B6 B5 B4 Transmit Side Gain B3 B2 B1 B0 Receive Side Gain 1 0 0 0 –16 dB 1 0 0 0 –16 dB 1 1 0 1 –14 dB 1 1 0 1 –14 dB 1 0 1 0 –12 dB 1 0 1 0 –12 dB 1 0 1 1 –10 dB 1 0 1 1 –10 dB 1 1 0 0 –8 dB 1 1 0 0 –8 dB 1 1 0 1 –6 dB 1 1 0 1 –6 dB 1 1 1 0 –4 dB 1 1 1 0 –4 dB 1 1 1 1 –2 dB 1 1 1 1 –2 dB 0 0 0 0 0 dB 0 0 0 0 0 dB 0 0 0 1 +2 dB 0 0 0 1 +2 dB 0 0 1 0 +4 dB 0 0 1 0 +4 dB 0 0 1 1 +6 dB 0 0 1 1 +6 dB 0 1 0 0 +8 dB 0 1 0 0 +8 dB 0 1 0 1 +10 dB 0 1 0 1 +10 dB 0 1 1 0 +12 dB 0 1 1 0 +12 dB 0 1 1 1 +14 dB 0 1 1 1 +14 dB The above gain settings table shows the transmit/receive voice signal gain settings and the transmit side gain settings for DTMF tones and other tones. Tone signal transmission is enabled by CR4 - B6 (discussed later), and the gain setting is set to the levels shown below. DTMF tones (low group): ................................. –16 dBm0 DTMF tones (high group) and other tones: ... –14 dBm0 For example, if the transmit gain set value is set to +8 dB (B7, B6, B5, B4) = (0, 1, 0, 0), then the following tones appear at the PCMSO pin. DTMF tones (low group): ................................. –8 dBm0 DTMF tones (high group) and other tones: ... –6 dBm0 However, the gain of the receive side tone and the gain of the side tones (path from transmit side to receive side) are set by the CR3 register. 24/38 ¡ Semiconductor MSM7708-02 (4) CR3 (Side Tone and Tone Generator Gain Adjustment) B5 B6 B7 Initial value B0 TONE TONE TONE TONE TONE GAIN2 GAIN1 GAIN0 ON/OFF GAIN3 GAIN2 GAIN1 GAIN0 0 0 0 0 0 0 0 0 Side Tone Side Tone Side Tone CR3 B1 B2 B3 B4 B7, B6, B5: ........ Side tone gain adjustment (refer to Table 3) B4: ..................... Tone generator ON/OFF 0: OFF 1: ON B3, B2, B1, B0: . Tone generator Receive side gain adjustment (refer to Table 4) Table 3 Side Tone Gain Settings B7 B6 B5 Side Tone Gain 0 0 0 OFF 0 0 1 –15 dB 0 1 0 –13 dB 0 1 1 –11 dB 1 0 0 – 9 dB 1 0 1 – 7 dB 1 1 0 – 5 dB 1 1 1 – 3 dB Table 4 Receive Side Tone Generator Gain Settings B3 B2 B1 B0 Tone Generator Gain B3 B2 B1 B0 Tone Generator Gain 0 0 0 0 –36 dB 1 0 0 0 –20 dB 0 0 0 1 –34 dB 1 0 0 1 –18 dB 0 0 1 0 –32 dB 1 0 1 0 –16 dB 0 0 1 1 –30 dB 1 0 1 1 –14 dB 0 1 0 0 –28 dB 1 1 0 0 –12 dB 0 1 0 1 –26 dB 1 1 0 1 –10 dB 0 1 1 0 –24 dB 1 1 1 0 – 8 dB 0 1 1 1 –22 dB 1 1 1 1 – 6 dB The receive side tone generator gain settings shown in Table 4 are set with the following levels as a reference. DTMF tones (low group): ................................. –2 dBm0 DTMF tones (high group) and other tones: ... 0 dBm0 For example, if the tone generator gain set value is set to –6 dB (B3, B2, B1, B0)=(1, 1, 1, 1), then tones at the following levels appear at the SAO or VFRO pin. DTMF tones (low group): ................................. –8 dBm0 DTMF tones (high group) and other tones: ... –6 dBm0 25/38 ¡ Semiconductor MSM7708-02 (5) CR4 (Tone Generator Operation Mode and Frequency Settings) B7 CR4 B6 DTMF/ TONE OTHERS SEL SEND 0 0 Initial value B5 B4 B3 B2 B1 B0 TONE5 TONE4 TONE3 TONE2 TONE1 TONE0 0 0 0 0 0 0 B7: ........................... Selection of DTMF signal and other tones (S tone, F tone, R tone, etc.) 0: Other tones 1: DTMF tones B6: ........................... Transmission side tone transmit 0: Voice signal transmit 1: Tone transmit B5, B4, B3, B2, B1, B0: .. Tone frequency setting (refer to Table 5) Table 5 DTMF Signal and Other Tone Settings (a) When B7 = 1 (DTMF Tones) B5 B4 B3 B2 B1 B0 Description B5 B4 B3 B2 B1 B0 Description * * 0 0 0 0 697 Hz + 1209 Hz * * 1 0 0 0 852 Hz + 1209 Hz * * 0 0 0 1 697 Hz + 1336 Hz * * 1 0 0 1 852 Hz + 1336 Hz * * 0 0 1 0 697 Hz + 1477 Hz * * 1 0 1 0 852 Hz + 1477 Hz * * 0 0 1 1 697 Hz + 1633 Hz * * 1 0 1 1 852 Hz + 1633 Hz * * 0 1 0 0 770 Hz + 1209 Hz * * 1 1 0 0 941 Hz + 1209 Hz * * 0 1 0 1 770 Hz + 1336 Hz * * 1 1 0 1 941 Hz + 1336 Hz * * 0 1 1 0 770 Hz + 1477 Hz * * 1 1 1 0 941 Hz + 1477 Hz * * 0 1 1 1 770 Hz + 1633 Hz * * 1 1 1 1 941 Hz + 1633 Hz 26/38 ¡ Semiconductor MSM7708-02 (b) When B7 = 0 (Other than DTMF Tones) Description B5 B4 B3 B2 B1 B0 B5 B4 B3 B2 B1 B0 Description 0 0 0 0 0 784.0 Hz (G) 1 0 0 0 0 0 1100 Hz 0 0 0 0 0 1 830.6 Hz (G+) 1 0 0 0 0 1 1200 Hz 0 0 0 0 1 0 880.0 Hz (A) 1 0 0 0 1 0 1300 Hz 0 0 0 0 1 1 932.3 Hz (A+) 1 0 0 0 1 1 1400 Hz 0 0 0 1 0 0 987.8 Hz (B) 1 0 0 1 0 0 1500 Hz 0 0 0 1 0 1 1046.5 Hz (C) 1 0 0 1 0 1 1600 Hz 0 0 0 1 1 0 1108.7 Hz (C+) 1 0 0 1 1 0 1700 Hz 0 0 0 1 1 1 1174.7 Hz (D) 1 0 0 1 1 1 1800 Hz 0 0 1 0 0 0 1244.5 Hz (D+) 1 0 1 0 0 0 1900 Hz 0 0 1 0 0 1 1318.5 Hz (E) 1 0 1 0 0 1 2000 Hz 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 1 1 1 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 1 0 Tone Scale 0 1396.9 Hz (F) 1 0 1 0 1 0 2100 Hz 1480.0 Hz (F+) 1 0 1 0 1 1 2200 Hz 1568.0 Hz (G) 1 0 1 1 0 0 2300 Hz 1661.2 Hz (G+) 1 0 1 1 0 1 2400 Hz 0 1760.0 Hz (A) 1 0 1 1 1 0 2500 Hz 1 1864.7 Hz (A+) 1 0 1 1 1 1 2600 Hz 0 0 1975.5 Hz (B) 1 1 0 0 0 0 2700 Hz 0 1 2093.0 Hz (C) 1 1 0 0 0 1 2800 Hz 0 1 0 2217.5 Hz (C+) 1 1 0 0 1 0 2900 Hz 0 1 1 2349.3 Hz (D) 1 1 0 0 1 1 3000 Hz 0 1 0 0 2489.0 Hz (D+) 1 1 0 1 0 0 2760 Hz 0 1 0 1 2637.0 Hz (E) 1 1 0 1 0 1 — 1 0 1 1 0 2793.8 Hz (F) 1 1 0 1 1 0 — 0 1 0 1 1 1 2960.0 Hz (F+) 1 1 0 1 1 1 — 0 1 1 0 0 0 3136.0 Hz (G) 1 1 1 0 0 0 — 0 1 1 0 0 1 400 Hz 1 1 1 0 0 1 — 0 1 1 0 1 0 500 Hz 1 1 1 0 1 0 — 0 1 1 0 1 1 600 Hz 1 1 1 0 1 1 — 0 1 1 1 0 1 700 Hz 1 1 1 1 0 0 — 0 1 1 1 0 1 800 Hz 1 1 1 1 0 1 — 0 1 1 1 1 0 900 Hz 1 1 1 1 1 0 — 0 1 1 1 1 1 1000 Hz 1 1 1 1 1 1 — 27/38 ¡ Semiconductor MSM7708-02 (6) CR5 (Serial Register Interface Control) CR5 Initial value B7 B6 B5 SEND/ ROM/ 4M8M/ REC SR 1M 0 0 0 B4 B3 B2 B1 B0 — — — CMD1 CMD0 0 0 0 0 0 B7: .............. Connection between register and ADPCM 0: with ADPCM receive side 1: ADPCM Transmit side B6: .............. Voice ROM/Serial register selection 0: Serial Register 1: Voice ROM B5: .............. Connecting serial register capacity 0: 1 Mb (MSM63V89C) 1: 4 Mb (MSM6684), 8 Mb (MSM6685) B4 - B2: ......Reserved for test. Should be set "0" B1, B0: .......Serial register I/F Instruction command (CMD1, CMD0) = (0, 0) : NOP (0, 1) : PLAY (Playback) (1, 0) : REC (Recording) (1, 1) : STOP (Stop) * (CMD1, CMD0) are reset (0, 0) after command execution. Instruction commands of Play and REC should not be set when busy (CR5 - B1) and RPM (CR5 - B0) are "1". (7) CR6 (VOICE/SILENCE Detect Function Control) CR6 Initial value B7 B6 B5 B4 B3 VOX ON ON OFF VOX ON/OFF LVL1 LVL0 TIME IN LEVEL SEL LVL1 LVL0 0 0 0 0 0 0 0 0 B2 B1 B0 RX NOISE RX NOISE RX NOISE B7: .............. Voice/Silence detect function ON/OFF 0: OFF 1: ON B6, B5: .......Transmit side voice/silence detector level settings (0,0): –20 dBm0 (0,1): –25 dBm0 (1,0): –30 dBm0 (1,1): –35 dBm0 B4: .............. Hangover time (refer to Fig. 1) settings 0: 160 ms 1: 320 ms B3: .............. Receive side Voice/Silence detect input signal 0: Internal background noise transmit 1: Voice receive signal transmit When using this data, set the VOXI pin to "0". B2: .............. Receive side background noise level setting 0: Internal automatic setting 1: External (by B1, B0) setting Internal automatic setting Æ Set to the voice signal level when B3 (VOXI) changes from "1" to "0". B1, B0: .......External setting background noise level (0,0): No noise (0,1): –55 dBm0 (1,0): –45 dBm0 (1,1): –35 dBm0 28/38 ¡ Semiconductor MSM7708-02 (8) CR7 (Detect Register: Read-only) B7 VOX CR7 Initial value Note: B6 B5 Silent Level Silent Level OUT 1 0 0 0 0 B4 B3 B2 B1 B0 — — — Busy RPM 0 0 0 0 0 B7: .............. Transmit side voice/silence detection 0: Silence 1: Voice B6, B5: .......Transmit side silence level (indicator) (0,0):Below –60 dBm0 (0,1): –50 to –60 dBm0 (1,0): –40 to –50 dBm0 (1,1): Above –40 dBm0 These outputs are enabled when the voice/silence detect function is turned on by CR6 - B7. B4, B3, B2: .Not used B1: .............. Serial Register I/F monitoring Monitors address read and write operation of serial register interface. 0: Stop 1: Read or Write B0: .............. Monitors serial register recording or playback. 0: Stop 1: Recording or playing back 29/38 ¡ Semiconductor MSM7708-02 (9) CR8 (Start X address 0-7) CR8 Initial value B7 B6 B5 B4 B3 B2 B1 B0 ST0 ST1 ST2 ST3 ST4 ST5 ST6 ST7 0 0 0 0 0 0 0 0 CR9 (Start X address 8-12) CR9 Initial value B7 B6 B5 B4 B3 B2 B1 B0 ST8 ST9 ST10 ST11 ST12 — — — 0 0 0 0 0 0 0 0 CR8 (B7 - B0), CR9 (B7 - B3): Record and Playback start address store register (10) CR10 (Stop Y address 0-7) CR10 Initial value B7 B6 B5 B4 B3 B2 B1 B0 SPY0 SPY1 SPY2 SPY3 SPY4 SPY5 SPY6 SPY7 0 0 0 0 0 0 0 0 CR10 (B7 - B0): Record and Playback stop Y address store register (11) CR11 (Stop X address 0-7) CR11 Initial value B7 B6 B5 B4 B3 B2 B1 B0 SP0 SP1 SP2 SP3 SP4 SP5 SP6 SP7 0 0 0 0 0 0 0 0 CR12 (Stop X address 8-12) CR12 Initial value B7 B6 B5 B4 B3 B2 B1 B0 SP8 SP9 SP10 SP11 SP12 — — — 0 0 0 0 0 0 0 0 CR11 (B7 - B0), CR12 (B7 - B3): Record and Playback stop X address store register Note: The data in CR8 - CR12 may be changed under the following conditions. If so, rewrite the data. (1) When REC or Play command is executed during the state of start address = stop address (2) When stop command is executed during the state of no operation of serial register interface (Busy = RPM = "0") 30/38 ¡ Semiconductor MSM7708-02 (12) CR13 (Channel Selection) CR13 Initial value B7 B6 B5 B4 B3 B2 B1 B0 CH0 CH1 CH2 CH3 CH4 — ADRD ADWT 0 0 0 0 0 0 0 0 B7 - B3 .......Channel selection (All 32 channels are selected with Hex cord) B2 ............... Since reserved for TEST, this bit should always be set to "0". B1 ............... Address read instruction 0: NOP 1: When set to "1", start/stop address corresponding to the channels specified by B7 to B3 is transferred from serial register channel index area to CR8 - CR12. After transfer, this bit is reset to "0". B0 ............... Address write instruction 0: NOP 1: When set to "1", start/stop address corresponding to the channels specified by B7 to B3 is transferred from CR8 - CR12 to serial register channel index area. After transfer, this bit is reset to "0". Note : Writing to ADRD and ADWT is inhibited when BUSY (CR7 - B1) or RPM (CR7 - B0) is "1". 31/38 ¡ Semiconductor MSM7708-02 DATA CONFIGURATION IN THE EXTERNAL SERIAL REGISTER X Address Space The address space of the external serial register is accessed based on (word direction indicated by the X address) ¥ (1 Kb depth in Y direction). The maximum X address in word direction depends on the total memory of serial registers connected. Since the leading 32 words (32 Kb) of the serial register are used as the channel index area, X address 020h onward can be used as the voice data area. CR5-B5 0 1 1 Total Memory Capacity (device name) 1 Mb (MSM63V89C) 4 Mb (MSM6684) 8 Mb (MSM6685) Number of words 1K words 4K words 8K words X address* 000h to 3FFh 0000h to 0FFFh 0000h to 1FFFh * 0000h to 001Fh is used as the channel index area. , Y Address Space For 1 Kb ADPCM data in Y direction, 4 bits ¥ 256 samples = 1024 bits are stored in the 1 Kb memory area. One Y address is allocated to one sample (4 bits) of ADPCM data and addressing is made with 00h to FFh. X address (1 K words of 000h to 3FFh : 1 word = 1 Kb) 000h channel index area (32 words ¥ 1 Kb + 32 Kb) 1Mb serial register 01Fh 020h 3FFh ADPCM (voice) data area 1 Kb in Y direction 1 word = 1 Kb Y address 00h 01h FEh FFh 4 bit 4 bit 4 bit 4 bit Figure 7 Address Space of the 1 Mb Serial Register 32/38 ¡ Semiconductor MSM7708-02 Channel Index Area of the Serial Register One channel (1 Kb) of the channel index area consists of the 40 bits of address data. (1) Stop Y address The Y address is represented by 8 bits and addressing is made with 00h to FFh. (2) Start X address, stop X address The X address is represented by 16 bits (valid 13 bits). If, for example, the serial register is 1Mb, the 1K-word X address space is addressed with 000h to 3FFh. Address data Blank data 40-bit 16-bit 8-bit 16-bit Start X address Stop Y address Stop X address Start X address (ST0 to ST12) ST0 ST1 Stop Y address (SPY0 to SPY7) SPY0 SPY1 Stop X address (ST0 to SP12) SP0 SP1 ST11 ST12 — — — — — SPY6 SPY7 SP11 SP12 — Figure 8 Channel Index Area of the Serial Register 33/38 ¡ Semiconductor MSM7708-02 METHODS OF RECORDING AND PLAYBACK Recording Method (See the flow chart in Figure 9.) Recording (1) • Set up the connection between the serial register/ voice ROM and ADPCM transmit-receive system. (See Figure 11.) (CR5 - B7) N BUSY = 0? • Specify the serial register/voice ROM. (CR5 RPM = 0? B6) Y • Set the external capacity. (CR5 - B5) Basic setting • Set the NOP command. (CR5 - B1 = "0", B0 = "0") (2) • Set the start/stop address. (CR8 to CR12) (3) • Set the channel. (CR13 - B7 to B3) ST, SP • Set the ADWT (address write) instruction. (CR13 address setting - B1 = "0", B0 = "1") (4) • The start/stop address of the channel set by the Channel setting ADWT instruction is stored in the channel index (ADWT) area. When status register BUSY (CR7 - B1) changes from "1" to "0", storage is complete. N BUSY = 0? (5) • Start recording by setting the REC (recording) command (CR5 - B1 = "1", B0 = "0"). In this case, Y the basic setting of CR5 - B7 to B5 should be the REC same as (1). (6) • Check the recording start with the status register RPM bit (CR7 - B0 = "1"). N (7) • To interrupt during recording, set the STOP RPM = 1? (stop) command (CR5 - B1 = "1", B0 = "1"). Y In this case, to store the address counter contents in the channel index area as a new stop address, the following settings are required: STOP • Set the channel. • Set the ADWT instruction. • When the BUSY bit changes from "1" N RPM = 0? to "0", settings are complete. (8) • When the address counter reaches the Y stop address, recording is complete. Channel setting Check completion of recording with (ADWT) RPM bit = "0". Note: If the stop address value is smaller than the start address value, recording is made to the last address of the serial register. N (1) CR5 (2) CR8 to CR12 (3) CR13 (4) CR7 (5) CR5 Recording start (6) CR7 Recording start check (7) CR5 Recording stop CR13 CR7 BUSY = 0? Y N RPM = 0? Y (8) CR7 Recording completion check END Figure 9 Flow Chart of Recording 34/38 ¡ Semiconductor MSM7708-02 Playback Method (See the flow chart in Figure 10.) (1) • Set up the connection between the serial register/voice ROM and ADPCM transmit-receive system. (See Figure 11.) (CR5 B7) • Specify the serial register/voice ROM. (CR5 - B6) • Set the external capacity. (CR5 B5) • Set the NOP command. (CR5 B1 = "0", B0 = "0") (2) • Set the channel. (CR13 - B7 to B3) • Set the ADRD (address read) instruction. (CR13 - B1 = "1", B0 = "0") (3) • For playback of the voice ROM, set the start/stop address here. (4) • The start/stop address of the channel set by the ADRD instruction is fetched from the channel index area. When status register BUSY (CR7 - B1) changes from "1" to "0", fetching is complete. (5) • Start playback by setting the PLAY (playback) command (CR5 - B1 = "0", B0 = "1"). In this case, basic setting of CR5 - B7 to B5 should be the same as (1). (6) • Check the playback start with the status register RPM bit (CR7 - B0 = "1"). (7) • To stop playback set the STOP (stop) command (CR5 - B1 = "1", B0 = "1"). (8) • When the address counter reaches the stop address, playback is complete. Check completion of playback with RPM bit = "0". Playback N BUSY = 0? RPM = 0? Y Basic setting (1) CR5 Channel setting (ADRD) (2) CR13 Voice ROM ST, SP address setting (3) CR8 to 12 N BUSY = 0? (4) CR7 Y N PLAY (5) CR5 Playback start RPM = 1? (6) CR7 Playback start check Y STOP N (7) CR5 Playback stop RPM = 1? Y (8) CR7 Playback completion check END Figure 10 Flow Chart of Playback Note: If the stop address value is smaller than the start address value, playback is made to the last address of the serial register. 35/38 ¡ Semiconductor MSM7708-02 SIGNAL FLOW IN RECORDING/PLAYBACK When the serial register is connected to each ADPCM transmit and receive system, the flow of recording/playback signal is as follows: Transmit-side recording (CR5 – B7 = "1" + REC) ADPCM CODER A-IN Transmit-side playback (CR5 – B7 = "1" + PLAY) IS (ADPCM-OUT) A-IN ADPCM CODER IS (ADPCM-OUT) Serial register Serial register Receive-side recording (CR5 – B7 = "0" + REC) Receive-side playback (CR5 – B7 = "0" + PLAY) A-OUT ADPCM DE-CODER Serial register IR (ADPCM-IN) A-OUT ADPCM DE-CODER IR (ADPCM-IN) Serial register Figure 11 Signal Flow in Transmit/Receive Side Recording/Playback 36/38 1 mF + – 10 mF 1 mF Voice analog input (VI) Transmit gain (VGSX2/VI) = (R2/R1) ¥ (R4/R3) Receive gain (VO/VVFRO) = 2 ¥ R6/R5 Receiver output 1 mF R1 R2 1 mF R3 R4 R6 R5 ZL = 120 nF + 350 W Sounder output Basic control SGR AG DG AIN1+ AIN1– GSX1 AIN2 GSX2 VFRO PWI AOUT– AOUT+ SAO PCMSO IR PCMRO PCMRI BCLK XSYNC YSYNC VOXO VOXI MUTE MLV1 MLV2 MLV3 DIO WE SAD SAS TAS RWCK ADPCM receive data CS1 CS2 ADPCM control 1 Mb serial register MSM63V89C DIN DOUT WE SAD SAS TAS RWCK RFSH FAM TEST TEST RS/A CS 1 Mb serial voice ROM MSM6595A-XXX DOUT SADX SASX TAS RDCK SASY SADY TEST TEST CS 37/38 MSM7708-02 MCK PDN RESET EXCK DEN DIN DOUT ADPCM transmit data ¡ Semiconductor 10 mF 500 W IS PCMSI APPLICATION CIRCUIT 1 mF VDD SGT An application circuit is shown below using a 1 Mb serial register and a 1 Mb serial voice ROM. MSM7708 ¡ Semiconductor MSM7708-02 PACKAGE DIMENSIONS (Unit : mm) TQFP64-P-1010-0.50-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.26 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 38/38