E2U0043-28-82 ¡ Semiconductor MSM7716 ¡ Semiconductor This version: Aug. 1998 MSM7716 Previous version: Nov. 1996 Single Rail Linear CODEC GENERAL DESCRIPTION The MSM7716 is a single-channel CODEC CMOS IC for voice signals that contains filters for linear A/D and D/A conversion. Designed especially for a single-power supply and low-power applications, the device is optimized for applications for the analog interfaces of audio signal processing DSPs and digital wireless systems. The analog output signal can directly drive a ceramic type handset receiver. In addition, levels for analog outputs can be set by external control. FEATURES • Single power supply • Low power consumption Operating mode Power down mode • Digital signal input/output interface • Sampling frequency(fs) • Transmission clock frequency • Filter characteristics : +2.7 V to +3.6 V : : : : : : 24 mW Typ. 0.05 mW Typ. 14-bit serial code in 2's complement format 4 to 16 kHz fs ¥ 14 min., 2048 kHz max. when fs = 8 kHz, complies with ITU-T Recommendation G. 714 • Built-in PLL eliminates a master clock • Two input circuits in transmit section • Two output circuits in receive section • Transmit gain adjustable using an external resistor • Receive gain adjustable by external control 8 steps, 4 dB/step • Transmit mic-amp is eliminated by the gain setting of a maximum of 36 dB. • Analog outputs can drive a load of a minimum of 1 kW ; an amplitude of a maximum of 4.0 VPP with push-pull driving. • Built-in reference voltage supply • Package options: 32-pin plastic TSOP (TSOPI32-P-814-0.50-1K) (Product name : MSM7716TS-K) 30-pin plastic SSOP (SSOP30-P-56-0.65-K) (Product name : MSM7716GS-K) 1/22 ¡ Semiconductor MSM7716 BLOCK DIAGRAM MAO MAIN – + SW 1 – + SW 2 RC LPF 8th BPF PCMOUT 14 BIT ADCONV TCONT AUTO ZERO PLL PBO PBIN SG GEN SGC BCLK SG VR GEN VFO VOL SW 4 AUXO – + AOUT+ 5th LPF 14 BIT DACONV PWD RCONT PCMIN PWD logic SW CONT SW 3 – + – + RC LPF RTIM PDN SW 4 PWI AOUT– SYNC SW 3 CONT Logic VOL CONT DEN CDIN DCLK VDD AG DG 2/22 ¡ Semiconductor MSM7716 PIN CONFIGURATION (TOP VIEW) MAIN MAO NC NC PBO PBIN NC SGC AG AUXO AOUT+ AOUT– NC NC PWI VFO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 PDN SYNC NC NC NC BCLK PCMOUT PCMIN DG DEN CDIN NC NC NC DCLK VDD 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SGC PBIN PBO NC NC MAO MAIN NC NC PDN SYNC NC BCLK PCMOUT PCMIN NC : No connect pin 32-Pin Plastic TSOP AG AUXO AOUT+ AOUT– PWI VFO NC NC NC VDD DCLK NC CDIN DEN DG 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 NC : No connect pin 30-Pin Plastic SSOP 3/22 ¡ Semiconductor MSM7716 PIN AND FUNCTIONAL DESCRIPTIONS MAIN, MAO Transmit microphone input and the level adjustment. MAIN is connected to the noninverting input of the op-amp, and MAO is connected to the output of the op-amp. The level adjustment should be configured as shown below. During power saving and power down modes, the MAO output is in high impedance state. C1 R2 Microphone input MAO MAIN R1 – + R1 : variable R2 > 20 kW C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1) (F) Gain = R2/R1 < 63 SG PBIN, PBO Transmit handset input and the level adjustment. PBIN is connected to the noninverting input of the op-amp, and PBO is connected to the output of the op-amp. The level adjustment should be configured as shown below. During power saving and power down, the PBO output is in high impedance state. R4 Handset microphone input C2 PBO PBIN R3 – + R3 : variable R4 > 20 kW C2 > 1/(2 ¥ 3.14 ¥ 30 ¥ R3) (F) Gain = R4/R3 < 63 SG VDD Power supply pin for +2.7 to 3.6 V (Typically 3.0 V). AG Analog signal ground. DG Ground pin for the digital signal circuits. This ground is separated from the analog signal ground in this device. The DG pin must be connected to the AG pin on the printed circuit board. 4/22 ¡ Semiconductor MSM7716 VFO Receive filter output. The output signal has an amplitude of 2.0 VPP above and below the signal ground voltage when the digital signal of +3 dBm0 is input to PCMIN. VFO can drive a load of 20 kW or more. This output can be externally controlled in the level range of 0 to –28 dB in 4 dB increments. During power saving or power down, VFO output is at the voltage level (VDD/2) of SG with a high impedance state. PWI, AOUT+, AOUT– PWI is connected to the inverting input of the receive driver. The receive driver output is connected to the AOUT– pin. Thus, a receive level can be adjusted with the pins PWI, AOUT–, and VFO described above. The output of AOUT+ is inverted with respect to the output of AOUT– with a gain of 1. The output signal amplitudes are a maximum of 2.0 VPP. These outputs, above and below the signal ground voltage (VDD/2), can drive a load of a minimum of 1 kW with push-pull driving (a load connected between AOUT+ and AOUT–). The output amplitudes are 4 VPP maximum during push-pull driving. These outputs can be mute controlled externally. These outputs are operational during power saving and output the SG voltage (VDD/2) in the high impedance state. AUXO Auxiliary receive filter output. The output signal is inverted with respect to the VFO output with a gain of 1. The output signal swings above and below the SG voltage (VDD/2), and can drive a minimum load of 0.5 kW with respect to the SG voltage. The output can be mute controlled externally. During power saving and power down, AUXO outputs the SG voltage (VDD/2) in the high impedance state. BCLK Shift clock signal input for PCMIN and PCMOUT. The frequency is equal to the data rate. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power-saving state. 5/22 ¡ Semiconductor MSM7716 SYNC Synchronizing signal input. In the transmit section, the PCM output signal from the PCMOUT pin is output synchronously with this synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section. In the receive section, 14 bits required are selected from serial input of PCM signals on the PCMIN pin by the synchronizing signal. Signals in the receive section are synchronized by this synchronizing signal. This signal must be synchronized in phase with the BCLK. When this signal frequency is 8 kHz, the transmit and receive section have the frequency characteristics specified by ITU-T G. 714. The frequency characteristics for 8 kHz are specified in this data sheet. For different frequencies of the SYNC signal, the frequency values in this data sheet should be translated according to the following equation: Frequency values described in the data sheet ¥ the SYNC frequency values to be actually used 8 kHz Setting this signal to logic "1" or "0" drives the device to power-saving state. PCMIN PCM signal input. A serial PCM signal input to this pin is converted to an analog signal synchronously with the SYNC signal and BCLK signal. The data rate of the PCM signal is equal to the frequency of the BCLK signal. The PCM signal is shifted at a falling edge of the BCLK signal. The PCM signal is latched into the internal register when shifted by 14 bits. The top of the data (MSD) is identified at the rising edge of SYNC. The input signal should be input in the 14-bit 2's complement format. The MSD bit represents the polarity of the signal with respect to the signal ground. 6/22 ¡ Semiconductor MSM7716 PCMOUT PCM signal output. The PCM output signal is output from MSD in sequential order, synchronously with the rising edge of the BCLK signal. MSD may be output at the rising edge of the SYNC signal, depending on the timing between BCLK and SYNC. This pin is in high impedance state except during 14-bit PCM output. It is also high impedance during power saving or power down mode. A pull-up resistor must be connected to this pin, because its output is configured as an open drain. The output coding format is in 14-bit 2's complement. The MSD represents a polarity of the signal with respect to the signal ground. Table 1 Input/Output Level PCMIN/PCMOUT MSD +Full scale 0 1 1 1 1 1 1 1 1 1 1 1 1 1 +1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 –1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 –Full scale 1 0 0 0 0 0 0 0 0 0 0 0 0 0 PDN Power down control signal input. A digital "L" level drives both transmit and receive circuits to a power down state. The control registers are set to the initial state. SGC Connection of a bypass capacitor for generating the signal ground voltage level. Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and the SGC pin. 7/22 ¡ Semiconductor MSM7716 DEN, DCLK, CDIN Serial control ports for the microcontroller interface. Writing data to the 8-bit control register enables control of the receive output level and the signal path. DEN is the "Enable" signal pin, DCLK is the data shift clock input pin, and CDIN is the control data input pin. When powered down (PDN = 0), the initial values are set as shown in Tables 2, 3, and 4. The initial values are held unless the control data is written after power-down release. The control data is shifted at the rising edge of the DCLK signal and latched into the internal control register at the rising edge of the DEN signal. When the microcontroller interface is not used, these pins should be connected to DG. The bit map of the 8-bit control register is shown below. B7 B6 B5 B4 B3 B2 B1 B0 SW1 SW2 SW3 SW4 — VOL1 VOL2 VOL3 8/22 ¡ Semiconductor MSM7716 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit VDD AG = DG = 0 V –0.3 to +7.0 V Analog Input Voltage VAIN AG = DG = 0 V –0.3 to VDD + 0.3 V Digital Input Voltage VDIN AG = DG = 0 V –0.3 to VDD + 0.3 V Storage Temperature TSTG — –55 to +150 °C Power Supply Voltage RECOMMENDED OPERATING CONDITIONS Parameter Max. Unit Condition Power Supply Voltage VDD — 2.7 3.0 3.6 V Operating Temperature Ta — –30 +25 +85 °C — — 1.4 VPP — VDD V Analog Input Voltage VAIN High Level Input Voltage VIH Low Level Input Voltage VIL Clock Frequency FC Sync Pulse Frequency Gain = 1 SYNC, BCLK, PCMIN, PDN, DEN, DCLK, CDIN Min. Typ. Symbol 0.45 ¥ VDD 0.16 ¥ 0 — BCLK 14 ¥ Fs — 128 ¥ Fs kHz FS SYNC 4.0 8.0 16 kHz Clock Duty Ratio DC BCLK 40 50 60 % Digital Input Rise Time tIr SYNC, BCLK, PCMIN, PDN, — — 50 ns tIf DEN, DCLK, CDIN Digital Input Fall Time Sync Pulse Setting Time VDD V — — 50 ns tXS, tRS BCLKÆSYNC, See Fig.1 100 — — ns tSX, tSR SYNCÆBCLK, See Fig.1 100 — — ns High Level Sync Pulse Width *1 tWSH SYNC, See Fig.1 1 BCLK — — — Low Level Sync Pulse Width *1 tWSL SYNC, See Fig.1 1 BCLK — — — PCMIN Setup Time tDS Refer to Fig.1 100 — — ns PCMIN Hold Time tDH Refer to Fig.1 100 — — ns RDL Pull-up resistor 0.5 — — kW CDL — — — 100 pF Digital Output Load tWCL DCLK Low width, See Fig.2 50 — — tWCH DCLK High width, See Fig.2 50 — — tCDL DCLKÆDEN, See Fig.2 50 — — tDCL DENÆDCLK, See Fig.2 50 — — tCDH DCLKÆDEN, See Fig.2 50 — — tDCH DENÆDCLK, See Fig.2 50 — — CDIN Setup Time tCDS See Fig.2 50 — — CDIN Hold Time tCDH See Fig.2 50 — — Analog Input Allowable DC Offset Voff Transmit gain stage, Gain = 0 dB –100 — +100 mV Transmit gain stage, Gain = 20 dB –10 — +10 mV Allowable Jitter Width — SYNC, BCLK — — 1000 ns DCLK Pulse Width DEN Setting Time 1 DEN Setting Time 2 ns ns ns ns *1 For example, the minimum pulse width of SYNC is 488 ns when the frequency of BCLK is 2048 kHz. 9/22 ¡ Semiconductor MSM7716 RECOMMENDED OPERATING CONDITIONS (Continued) Parameter Symbol Condition tSD Digital Output Delay Time Min. Typ. Max. 20 — 100 tXD1 CL = 50 pF + 1 LSTTL 20 — 100 tXD2 Pull-up resistor = 500 W 20 — 100 20 — 100 tXD3 Unit ns ELECTRICAL CHARACTERISTICS DC and Digital Interface Characteristics Parameter Symbol IDD1 Power Supply Current IDD2 IDD3 High Level Input Voltage VIH Low Level Input Voltage VIL High Level Input Leakage Current IIH Low Level Input Leakage Current IIL Digital Output Low Voltage (Fs = 8 kHz, VDD = 2.7 V to 3.6 V, Ta = –30°C to +85°C) Condition Operating mode, VDD = 3.6 V No signal VDD = 3.0 V Power-saving mode, PDN = 1, SYNC, BCLK Æ OFF Power-down mode, PDN = 0 Min. Typ. Max. Unit — 10.0 17.0 mA — 8.0 13.0 mA — 6.0 11.0 mA — 0.01 0.05 mA — VDD V 0.45 ¥ SYNC, BCLK, PCMIN, DEN, CDIN, DCLK, PDN VDD 0.16 ¥ V 0.0 — — — — 2.0 mA — — — 0.5 mA VDD VOL PCMOUT pull-up resistor = 500 W 0.0 0.2 0.4 V Digital Output Leakage Current IO — — — 10 mA Input Capacitance CIN — — 5 — pF 10/22 ¡ Semiconductor MSM7716 Transmit Analog Interface Characteristics Parameter Symbol (Fs = 8 kHz, VDD = 2.7 V to 3.6 V, Ta = –30°C to +85°C) Condition Min. Typ. Max. Unit Input Resistance RINX MAIN, PBIN 10 — — MW Output Load Resistance RLGX MAO, PBO with respect to SG 20 — — kW Output Load Capacitance CLGX — — 30 pF Output Amplitude VOGX –0.7 — +0.7 V Offset Voltage VOSGX –20 — +20 mV Gain = 1 Receive Analog Interface Characteristics Parameter Output Resistance Output Load Resistance Symbol (Fs = 8 kHz, VDD = 2.7 V to 3.6 V, Ta = –30°C to +85°C) Min. Typ. Max. Unit ROAO AUXO, AOUT+, AOUT- — — 10 W ROVO VFO — — 100 W 0.5 — — kW RLAO Condition AUXO, AOUT+, AOUT– (each) with respect to SG RLVO VFO with respect to SG 20 — — kW Output Load Capacitance CLAO Output open — — 50 pF Output Amplitude VOAO –1.0 — +1.0 V Offset Voltage VOSA –100 — +100 mV AUXO, AOUT+, AOUT–, VFO with respect to SG AUXO, AOUT+, AOUT–, VFO with respect to SG 11/22 ¡ Semiconductor MSM7716 AC Characteristics Parameter Overall Frequency Response (Fs = 8 kHz, VDD = 2.7 V to 3.6 V, Ta = –30°C to +85°C) Loss 1 Freq. (Hz) 60 Loss 2 300 Loss 3 1020 Loss 4 2020 Loss 5 3000 Loss 6 3400 Symbol Level Condition (dBm0) Analog 0 to Analog Min. Typ. Max. 20 — — –0.2 — +0.4 Reference –0.2 — +0.4 –0.2 — +0.4 0 — 1.6 Loss T1 60 20 — — Loss T2 300 –0.15 — +0.2 Transmit Frequency Response Loss T3 1020 (Expected Value) Loss T4 2020 Loss T5 3000 Receive Frequency Response (Expected Value) Transmit Signal to Distortion Ratio (Expected Value) Receive Signal to Distortion Ratio (Expected Value) *1 –0.15 — +0.2 –0.15 — +0.2 Loss T6 3400 0 — 0.8 Loss R1 300 –0.15 — +0.2 Loss R2 1020 Loss R3 2020 Loss R4 Loss R5 0 — +0.2 3000 –0.15 — +0.2 3400 0.0 — 0.8 SD 1 3 Analog 55.9 — — SD 2 0 to 55.9 — — –10 Analog 55.9 — — *1 45.9 — — SD 4 1020 –20 SD 5 –30 35.9 — — SD 6 –40 25.9 — — SD 7 –50 15.9 — — SD T1 3 58 — — SD T2 0 58 — — –10 58 — — –20 48 — — SD T3 SD T4 1020 *1 SD T5 –30 38 — — SD T6 –40 28 — — SD T7 –50 18 — — SD R1 3 58 — — SD R2 0 58 — — SD R3 –10 58 — — 48 — — SD R4 1020 dB dB Reference –0.15 SD 3 Overall Signal to Distortion Ratio Reference 0 Unit –20 *1 SD R5 –30 38 — — SD R6 –40 28 — — SD R7 –50 18 — — dB dB dB dB Psophometric filter is used. 12/22 ¡ Semiconductor MSM7716 AC Characteristics (Continued) Parameter Symbol (Fs = 8 kHz, VDD = 2.7 V to 3.6 V, Ta = –30°C to +85°C) Freq. (Hz) GT 1 GT 2 Overall Gain Tracking Transmit Gain Tracking (Expected Value) Receive Gain Tracking (Expected Value) GT 3 1020 Level Condition (dBm0) 3 Analog –10 to –40 Analog Min. Typ. Max. –0.4 +0.01 +0.4 Reference –0.3 0.00 +0.8 –1.3 –0.03 +1.3 GT 4 –50 GT 5 –55 –1.6 –0.15 +1.6 GT T1 3 –0.3 +0.01 +0.3 GT T2 GT T3 –40 –0.3 0.00 +0.3 GT T4 –50 –0.6 –0.03 +0.6 GT T5 –55 –1.2 +0.15 +1.2 GT R1 3 –0.3 –0.06 +0.3 GT R2 –10 GT R3 1020 dB Reference –10 1020 Unit dB Reference –40 –0.3 –0.02 +0.3 GT R4 –50 –0.6 –0.02 +0.6 GT R5 –55 –1.2 –0.27 +1.2 dB 13/22 ¡ Semiconductor MSM7716 AC Characteristics (Continued) Parameter Overall Idle Channel Noise Transmit Idle Channel Noise (Expected Value) Receive Idle Channel Noise (Expected Value) (Fs = 8 kHz, VDD = 2.7 V to 3.6 V, Ta = –30°C to +85°C) Symbol Freq. (Hz) Nidle A — Nidle T — Nidle R — Level Condition (dBm0) AIN: no signal — *1 — *1 — VDD = 3.0 V AV T Absolute Level (Initial Level) AIN: no signal 1020 0 (Deviation of Temperature and Power) *2 VDD = +2.7 AV Tt to 3.6 V Ta = –30 AV Rt Typ. Max. Unit — –70 –66 dBmOp — –76 –74 dBmOp — –76 –74 0.338 0.350 0.362 0.483 0.500 0.518 –0.2 — +0.2 dB –0.2 — +0.2 dB — — 0.6 ms — — 0.325 — — 0.175 Vrms Ta = 25°C AV R Absolute Level Min. to 85°C A to A Absolute Delay tD 1020 0 BCLK = 64 kHz tGD T1 Transmit Group Delay tGD T3 Receive Group Delay Crosstalk Attenuation *1 *2 *3 500 tGD T2 600 to 2600 CR T CR R *3 2800 tGD R1 500 to 2600 tGD R2 0 2800 1020 0 0 — — 0.325 — 0.00 0.125 — 0.12 0.325 TRANS Æ RECV 75 85 — RECV Æ TRANS 70 80 — *3 ms ms dB Psophometric filter is used. AVT is defined at MAO and PBO-PCMOUT. AVR is defined at PCMIN-VFO. VOL = 0 dB Minimum value of the group delay distortion 14/22 ¡ Semiconductor MSM7716 AC Characteristics (Continued) Parameter Discrimination Out-of-band Spurious Intermodulation Distortion Power Supply Noise Rejection Ratio Auxiliary Output Gain (Fs = 8 kHz, VDD = 2.7 V to 3.6 V, Ta = –30°C to +85°C) Freq. Level Condition (Hz) (dBm0) 0 to 4.6 kHz to 0 DIS 4000 Hz 72 kHz Symbol S IMD 300 to 3400 fa = 470 fb = 320 PSR T 0 to PSR R 50 kHz GAUX 1020 0 Max. Unit 30 32 — dB — –37.5 –35 dBm0 2fa – fb — –52 –40 dBm0 50 mVPP *1 — 30 — dB 0 VFO to AUXO –1.0 0 +1.0 dB Set at – 4 dB –5 –4 –3 GV3 –8 dB –9 –8 –7 GV4 –12 dB –13 –12 –11 –16 dB –17 –16 –15 –20 dB –21 –20 –19 –24 dB –25 –24 –23 –28 dB –29 –28 –27 GV5 GV6 GV7 GV8 *1 100 kHz Typ. –4 GV2 VOL Gain Setting Value 4.6 kHz to Min. 1020 0 Referenced to 0 dB setting dB Measured inband. 15/22 , , , , ¡ Semiconductor MSM7716 TIMING DIAGRAM PCM Data Output Timing Transmit Timing BCLK 1 tXS 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 16 17 tSX tWSL tWSH SYNC tSD tXD1 MSD D2 PCMOUT D3 tXD2 D5 D4 D6 D7 D8 D9 tXD3 D10 D11 D12 D13 D14 When tXS £ 1/2 • Fc, the Delay of the MSD bit is defined as tXD1. When tSX < 1/2 • Fc, the Delay of the MSD bit is defined as tSD. Receive Timing BCLK 1 tRS 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tSR tWSL SYNC PCMIN tWSH MSD D2 D3 tDS D4 D5 tDH D6 D7 D8 D9 D10 D11 D12 D13 D14 Figure 1 Basic Timing Diagram MCU Interface Timing DCLK 1 tCDL DEN 2 tDCL 3 4 5 6 tWCL tWCH B7 B6 B5 B4 8 B3 9 10 11 12 13 tDCH tCDH tCDS CDIN 7 tCDH B2 B1 B0 Figure 2 MCU Interface Timing Diagram 16/22 ¡ Semiconductor MSM7716 FUNCTIONAL DESCRIPTION Control Data Description SW1, SW2 - - Control bits for the transmit speech path switch. The AD converter input is selected according to the bit data shown in Table 2. Table 2 State SW2 SW1 AD Converter Input Remarks T1 0 0 No signal (muting state) — T2 0 1 Input signal to MAIN At initial setting T3 1 0 Input signal to PBIN — T4 1 1 Addition signal of both MAIN and PBIN The gain of each input drops about 6 dB SW3, SW4 - - Control bits for the receive speech path switch. The control should be performed according to Table 3. Table 3 State SW4 SW3 AOUT+, AOUT– Output AUXO Output Remarks R1 0 0 SG SG — R2 0 1 PWI SG At initial setting R3 1 0 SG DA — R4 1 1 PWI DA — DA: DA converter output. SG: signal ground voltage. VOL1, VOL2, VOL3 - - - Control bits for the receive signal output level. By controlling these bits, the output levels of VFO and AUXO can be controlled according to Table 4. Table 4 VOL1 VOL2 VOL3 Receive Signal Gain Remarks 0 0 0 0 dB At initial setting 0 0 1 –4 dB — 0 1 0 –8 dB — 0 1 1 –12 dB — 1 0 0 –16 dB — 1 0 1 –20 dB — 1 1 0 –24 dB — 1 1 1 –28 dB — 17/22 ¡ Semiconductor MSM7716 APPLICATION CIRCUIT 1 kW +3 V MSM7716 Microphone analog input Handset analog input Addition signal input 1 mF 1 mF 1 mF 20 kW 20 kW 20 kW 20 kW 20 kW 20 kW PCMOUT MAO PCMIN PBIN BCLK PCM shift clock input PBO SYNC 8 kHz SYNC pulse input PWI AOUT– Analog inverted output* AOUT+ AUXO Auxiliary output* 0.1 mF SGC AG 0V PCM input VFO Analog output* +3 V PCM output MAIN 20 kW PDN Power down control input "1" = Operation "0" = Power down DCLK DEN Controller CDIN DG 10 mF 0 to 10 W + 1 mF VDD * The swing of the analog output signal is a maximum of ±1.0 V above and below the VDD/2 offset level. 18/22 ¡ Semiconductor MSM7716 APPLICATION INFORMATION Digital pattern for 0 dBm0 The digital pattern for 0 dBm0 is shown below. (SYNC frequency = 8 kHz, signal frequency = 1 kHz) S2 S3 S1 S4 SG S5 S8 S6 Sample No. MSD D2 D3 D4 D5 S7 D6 D7 S1 0 0 1 0 0 0 1 D8 D9 D10 D11 D12 D13 D14 0 1 0 1 0 1 1 S2 0 1 0 1 0 0 1 1 1 0 1 1 1 0 S3 0 1 0 1 0 0 1 1 1 0 1 1 1 0 S4 0 0 1 0 0 0 1 0 1 0 1 0 1 1 S5 1 1 0 1 1 1 0 1 0 1 0 1 0 0 S6 1 0 1 0 1 1 0 0 0 1 0 0 0 1 S7 1 0 1 0 1 1 0 0 0 1 0 0 0 1 S8 1 1 0 1 1 1 0 1 0 1 0 1 0 0 19/22 ¡ Semiconductor MSM7716 NOTES ON USE • To ensure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins. • Connect the AG pin and the DG pin as close as possible. Connect to the system ground with low impedance. • Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If the use of IC socket is unavoidable, use the short lead type socket. • When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave sources such as power supply transformers surround the device. • Keep the voltage on the VDD pin not lower than –0.3 V even instantaneously to avoid latchup that may otherwise occur when power is turned on. • Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of these devices. 20/22 ¡ Semiconductor MSM7716 PACKAGE DIMENSIONS (Unit : mm) TSOPI32-P-814-0.50-1K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.27 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 21/22 ¡ Semiconductor MSM7716 (Unit : mm) SSOP30-P-56-0.65-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.19 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 22/22