OKI MSM7718-01TS-K

E2U0052-18-86
¡ Semiconductor
MSM7718-01
¡ Semiconductor
This version:MSM7718-01
Aug. 1998
Echo Canceler with ADPCM CODEC
GENERAL DESCRIPTION
The MSM7718, developed for PHS (Personal Handyphone System) applications, is a CMOS LSI
device and contains a line echo canceler and a single channel full-duplex ADPCM transcoder
that performs interconversion between voice-band analog signal and 32 kbps ADPCM data.
This device includes DTMF tone and several types of tone generation, transmit/receive data mute
and gain control, and VOX function and is best suited for master telephones in PHS applications.
FEATURES
• Single 3 V power supply
VDD : 2.7 V to 3.6 V
• ADPCM :
ITU-T Recommendations G.726 (32 kbps)
• Full-Duplex single channel operation
• Transmit/receive synchronous mode
• PCM interface coding format :
µ-law
• Built-in line echo canceler
Echo attenuation : 30 dB (typ.)
Cancelable echo delay time :
Normal speech mode :
23 ms (max.)
Line echo canceler expansion mode : 54 ms (max.)
• Serial PCM/ADPCM transmission data rate : 64 kbps to 2048 kbps
• Low power consumption
Operating mode :
Typically 66 mW (VDD = 3.0 V)
Power-down mode :
Typically 0.3 mW (VDD = 3.0 V)
• Two analog input gain adjustable amplifier stages
• Analog output stage :
Push-pull drive, (direct drive of 350 W + 120 nF)
• Master clock frequency :
9.600/19.200 MHz
• Transmit/receive mute, transmit/receive programmable gain control
• Built-in DTMF tone generator and various ringing tones generator
• DTMF tone and call progress tone detection
• Serial MCU interface control
• Built-in VOX control
Transmit side :
Voice/silence detect
Receive side :
Background noise generation at the absence of voice signal
• Built-in 2100 Hz tone detection (bidirectional)
• Package:
100-pin plastic TQFP (TQFP100-1414-0.50-K) (Product name : MSM7718-01TS-K)
1/38
MSM7718-01
¡ Semiconductor
BLOCK DIAGRAM
Tone Generator (DTMF etc.)
ATTtgrx
ATTtgtx
Tone Detector (DTMF etc.)
ATTsL
ATTtx
Center
Clip
+
–
SinL
SoutL
Line
Adapive FIR Filter
(LAFF)
Coeff.L0
Power Calc.
Coeff.L1
Howling Detector
Double Talk Detector
ATTrx
RinL
RoutL
GainL ATTrL
Line Echo Canceler
L/m
Power
Detect
2100 Hz Detect
Noise
Gen.
m/L
Voice Detect
m/L
L/m
PCM CODEC
SGR
SGT
VREF
L/m
–
+
BPF
–
+
ADC
GSX2
RC LPF
VFRO
PWI
RC LPF
–
+
ADPCM TRANSCODER
DAC
LPF
–1
m/L
P/S&S/P
Timing
Gen.
SYNCP
BCLKP
MCU Interface
PCMPCI
PCMPCO
PCMLNI
PCMLNO
PCMACI
PCMACO
PCMADI
PCMADO
1.2 kW
VDDD1,2,3
VDDA
DG1,2,3
AG
DEN
EXCK
DIN
DOUT
INT
AOUT+
ADPCM
CODER
P/S
ADPCM
DECODER
S/P
Clock Gen.
Test Interface
MLV0
MLV1
MLV2
MUTE
D7-0
A20-0
WE
OE
CS1
CS2
RP
IS
BCLKA
SYNCA
IR
TSTO
AOUT–
1.2 kW
Flash
Memory
Controller
(Reserved)
TSTI1-4
AIN1–
AIN1+
GSX1
AIN2
VOXI
Mute
MCKSL
MCK
PDN/RST
PDWN
VOXO
2/38
77 CS1
78 OE
79 WE
80 RP
81 PDWN
82 VDDD3
83 TSTI1
84 BCLKA
85 SYNCA
86 IR
87 BCLKP
88 NC
89 PCMPCI
90 PCMLNI
91 PCMACI
92 PCMADI
93 DOUT
94 IS
95 PCMPCO
96 PCMLNO
97 DG3
98 PCMACO
99 PCMADO
100 NC
76 NC
MSM7718-01
¡ Semiconductor
NC
1
75 NC
TSTI2
2
74 CS2
PDN/RST
3
73 INT
DIN
4
72 TSTO
EXCK
5
71 VOXO
DEN
6
70 VOXI
VDDD1
7
69 MLV0
SYNCP
8
68 MLV1
TSTI4
9
67 MLV2
TSTI3 10
66 MUTE
65 DG2
MCK 11
MCKSL 12
64 D7
GNDA 13
63 NC
VFRO 14
62 D6
PWI 15
61 D5
AOUT– 16
60 D4
AOUT+ 17
59 D3
SGT 18
58 D2
SGR 19
57 D1
NC 20
56 D0
NC 21
55 A0
AIN1– 22
54 A1
GSX1 23
53 A2
AIN1+ 24
52 VDDD2
51 NC
NC 50
A3 49
A4 48
A5 47
A6 46
A7 45
A8 44
A9 43
A10 42
A11 41
A12 40
A13 39
A14 38
NC 37
A15 36
A16 35
A17 34
A18 33
A19 32
A20 31
DG1 30
VDDA 29
AIN2 28
26
NC
GSX2 27
NC 25
NC: No-connect pin
100-Pin Plastic TQFP
3/38
MSM7718-01
¡ Semiconductor
PIN FUNCTIONAL DESCRIPTION
AIN1+, AIN1–, AIN2, GSX1, GSX2
Transmit analog inputs and the outputs for transmit gain adjustment.
AIN1– (AIN2) connects to inverting input of the internal transmit amplifier. AIN1+ connects to noninverting input of the internal transmit amplifier. GSX1 (GSX2) connects to the internal transmit
amplifier output. Refer to Fig.1 for gain adjustment.
VFRO, AOUT+, AOUT–, PWI
Receive analog outputs and the output for receive gain adjustment.
VFRO is the receive filter output. AOUT+ and AOUT– are differential analog signal outputs which
can directly drive ZL (= 350 W + 120 nF) or a 1.2 kW load. Refer to Fig.1 for gain adjustment.
However, these outputs are in high impedance state during power-down.
AIN1–
Differential
Analog Input V1
C1
R1
R2
–
VREF
+
AIN1+
C1
R1
R2
GSX1
SGT
AIN2
+
–
C2
R3
–
to ENCODER
+
R4
GSX2
Transmit Gain: V GSX2 /Vi
= (R2/R1) ¥ (R4/R3)
VFRO
from DECODER
Receive Gain: V O /V VFRO
= 2 ¥ (R5/R6)
R6
PWI
R5
AOUT–
Z L =120 nF + 350 W
VO
Differential
Analog
Output
–
+
AOUT+
–1
Figure 1 Analog Interface
4/38
¡ Semiconductor
MSM7718-01
SGT, SGR
Outputs of the analog signal ground voltage.
SGT outputs the analog signal ground voltage of the transmit system, and SGR outputs the analog
signal ground voltage for the receive system. The output voltage is approximately 1.4 V. Connect
bypass capacitors of 10 mF and 0.1 mF (ceramic type) between these pins and the AG pin. However
to reduce the response time of the receiver power-on, it is recommended to apply bypass capacitors
of 1 mF and 0.1 mF. During power-down, the output changes to 0 V.
AG
Analog ground.
DG1, 2, 3
Digital ground.
VDDA
+3 V power supply for analog circuits.
VDDD1, 2, 3
+3 V power supply for digital circuits.
PDN/RST
Power-down reset control input.
A logic “0” makes the LSI device enter a power-down state. At the same time, all control register
data is reset to the initial state. Set this pin to a logic “1” during normal operating mode. Since the PDN/
RST pin is ORed with CR0-B5 of the control register, set CR0-B5 to digital “0” when using this pin.
PDWN
Power-down control input.
When set to a logic “0”, the device changes to the power-down state, but each bit of control register
and internal variables of control register are retained. During normal operation, set this pin to logic
“1”. Since the PDWN pin is ORed with CR0-B6 of the control register, set CR0-B6 to logic “0” when
using this pin.
MCK
Master clock input.
The frequency must be 9.6 MHz or 19.2 MHz. The master clock signal is allowed to be asynchronous
with SYNCP, SYNCA, BCLKP, and BCLKA.
5/38
¡ Semiconductor
MSM7718-01
MCKSL
Master clock selection input.
Set MCKSL to logic “0” when the master clock frequency is 9.6 MHz, and to logic “1” when it is 19.2
MHz.
PCMPCO
PCM data output of the PCM CODEC.
PCM is output from MSB, synchronizing with the rising edge of BCLKP and SYNCP. This pin is in
a high impedance state except during 8-bit PCM output. (It is also in a high impedance state during
power-down mode.) A pull-up resistor must be connected to this pin because its output is configured
as an open drain.
PCMPCI
PCM data input of the PCM CODEC.
PCM is shifted in at the falling edge of the BCLKP signal. The start of the PCM data (MSB) is
identified at the rising edge of SYNCP.
PCMADO
PCM data output of the ADPCM transcoder.
PCM is the output data after ADPCM decoder processing and is serially output from MSB in
synchronization with the rising edge of BCLKP and SYNCP. However, this signal timing can be
controlled at PCM multiplexing by the control register CR1-B5.
(The time slot 1 or 2 can be selected. Refer to Figs. 2-4.)
This pin is in a high impedance state except during 8-bit PCM output. (It is also in an high impedance
state during power-down mode.) A pull-up resistor must be connected to this pin because its output
is configured as an open drain.
PCMADI
PCM data input of the ADPCM transcoder.
PCM is shifted in at a falling edge of the BCLKP signal and input from MSB. The start of the PCM
data (MSB) is identified at the rising edge of SYNCP. However, this signal timing can be controlled at PCM
multiplexing by the control register CR1-B5.
(The time slot 1 or 2 can be selected. Refer to Figs. 2-4.)
PCMLNO
PCM receive data output of the line echo canceler.
PCM is output from MSB in a sequential order, synchronizing with the rising edge of BCLKP and
SYNCP. However, this signal timing can be controlled at PCM multiplexing by the control
register CR2-B3 to B5.
(The time slot of 1 to 7 can be selected. Refer to Figs. 2-4.)
This pin is in a high impedance state except during 8-bit PCM output. (It is also in a high impedance
state during power-down mode.) A pull-up resistor must be connected to this pin because its output
is configured as an open drain.
6/38
MSM7718-01
¡ Semiconductor
PCMLNI
PCM transmit data input of the line echo canceler.
PCM is shifted in at a falling edge of the BCLKP signal and input from MSB. The start of the PCM
data (MSB) is identified at the rising edge of SYNCP. However, this signal timing can be controlled
at PCM mutiplexing by the control register CR2-B3 to B5.
(One of the time slots 1 to 7 can be selected. Refer to Figs. 2-4.)
PCMACO
PCM transmit data output of the line echo canceler.
PCM is output from MSB in a sequential order, synchronizing with the rising edge of BCLKP and
SYNCP. However, this signal timing can be controlled at PCM multiplexing by the control
register CR2-B0 to B2. (The time slot 1 to 7 can be selected. Refer to Figs. 2 - 4.)
This pin is in a high impedance state except during 8-bit PCM output.
(It is also in a high impedance sate during power down mode.) A pull-up resistor must be connected
to this pin because its output is configured as an open drain.
PCMACI
PCM receive data input of the line echo canceler.
PCM is shifted in at a falling edge of BCLKP and input from MSB.
The start of the PCM data (MSB) is identified at the rising edge of SYNCP. However, this signal
timing can be controlled at PCM multiplexing by the control register CR2-B0 to B2. (One of the time
slots 1 to 7 can be selected. Refer to Figs. 2-4.)
BCLKP
SYNCP
PCM
Multiple
time slot 1
time slot 2
time slot 3
time slot 7
Note : The PCM signals (PCMPCI and PCMPCO) of the PCM CODEC are always assigned to time
slot 1.
The PCM signals (PCMADI and PCMADO) of the ADPCM transcoder can be assigned to
time slot 1 or 2.
The PCM signals (PCMLNI, PCMLNO, PCMACI, PCMACO) of the line echo canceler can
be assigned to one of the time slots 1 to 7. (Multiple timing is controlled by CR1 and CR2.)
Figure 2 PCM Multiple Timing
7/38
MSM7718-01
¡ Semiconductor
MSM7718
Line Echo
Canceler
Line
PCM
CODEC
ADPCM
Transcoder
Slave telephone
PCMADO
PCMADI
PCMACO
PCMACI
PCMLNO
PCMLNI
PCMPCO
PCMPCI
Note : In this connection, PCMLNI, PCMLNO, PCMACI, and PCMACO should all be assigned
to time slot 1 for their output timing (the output timing for the PCM CODEC is always
assigned to time slot 1).
Turn on the line echo canceler and establish a route between the slave telephone and the
line.
Figure 3 PCM Signal Connection Example 1
8/38
MSM7718-01
¡ Semiconductor
MSM7718
Line Echo
Canceler
Line
PCM
CODEC
ADPCM
CODEC
PCMADO
PCMADI
PCMACO
PCMACI
PCMLNO
PCMLNI
PCMPCO
PCMPCI
Microphone
and speaker
of the master
telephone
Slave telephone
PCM
CODEC
Notes : The PCM signals of the ADPCM transcoder are assigned to time slot 2. (The PCM signals
of the PCM CODEC are always assigned to time slot 1.) The PCM signals of an external
PCM CODEC are assigned to time slot 3.
Route between the line and the slave telephone
PCMLNI and PCMLNO are assigned to time slot 1 and PCMACI and PCMACO are
assigned to time slot 2.
Turn on the line echo canceler, and establish the route between the line and the slave
telephone.
Route between the master telephone's microphone/speaker (handsfree) and the slave
telephone
PCMLNI and PCMLNO are assigned to time slot 3 and PCMACI and PCMACO are
assigned to time slot 2.
Turn on the line echo canceler, and establish the route between the microphone/
speaker of the master telephone and the slave telephone.
Route between the line and the master telephone's microphone/speaker (handsfree)
PCMLNI and PCMLNO are assigned to time slot 1 and PCMACI and PCMACO are
assigned to time slot 3.
Put the line echo canceler into “through mode”, and establish the route between
the line and the microphone/speaker of the master telephone.
Various routing can be implemented providing extension of external PCM CODECs.
Figure 4 PCM Signal Connection Example 2
9/38
¡ Semiconductor
MSM7718-01
BCLKP
Shift clock input for the PCM data (PCMPCO, PCMPCI, PCMADO, PCMADI, PCMLNO, PCMLNI,
PCMACO, PCMACI). The frequency is set in the range of 64 kHz to 2048 kHz.
This signal must be synchronized with the SYNCP signal. (Refer to Fig. 2.)
SYNCP
8 kHz synchronous signal input for transmit and receive PCM data.
This signal must be synchronized with the BCLKP signal. (Refer to Fig. 2.)
IS
Transmit ADPCM data output.
This data is the output data after ADPCM encoding, and is serially output from MSB in synchronization with the rising edge of BCLKA and SYNCA. This pin is an open drain output which remains
in a high impedance state during power-down, and requires a pull-up resistor.
IR
Receive ADPCM data input.
ADPCM is shifted in on the rising edge of BCLKA in synchronization with SYNCA and input
orderly from MSB.
BCLKA
Shift clock input for the ADPCM data (IS, IR).
The frequency is from 64 kHz to 2048 kHz.
This signal must be synchronized with the SYNCA signal.
SYNCA
8 kHz synchronous signal input for transmit and receive ADPCM data.
Synchronize this data with BCLKA signal. SYNCA is used for indicating the MSB of the serial
ADPCM data stream.
DEN, EXCK, DIN, DOUT, INT
Serial control ports for MCU interface.
Reading and writing data is performed by an external MCU through these pins. 17-byte control
registers are provided in this device.
DEN is the “Enable” control signal input, EXCK is the data shift clock input, DIN is the address and
data input, and DOUT is the data output.
Input/output timing is shown in Fig. 5.
INT goes to logic “0” when any change has been found in the tone detection results in the tone
detection mode (change in the control register bits CR7-B3, B2), and goes to logic “1” when the data
of control register CR7 is read out.
10/38
,
,,,
MSM7718-01
¡ Semiconductor
DEN
EXCK
DIN
W
A4
A3
A2
A1
DOUT
A0
B7
B6
B5
B4
B3
B2
B1
B0
B4
B3
B2
B1
B0
High Impedance
(a) Data Write Timing
DEN
EXCK
DIN
DOUT
R
A4
A3
High Impedance
A2
A1
A0
B7
B6
B5
(b) Data Read Timing
Figure 5 MCU Interface Input/Output Timing
VOXO
Signal output for transmit VOX function.
The VOX function recognizes the presence or absence of the transmit voice signal by detecting the
level of the transmit signal to the line echo canceler . “1” and “0” levels set to this pin correspond
to the presence and the absence of voice, respectively. This result appears also at the register data
CR7-B7. The signal energy detect threshold is set by the control register data CR6-B6, B5.
The timiging diagram of the VOX function is shown in Fig 6.
The transmit signal to the line echo canceler refers to the signal input to the PCMLNI pin.
VOXI
Signal input for receive VOX function.
The “1” level at VOXI indicates the presence of a voice signal, the decoder block processes normal
receive signal, and the voice signal on the PCMACI pin goes through. The “0” level indicates the
absence of a voice signal and the background noise generated in this device is output to the line echo
canceler.
The background noise amplitude is set by the control register CR6.
Because this signal is ORed with the register data CR6-B3, set the control register data CR6-B3 to logic
“0”.
11/38
MSM7718-01
¡ Semiconductor
Voice Input
GSX2
Silence
VOXO
Voice
Voice
TVXOFF
Silence
Detect (Hangover time)
TVXON
Voice
Detect
(a) Transmit VOX Function Timing Diagram (for Analog Input)
Silence
VOXI
Voice
Voice
Voice Output
VFRO
Normal Voice Signal
Decoded Time Period
Background
Noise
(b) Receive VOX Function (CR6-B3: logic “0”) Timing Diagram (for Analog Input)
Note: The VOX function is valid when CR6-B7 is set to logic “1”.
Figure 6 VOX Function
MUTE
This pin is used to enable the receive side voice path mute level.
To set the mute level, set this pin to “1”.
MLV0, MLV1, MLV2
These pins are used to set the receive side voice path mute level.
For the control method, refer to the control register description (CR1). Since these pins are ORed
with CR1-B2, B1, and B0 internally, set the bits of the register to “0“ before using this pin.
12/38
¡ Semiconductor
MSM7718-01
D7 to D0 (reserved for external memory I/F)
Output of write data, and input-output of read data.
A20 to A0 (reserved for external memory I/F)
External memory address output.
WE (reserved for external memory I/F)
Output for write control .
OE (reserved for external memory I/F)
Output for read control.
CS1, CS2 (reserved for external memory I/F)
Chip select output.
RP (reserved for external memory I/F)
Reset/power-down control output for external memory.
TSTI1, TSTI2, TSTI3, TSTI4
Input for test.
Normally fix these pins to logic “0”.
TSTI4
Input for mode select.
Fix this pin to logic “0” for normal speech mode.
Fix this pin to logic “1” for line echo canceler expansion mode. Refer to the explanation of CR0
for the operation mode.
TSTO
Output for test.
13/38
MSM7718-01
¡ Semiconductor
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
Rating
Unit
Power Supply Voltage
VDD
Analog Input Voltage
VAIN
—
–0.3 to +5
V
—
– 0.3 to VDD + 0.3
V
Digital Input Voltage
Storage Temperature
VDIN
—
–0.3 to VDD + 0.3
V
TSTG
—
–55 to +150
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
(VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C)
Max.
Min.
Typ.
Unit
Symbol
Condition
VDD
—
Operating Temperature
Ta
—
Input High Voltage
VIH
All digital inputs
Input Low Voltage
VIL
All digital inputs
0
—
Digital Input Rise Time
tIr
All digital inputs
—
—
50
tIf
All digital inputs
—
—
50
Power Supply Voltage
Digital Input Fall Time
Master Clock Frequency
fMCK
MCK
DC
2.7
–25
0.45
¥ VDD
—
3.6
V
+25
+70
°C
—
—
V
0.16
¥ VDD
–100ppm 19.2/9.6 +100ppm
V
ns
ns
MHz
MCK
40
50
60
%
Bit Clock Frequency
fBCK
BCLKP, BCLKA
64
—
2048
kHz
Synchronous Pulse Frequency
fSYNC
SYNCP, SYNCA
–1000ppm
8.0
+1000ppm
kHz
Clock Duty Cycle
DCK
40
50
60
%
100
—
—
ns
100
—
—
ns
—
—
100
ns
100
—
—
ns
100
—
—
ns
—
—
100
ns
1 BCLK
—
100
ms
100
—
—
ns
—
—
ns
Master Clock Duty Ratio
tXS
Transmit Sync Pulse Setting Time
tSX
tXO
tRS
Receive Sync Pulse Setting Time
tSR
BCLKP, BCLKA, EXCK
BCLKP to SYNCP,
BCLKA to SYNCA
SYNCP to BCLKP,
SYNCA to BCLKA
SYNCP to BCLKP, SYNCA to BCLKA
BCLKP to SYNCP,
BCLKA to SYNCA
SYNCP to BCLKP,
SYNCA to BCLKA
tRO
SYNCP to BCLKP, SYNCA to BCLKA
Receive Sync Pulse Setting Time
tWS
SYNCP, SYNCA
PCM, ADPCM Setup Time
tDS
—
PCM, ADPCM Hold Time
tDH
—
100
Note: If SYNCP and SYNCA are generated from different clocks, do not change the relative
timing of the rising edge of SYNCP and that of SYNCA (that is, which rising edge is
earlier) after the reset state has been released.
14/38
MSM7718-01
¡ Semiconductor
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD= 2.7 to 3.6 V, Ta= –25 to +70°C)
Parameter
Power Supply Current 1
Power Supply Current 2
Input Leakage current
Symbol
IDD1
IDD2
Condition
Operating mode, no signal
(only the master clock is input)
Power down mode
(only the master clock is input)
Min.
Typ.
Max.
Unit
—
22
40
mA
—
0.2
1
mA
IIH
VI=VDD
—
—
2
mA
IIL
VI = 0 V
—
—
0.5
mA
High Level Digital
VOH1
IOH= 0.4 mA
0.5¥VDD
—
VDD
V
Output Voltage
VOH2
IOH= 1 mA
0.8¥VDD
—
VDD
V
VOL
1LSTTL, pull-up resistance : 500 W
0
0.2
0.4
V
IS
—
—
10
mA
—
5
—
pF
Low Level Digital
Output Voltage
Digital Output
Leakage Current
Input Capacitance
IO
CIN
—
Analog Interface Characteristics
(VDD= 2.7 to 3.6 V, Ta= –25 to +70°C)
Parameter
Input Resistance
Output Load Resistance
Output Load Capacitance
Symbol
Min.
Typ
Max.
Unit
10
—
—
MW
GSX1, GSX2, VFRO
20
—
—
kW
AOUT+
1.2
—
—
kW
RL3
AOUT–
1.2
—
—
kW
CL1
GSX1, GSX2, VFRO
—
—
100
pF
CL2
AOUT+
—
—
100
pF
CL3
AOUT–
—
—
100
pF
—
—
1.3
VPP
—
—
1.3
VPP
AIN+, AIN–, AIN2, PWI
RL1
RL2
VO1
Output Voltage Level (*1)
Offset Voltage
Condition
RIN
GSX1, GSX2, VFRO
(RL=20kW)
VO2
AOUT+ (RL=1.2 kW)
VO3
AOUT– (RL=1.2 kW)
—
—
1.3
VPP
VOFGX
VFRO
–100
—
+100
mV
VOFGX
VFRO
–20
—
+20
mV
SGT, SGR Output Voltage
VSG
SGT, SGR
—
1.4
—
V
SGT Output Impedance
RSGT
SGT
—
40
80
kW
SGR Output Impedance
RSGR
SGR
—
4
8
kW
*1 –7.7 dBm (600 W) = 0 dBm0, +3.14 dBm0=1.30 VPP
15/38
MSM7718-01
¡ Semiconductor
Digital Interface Characteristics
(VDD= 2.7 to 3.6 V, Ta= –25 to +70°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Digital Output Delay Time
tSDX, tSDR
0
—
200 (100)
ns
PCM, ADPCM Interface
tXD1, tRD1
0
—
200 (100)
ns
0
—
200 (100)
ns
0
—
200 (100)
ns
1LSTTL+100 pF
pull-up resistance : 500 W
Values in parentheses apply when
tXD2, tRD2 Cload = 10 pF,
tXD3, tRD3 pull-up resistance :£2 kW
Serial Port
tM1
50
—
—
ns
Digital Input/Output
tM2
20
—
—
ns
Setting Time
tM3
20
—
—
ns
tM4
50
—
—
ns
tM5
100
—
—
ns
tM6
50
—
—
ns
tM7
50
—
—
ns
tM8
0
—
—
ns
tM9
50
—
—
ns
tM10
50
—
—
ns
tM11
0
tM12
100
—
—
—
—
—
—
10
ns
ns
MHz
7
8
9
10
fECK
Shift Clock Frequency
Cload=100 pF
EXCK
PCM/ADPCM Output Timing
BCLKP
0
tXS
SYNCP
tXO
PCMPCO
PCMADO
PCMLNO
PCMACO
1
tSX
2
tWS
tXD1
tXD2
3
4
5
6
tXD3
LSB
MSB
tSDX
Note : The timing for PCMADO, PCMLNO, and PCMACO shown above reperesents the timing
when time slot 1 is selected.
BCLKA
0
tXS
SYNCA
tXO
IS
1
tSX
2
tXD1
tXD2
MSB
3
4
5
6
7
8
9
10
tXD3
LSB
tSDX
16/38
MSM7718-01
¡ Semiconductor
PCM/ADPCM Input Timing
0
tRS
BCLKA
1
tSR
SYNCA
2
tRO
IR
3
4
0
1
tSR
tRS
SYNCP
7
8
9
10
5
6
7
8
9
10
LSB
2
tRO
PCMPCI
PCMADI
PCMLNI
PCMACI
6
tDS tDH
MSB
BCLKP
5
tWS
3
4
tDS tDH
MSB
LSB
Note : The timing for PCMADI, PCMLNI, and PCMACI shown above represents the timing when
time slot 1 is selected.
Serial Port Timing for Microcontroller Interface
DEN
tM5
tM2
1
EXCK
tM1
DIN
2
3
tM3
W/R
tM4
A4
5
6
tM6
7
13
14
tM9
tM7
A1
A0
15
B7
B1
B0
tM11
tM8
DOUT
tM12
tM10
B7
B1
B0
17/38
MSM7718-01
¡ Semiconductor
AC Characteristics
(VDD = 2.7 to 3.6 V, Ta = –25 to +70°C)
Parameter
Transmit Frequency Response
Receive Frequency Response
Transmit Signal to Distortion
Receive Signal to Distortion
Transmit Gain Tracking
Symbol
Condition
Freq.(Hz) level (dBm0) Others
Typ.
0-60
25
—
—
LOSS T2
300-3k
–0.15
—
+0.2
LOSS T3
1020
LOSS T4
3300
0
—
—
+0.8
0.8
LOSS T5
3400
0
—
LOSS T6
3968.75
13
—
—
LOSS R1
0-3000
–0.15
—
+0.2
LOSS R2
1020
LOSS R3
3300
LOSS R4
LOSS R5
Reference
–0.15
—
+0.8
3400
0
—
0.8
3968.75
13
—
—
0
—
SD T1
3
35
—
—
SD T2
0
35
—
—
35
—
—
SD T3
1020
–30
(*2)
SD T4
–40
28
—
—
SD T5
–45
23
—
—
SD R1
3
35
—
—
SD R2
0
35
—
—
35
—
—
28
—
—
SD R3
1020
–30
(*2)
SD R4
–40
SD R5
–45
23
—
—
GT T1
3
–0.2
—
+0.2
GT T2
–10
1020
–0.2
—
+0.2
–50
–0.5
—
+0.5
GT T5
–55
–1.2
—
+1.2
3
–0.2
—
+0.2
–40
GT R2
—
—
+0.2
–50
–0.5
—
+0.5
GT R5
–55
–1.2
—
+1.2
–40
—
–0.2
NIDLT
—
AIN=SG
(*2)
—
—
NIDLR
—
(*3)
(*2)
—
—
AVT
AVR
1020
0
Power Supply Noise
PSRRT
Noise Freq.:
Noise Level:
Rejection Ratio
PSRRR
0 to 50 kHz
50 mVpp
dB
dB
dB
Reference
–10
1020
GT R4
GT R3
dB
Reference
GT T4
GT T3
Unit
dB
Reference
–0.15
Idle Channel Noise
Absolute Signal Amplitude
Max.
LOSS T1
GT R1
Receive Gain Tracking
Min.
dB
–68 dBm0p
(–75.7) (dBmp)
–72 dBm0p
(79.7) (dBmp)
GSX2
0.285 0.32(*4) 0.359
Vrms
VFRO
0.285 0.32(*4) 0.359
Vrms
—
30
—
—
dB
30
—
—
dB
*2. P-message weighted filter used
*3. PCMPCI input code: “11111111” (m-law)
*4. 0.320 Vrms=0 dBm0=–7.7 dBm
Note : All ADPCM coder and decoder characteristics fully comply with ITU-T Recommendations
G.726.
18/38
MSM7718-01
¡ Semiconductor
AC Characteristics (DTMF and Other Tones)
(VDD = 2.7 to 3.6 V, Ta = –25 to +70°C)
Parameter
Frequence Deviation
Tone Reference
Output Level (*5)
Relative Value of
DTMF Tones
Symbol
Condition
Min. Typ. Max. Unit
DfT1
DTMF Tones
–1.5
—
+1.5
%
Other various tones
–1.5
—
+1.5
%
–10
–8
–6 dBm0
DfT2
VTL
Transmit side tone
VTH
(Gain set value:0dB) DTMF (High group), Others
VRL
Recieve side tone
VRH
RDTMF
DTMF (Low group)
–8
–6
–4 dBm0
–10
–8
–6 dBm0
(Gain set value:0dB) DTMF (High group), Others
–8
–6
–4 dBm0
VTH/VTL, VRH/VRL
1
2
3
DTMF (Low group)
dB
*5 Not including programmable gain set values
AC Characteristics (Gain Settings)
(VDD = 2.7 to 3.6 V, Ta = –25 to +70°C)
Parameter
Transmit/Recieve Gain
Setting Accurancy
Symbol
DG
Condition
Min. Typ. Max. Unit
For all gain set values
–1
0
+1
dB
AC Characteristics (VOX Function)
(VDD = 2.7 to 3.6 V, Ta = –25 to +70°C)
Parameter
Symbol
Condition
Transmit VOX Detection Time
tVXON
SilenceÆvoice
voice signal ON/OFF Detect Time
tVXOFF
VoiceÆsilence
Transmit VOX Detection Level
Accuracy (Voice Detection Level)
DVX
VOXO pin:see Fig.6
Voice/silence
differential:10 dB
For detection level set values by
CRM6-B6,B5
Min.
Typ.
Max.
—
5
—
140/300 160/320 180/340
–2.5
0
+2.5
Unit
ms
ms
dB
19/38
MSM7718-01
¡ Semiconductor
AC Characteristics (Tone Detect Function)
(VDD = 2.7 to 3.6 V, Ta = –25 to +70°C)
Symbol
Condition
CPT Detection Frequency
fdetcp
—
CPT Non-detection Frequency
frejcp
—
CPT Detection Level
Vdetcp
CPT Non-detection Level
Vrejcp
Parameter
CPT Input Signal Continuation Time
Min. Typ. Max. Unit
Input Frequency: 350 to 640 Hz
—
tdetcp
CPT detected
trejcp
CPT not detected
—
350
—
640
Hz
700
—
—
Hz
—
—
250
Hz
–39
—
0
dBm0
—
—
–49 dBm0
55
—
—
ms
—
—
30
ms
30
45
55
ms
CPT Detection Delay Time
tdlycp
CPT Detection Hold Time
tholcp
7
16
24
ms
DTMF Detection Frequency
fdetdt
At Nominal Frequency
—
—
±1.5
%
DTMF Non-detection Frequency
—
frejdt
At Nominal Frequency
±3.8
—
—
%
DTMF Detection Level
Vdetdt
Input Frequency:Nominal Frequency ±1.5% –39
—
0
dBm0
DTMF Non-detection Level
Vrejdt
DTMF Input Signal continuation Time
—
—
—
–47 dBm0
tdetdt
CPT detected
38
—
—
ms
trejdt
CPT not detected
—
—
16
ms
DTMF Detection Delay Time
tdlydt
—
16
—
38
ms
DTMF Detection Hold Time
tholdt
—
14
—
25
ms
ANS Detection Frequency
fdetan
—
ANS Non-detection Frequency
frejan
ANS Detection Level
Vdetan
ANS Non-detection Level
Vrejan
ANS Input Signal Continuation Time
ANS Detection Delay Time
ANS Detection Hold Time
—
Input Frequency: 2079 to 2121 Hz
—
tdetan
CPT detected
trejan
CPT not detected
2079 2100 2121
Hz
2350
Hz
—
—
—
— 1900
–31
—
—
—
–35 dBm0
480
—
—
ms
0
Hz
dBm0
—
—
420
ms
tdlyan
—
420
450 480
ms
tholan
—
7
12
ms
tdetXX
17
trejXX
INPUT SIGNAL
DETECPT: CR7-B3
DETDTMF: CR7-B2
DET21L: CR7-B1
DET21L: CR7-B1
tdlyXX
tholXX
INT pin
INT: CR7-B4 (positive logic)
The state of the INT pin is changed by reading the
contents of CR7. It is retained when CR7 is not read.
Note : In the case of call progress tone, DTMF tone, and 2100 Hz tone, XX refers to cp, dt, and
an respectively.
20/38
MSM7718-01
¡ Semiconductor
FUNCTIONAL DESCRIPTION
Control Registers
Table 1 Control Register Map
Address
Reg
Name A4 A3 A2 A1 A0
Contents
B7
B6
B5
PDN/
RST
ADPCM ADPCM PCM AD
MODE RESET
SEL
PCM PCO PCM PCI PCM LN
MUTE MUTE
SEL2
TX
TX
TX
GAIN3 GAIN2 GAIN1
TX TONE TX TONE TX TONE
GAIN3 GAIN2 GAIN1
DTMF/OTHERS TX TONE RX TONE
SEL
SEND
SEND
ON
VOX
ON
LVL0
ON/OFF LVL1
VOX Silence level Silence level
1
0
OUT
LECTHR LECCLR1 LECCLR2
(HCL)*
AECTHR
AECCLR
—
(HCL)*
SEND/
MEM ADPCM
REC
SEL
MODE1
ST7/
ST6/
ST5/
A7
A6
A5
ST15/ ST14/
ST13/
A15
A14
A13
B4
0
0
0
0
0
CR1
0
0
0
0
1
CR2
0
0
0
1
0
CR3
0
0
0
1
1
CR4
0
0
1
0
0
CR5
0
0
1
0
1
CR6
0
0
1
1
0
CR7
0
0
1
1
1
CR8
0
1
0
0
0
CR9
0
1
0
0
1
CR10
0
1
0
1
0
CR11
0
1
0
1
1
CR12
0
1
1
0
0
CR13
0
1
1
0
1
—
—
—
CR14
0
1
1
1
0
SP7
SP6
SP5
SP4
CR15
0
1
1
1
1
SP15
SP14
SP13
CR16
1
0
0
0
0
—
—
—
CR17
1
0
0
0
1
CR18
1
0
0
1
0
PDWN
B2
B1
B0
R/W
OPE
OPE
OPE
OPE
MODE3 MODE2 MODE1 MODE0 R/W
TX
RX
RX
RX
RX
MUTE MUTE
MLV2
MLV1
MLV0 R/W
PCM LN PCM LN PCM AC PCM AC PCM AC
SEL1
SEL0
SEL2
SEL1
SEL0 R/W
TX
RX
RX
RX
RX
GAIN0 GAIN3 GAIN2 GAIN1 GAIN0 R/W
TX TONE RX TONE RX TONE RX TONE RX TONE
GAIN0 GAIN3 GAIN2 GAIN1 GAIN0 R/W
CR0
—
B3
—
TONE4
TONE0 R/W
TONE3
TONE2
TONE1
VOX
IN
DET
INT
CPT
LECHD LECCCLP
(NLP)*
AECCCLP
AECHD
(NLP)*
ADPCM
MODE0 CMD3
ST4/
ST3/
A4
A3
ST12/
ST11/
A12
A11
ST20/
ST19/
A20
A19
RX. NOISE
LEVEL SEL
DET
DTMF
LECHLD
(ADP)*
AECHLD
(APD)*
RX. NOISE RX. NOISE
LVL1
LVL0 R/W
BUSY/ RPM/
DET21L DET21A R
LECATT LECGC R/W
(ATT)* (GC)*
AECATT AECGC R/W
(ATT)* (GC)*
OFF
TIME
CMD2
CMD1
CMD0 R/W
ST2/
A2
ST10/
A10
ST18/
A18
ST1/
A1
ST9/
A9
ST17/
A17
ST0/
A0
ST8/
A8
ST16/
A16
R/W
SP3
SP2
SP1
SP0
R/W
SP12
SP11
SP10
SP9
SP8
R/W
SP20
SP19
SP18
SP17
SP16
R/W
R/W
R/W
D7/CA7 D6/CA6 D5/CA5 D4/CA4 D3/CA3 D2/CA2 D1/CA1 D0/CA0 R/W
WA7
WA6
WA5
WA4
D TONE3/ D TONE2/ D TONE1/
WA3
WA2
WA1
D TONE0/
R/W
WA0
R/W : Read/write enable R : Read only register
* : These are the symbols of control pins used in the MSM7602 (echo canceler LSI device).
21/38
MSM7718-01
¡ Semiconductor
(1)CR0 (Basic operating mode settings)
B7
B6
B5
B4
CR0
—
PDWN
PDN/RST
—
Initial value *
0
0
0
0
*:
B3
B2
B1
B0
OPE
OPE
OPE
OPE
MODE3
MODE2
MODE1
MODE0
0
0
0
0
Indicates the value to be set when a resetting is made through the PDN/RST pin. (Also
when reset by bit 5 (B5, PDN/RST), the other bits of CR0 are reset to initial values.)
B7 ... Not used
B6 ... Power-down (entire system)
0: Power-on 1: Power-down
ORed with the inverted external power-down signals
Set the PDWN pin to “1” when this data is used. The control registers and their internal
variables are not reset.
B5 ... Power-down reset (entire system)
0: Power-on 1: Power-down reset
ORed with the inverted external power-down reset signals
Set the PDN/RST pin to “1” when this data is used .
B4 ... Not used
B3, 2, 1, 0 ...... Selection of an operating mode
(0, 0, 0, 0) : Initial mode
This mode enables a change (see Figure 15-1, 2) in memory that contains internal default values such
as tone generation frequencies.
In this mode, the PCM output pin acts to output idle patterns and the PCM input pin acts to
input idle patterns. When a reset or power-down occurs or when power down is released,
the device enters the initial mode about 200 ms after that.
(0, 0, 0, 1) : Reserved
(0, 0, 1, 0) : Normal speech mode (see Figure 7-1)
This mode enables call services between a slave telephone and a line (including tone
generation) and detection of a DTMF tone and a call progress tone.
The internal process enables the tone detector. The ADPCM encoder/decoder, the tone
generator, and the line echo canceler become operative and can be controlled by the contents
of the control registers.
(0, 0, 1, 1) to (0, 1, 0, 0) : Reserved
(0, 1, 0, 1) : Line echo canceler expansion mode (see Figure 7-2)
This mode can expand the delay time of the line echo canceler up to 54 ms.
Concerning the internal processing, the ADPCM encoder/decoder, the line echo canceler, and
the tone generator become operative and can be controlled by the contents of the control
registers.
In addition, 2100 Hz tone of PCMLNI and PCMACI (bidirectional) can be detected.
(0, 1, 1, 0) to (1, 1, 1, 1) : Reserved
22/38
MSM7718-01
¡ Semiconductor
Note :
• When the MSM7718 is used in normal speech
mode, set the TSTI4 pin to “0”.
• In normal speech mode, the tone detector can
detect call progress tone and DTMF tone by
PMLNI input.
Tone Generator
Tone Detector
23 ms Line
Echo Canceler
ADPCM CODER
PCM CODEC
ADPCM DECODER
MSM7718
Figure 7-1 Normal Speech Mode
Note :
• When the MSM7718 is used in line echo
Tone Detector
canceler expansion mode, set the TSTI4 pin to
digital “1”.
54 ms Line
•
In
line echo canceler expansion mode, the
Echo Canceler
tone detector can detect not only call progress
tone and DTMF tone by PMLNI input but
ADPCM CODER
also 2100 Hz tone by PCMLNI and PCMACI
PCM CODEC
ADPCM DECODER
input (bidirectional).
• The PCM CODEC does not operate in this
mode. A capacitor is required between SGT
MSM7718
and ground and between SGR and ground
Figure 7-2 Line Echo Canceler Expansion
(see Application Circuit).
Mode
Tone Generator
23/38
MSM7718-01
¡ Semiconductor
(2) CR1 (Setting of ADPCM operating mode and PCM I/O signals)
CR1
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
ADPCM
ADPCM
PCM AD
TX
RX
RX
RX
RX
MODE
RESET
SEL
MUTE
MUTE
MLV2
MLV1
MLV0
0
0
0
0
0
0
0
0
B7 ... ADPCM algorithm
0: 32 kbps (G.726) 1: Reserved
B6 ... Transmitter/receiver ADPCM resetting (conforming to G.726)
1: Reset
B5 ... PCM I/O multiple timing control (PCMADI and PCMADO pins) of the ADPCM CODEC
0: Time slot 1 1: Time slot 2
B4 ... Muting of transmitter ADPCM data 1: Mute
B3 ... Muting of receiver ADPCM data
1: Muting specified by bits B2, B1, and B0 is enabled.
This bit is valid when the MUTE pin is “0”.
B2, B1, B0 ... Setting of a receiver voice path mute level
(MLV2, MLV1, MLV0) =
(0, 0, 0) :
(0, 0, 1) :
(0, 1, 0) :
(0, 1, 1) :
(1, 0, 0) :
(1, 0, 1) :
(1, 1, 0) :
(1, 1, 1) :
Through
– 6 dB
–12 dB
–18 dB
–24 dB
–30 dB
–36 dB
MUTE
24/38
MSM7718-01
¡ Semiconductor
(3) CR2 (Setting of PCM I/O multiple control)
CR2
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
PCM PCO
PCM PCI
PCM LN
PCM LN
PCM LN
PCM AC
PCM AC
PCM AC
MUTE
MUTE
SEL2
SEL1
SEL0
SEL2
SEL1
SEL0
0
0
0
0
0
0
0
0
B7 ... ON or OFF of the PCM signal of the transmitter side of the PCM CODEC (PCMPCO pin)
0: ON 1: OFF
When this bit is “1” (OFF), the PCMPCO pin transmits a PCM idle pattern.
B6 ... ON or OFF of the PCM signal of the receiver side of the PCM CODEC (PCMPCI pin)
0: ON 1: OFF
When this bit is “1” (OFF), the PCMPCI pin receives a PCM idle pattern.
B5, 4, 3 .... PCM I/O multiple timing control (PCMLNI and PCMLNO pins) of the line echo canceler
(see Table 2)
B2, 1, 0 .... PCM I/O multiple timing control (PCMACI and PCMACO pins) of the line echo canceler
(see Table 2)
Table 2 PCM Multiple Timing Control Table
B5
( B2
B4
B1
B3
B0 )
Corresponding time slot
0
0
0
None
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
Note : When bits B5 to B3 or B2 to B0 are all zeros, the internal process inputs a PCM idle pattern.
In this case, the outputs are all in high impedance state for all time slots.
25/38
MSM7718-01
¡ Semiconductor
(4) CR3 (Transmit/receive gain adjustment)
CR3
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
TX
TX
TX
TX
RX
RX
RX
RX
GAIN3
GAIN2
GAIN1
GAIN0
GAIN3
GAIN2
GAIN1
GAIN0
0
0
0
0
0
0
0
0
B7, 6, 5, 4 ...... Adjustment of the transmit signal gain [ATTtx]
(see Table 3)
B3, 2, 1, 0 ...... Adjustment of the receive signal gain [ATTrx]
(see Table 3)
Table 3 Transmit/Receive Signal Gain Setting
B7
B6
B5
B4
B3
B2
B1
B0
1
0
0
0
Transmit signal gain
–16 dB
1
0
0
0
Receive signal gain
–16 dB
1
0
0
1
–14 dB
1
0
0
1
–14 dB
1
0
1
0
–12 dB
1
0
1
0
–12 dB
1
0
1
1
–10 dB
1
0
1
1
–10 dB
1
1
0
0
–8 dB
1
1
0
0
–8 dB
1
1
0
1
–6 dB
1
1
0
1
–6 dB
1
1
1
0
–4 dB
1
1
1
0
–4 dB
1
1
1
1
–2 dB
1
1
1
1
–2 dB
0
0
0
0
0 dB
0
0
0
0
0 dB
0
0
0
1
+2 dB
0
0
0
1
+2 dB
0
0
1
0
+4 dB
0
0
1
0
+4 dB
0
0
1
1
+6 dB
0
0
1
1
+6 dB
0
1
0
0
+8 dB
0
1
0
0
+8 dB
0
1
0
1
+10 dB
0
1
0
1
+10 dB
0
1
1
0
+12 dB
0
1
1
0
+12 dB
0
1
1
1
+14 dB
0
1
1
1
+14 dB
This table is for gains of transmit/receive voice signals.
26/38
MSM7718-01
¡ Semiconductor
(5) CR4 (Adjustment of tone generator gain)
CR4
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
TX TONE
TX TONE
TX TONE
TX TONE
RX TONE
RX TONE
RX TONE
RX TONE
GAIN3
GAIN2
GAIN1
GAIN0
GAIN3
GAIN2
GAIN1
GAIN0
0
0
0
0
0
0
0
0
B7, 6, 5, 4 ...... Transmit side gain adjustment for the tone generator [ATTtgtx] (see Table 4)
B3, 2, 1, 0 ...... Receive side gain adjustment for the tone generator [ATTtgrx] (see Table 5)
Table 4 Setting of Transmit Side Gain of Tone Generator
B7
B6
B5
B4
Tone generator gain
B7
B6
B5
B4
Tone generator gain
0
0
0
0
–36 dB
1
0
0
0
–20 dB
0
0
0
1
–34 dB
1
0
0
1
–18 dB
0
0
1
0
–32 dB
1
0
1
0
–16 dB
0
0
1
1
–30 dB
1
0
1
1
–14 dB
0
1
0
0
–28 dB
1
1
0
0
–12 dB
0
1
0
1
–26 dB
1
1
0
1
–10 dB
0
1
1
0
–24 dB
1
1
1
0
–8 dB
0
1
1
1
–22 dB
1
1
1
1
–6 dB
Table 5 Setting of Receive Side Gain of Tone Generator
B3
B2
B1
B0
Tone generator gain
B3
B2
B1
B0
Tone generator gain
0
0
0
0
–36 dB
1
0
0
0
–20 dB
0
0
0
1
–34 dB
1
0
0
1
–18 dB
0
0
1
0
–32 dB
1
0
1
0
–16 dB
0
0
1
1
–30 dB
1
0
1
1
–14 dB
0
1
0
0
–28 dB
1
1
0
0
–12 dB
0
1
0
1
–26 dB
1
1
0
1
–10 dB
0
1
1
0
–24 dB
1
1
1
0
–8 dB
0
1
1
1
–22 dB
1
1
1
1
–6 dB
Settings of Table 5 are made in relation to the following tone levels:
DTMF tone (Low frequency group)
: –2 dBm0
DTMF tone (High frequency group) and other tone
: 0 dBm0
For example, when bits B3, B2, B1, and B0 are set to “1, 1, 1, 1” (–6 dB), the PCMLNO pin outputs a
tone of the following levels:
DTMF tone (Low frequency group)
: –8 dBm0
DTMF tone (High frequency group) and other tone
: –6 dBm0
The default value change command enables the gain adjustment by –1 dB step.
Writing “13CAh” into the address 00D8h adds a gain of –1 dB to the values in the above table. The
default value is “1634h”.
27/38
MSM7718-01
¡ Semiconductor
(6) CR5 (Setting of tone generator operating mode and tone frequency)
B7
B6
B5
DTMF/OTHERS TX TONE
CR5
RX TONE
SEL
SEND
SEND
0
0
0
Initial value
B4
B3
B2
B1
B0
TONE4
TONE3
TONE2
TONE1
TONE0
0
0
0
0
0
B7 ... Selection of DTMF signal or others (S, F, or R tone)
0: Others 1: DTMF signal
B6 ... Transmission of transmit side tone
0: Not transmit 1: Transmit
B5 ... Transmission of receive side tone
0: Not transmit 1: Transmit
B4, 3, 2, 1, 0 ... Setting of a tone frequency (see Table 6)
Table 6 Setting of Tone Generator Frequencies
(a) when B7 = “1” (DTMF tone)
B4 B3 B2 B1 B0
Description
B4 B3 B2 B1 B0
Description
*
0
0
0
0
697 Hz + 1209 Hz (1)
*
1
0
0
0
852 Hz + 1209 Hz (7)
*
0
0
0
1
697 Hz + 1336 Hz (2)
*
1
0
0
1
852 Hz + 1336 Hz (8)
*
0
0
1
0
697 Hz + 1477 Hz (3)
*
1
0
1
0
852 Hz + 1477 Hz (9)
*
0
0
1
1
697 Hz + 1633 Hz (A)
*
1
0
1
1
852 Hz + 1633 Hz (C)
*
0
1
0
0
770 Hz + 1209 Hz (4)
*
1
1
0
0
941 Hz + 1209 Hz (*)
*
0
1
0
1
770 Hz + 1336 Hz (5)
*
1
1
0
1
941 Hz + 1336 Hz (0)
*
0
1
1
0
770 Hz + 1477 Hz (6)
*
1
1
1
0
941 Hz + 1477 Hz (#)
*
0
1
1
1
770 Hz + 1633 Hz (B)
*
1
1
1
1
941 Hz + 1633 Hz (D)
(b) When B7 = “0” (Others)
The Table below lists default frequencies. “00000” to “00011” (“B4, B3, B2, B1, B0”) are tones,
which are modulated by sinewave. “01000” to “01011” are wamble tones, and “10000” to “10111”
are single tones. For procedures to change frequencies, see the next page.
B4 B3 B2 B1 B0
Description
B4 B3 B2 B1 B0
Description
0
0
0
0
0
400/0H – 16 Hz Sine wave modulation
1
0
0
0
0
400 Hz Single tone
0
0
0
0
0
3000/0H – 16 Hz Sine wave modulation
1
0
0
0
1
1000 Hz Single tone
0
0
0
1
0
2700/0H – 16 Hz Sine wave modulation
1
0
0
0
1
2000 Hz Single tone
0
0
0
1
1
*/*H – 16 Hz Sine wave modulation
1
0
0
1
1
2667 Hz Single tone
0
0
1
0
0
—
1
0
1
0
0
1300 Hz Single tone
0
0
1
0
1
—
1
0
1
0
1
2080 Hz Single tone
1
0
1
1
0
*Hz Single tone
0
0
1
1
0
—
0
0
1
1
1
—
1
0
1
1
1
*Hz Single tone
0
1
0
0
0
513/636 Hz 12 Hz Wamble
1
1
0
0
0
—
0
1
0
0
1
800/1000 Hz 8 Hz Wamble
1
1
0
0
1
—
0
1
0
1
0
2000/2667 Hz 8 Hz Wamble
1
1
0
1
0
—
0
1
0
1
1
*/*Hz *Hz Wamble
1
1
0
1
1
—
0
1
1
0
0
—
1
1
1
0
0
—
0
1
1
0
1
—
1
1
1
0
1
—
0
1
1
1
0
—
1
1
1
1
0
—
0
1
1
1
1
—
1
1
1
1
1
—
28/38
MSM7718-01
¡ Semiconductor
Frequencies of tones (other than DTMF signals) to be generated by the tone generator can be changed.
Tone frequencies can be changed in the Initial mode. See Figure 15-1 for procedures to change tone
frequencies. The related subaddresses are shown below.
Modulation by 16 Hz sine wave
B4 B3 B2 B1 B0
Subaddress 1
(Frequency 1)
*1
0
0
0
0
0
164h
0
0
0
0
1
165h
0
0
0
1
0
166h
0
0
0
1
1
167h
Modulation by 16 Hz sine wave
62.5 ms
Wamble
B4 B3 B2 B1 B0
Subaddress 1
(Frequency 1)
*1
Subaddress 2
(Frequency 2)
*1
Subaddress 3
(Time 1)
*2
Subaddress 4
(Time 2)
*2
168h
16Ch
170h
174h
0
1
0
0
0
0
1
0
0
1
169h
16Dh
171h
175h
0
1
0
1
0
16Ah
16Eh
172h
176h
0
1
0
1
1
16Bh
16Fh
173h
177h
Single tone
B4 B3 B2 B1 B0
Subaddress 1
(Frequency 1)
*1
1
0
0
0
0
178h
1
0
0
0
1
179h
1
0
0
1
0
17Ah
1
0
0
1
1
17Bh
1
0
1
0
0
17Ch
1
0
1
0
1
17Dh
1
0
1
1
0
17Eh
1
0
1
1
1
17Fh
8 Hz wamble tone
Time 1
62.5 ms
Time 2
62.5 ms
Transmit single tone
*1 Transmitted Tone Frequency = A ¥ 8.192 (A = frequency)
ex. When frequency = 1000 Hz, 1000 ¥ 8.192 = 9011.2 = 9011d (eliminate after the decimal
point) = 2333h
*2
Wamble Frequency (Tone Transmit time) = (A/B)/2 – 1
(A = Transmitted tone frequency, B = wamble frequency)
ex. When wamble frequency is 8 Hz, tone frequency = 2667 Hz.
(2667/8)/2 – 1 = 166.69 = 166d (eliminate after the decimal point) = A6h
29/38
MSM7718-01
¡ Semiconductor
(7)CR6 (VOX function control)
CR6
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
VOX
ON
ON
OFF
VOX
RX. NOISE
RX. NOISE
RX. NOISE
ON/OFF
LVL1
LVL0
TIME
IN
LEVEL SEL
LVL1
LVL0
0
0
0
0
0
0
0
0
B7 ... Turns ON or OFF the VOX function. 0: OFF, 1: ON
B6, 5 ... Setting of transmit side voice or silence detection level
(0, 0) : –20 dBm0
(0, 1) : –25 dBm0
(1, 0) : –30 dBm0
(1, 1) : –35 dBm0
Note: • The detection level is changeable by inserting the pad of –1 dB to –5 dB in addition to the
above values.
• Write 16384 ¥ 10 (–A/20) at address "175h". (A=pad)
Example: When –1 dB pad is inserted, 16384 ¥ 10 (– (–1)/20)
=18383.15=18383d (eliminate after the decimal point)=47CFh
B4 ... Setting of hangover time (TVXOFF) (see Figure 6)
0: 160 ms 1: 320 ms
B3 ... VOX input signal (receiver side)
0: Transmits an internal background noise.
1: Transmits a voice reception signal.
Set the VOXI pin to “0” to use this data.
B2 ... Setting of a receiver side background noise level
0: Automatic internal setting
1: Reserved
B1, 0 ... Externally-set background noise level
(0, 0) : No noise
(0, 1) : –55 dBm0
(1, 0) : –45 dBm0
(1, 1) : –35 dBm0
(8) CR7 (Detection register : read-only)
B7
CR7
Initial value
VOX
B6
B5
Silence level Silence level
OUT
1
0
0
0
0
B4
INT
0
DET
B3
B2
DET
B1
BUSY/
B0
PRM/
CPT
DTMF
DET21L
DET21A
0
0
0
0
B7 ... Detection of transmit side voice or noise
0: Silence 1: Voice
B6, 5 ... Transmit side silence level (indicator)
(0, 0) : –10 dB or less with respect to the detection level defined by CR6-B6, B5.
(0, 1) : –5 to –10 dB with respect to the detection level defined by CR6-B6, B5.
(1, 0) : 0 to –5 dB with respect to the detection level defined by CR6-B6, B5.
(1, 1) : 0 dB or more. Refer to the detection level defined by CR6-B6, B5.
Note : The above outputs are valid only when the VOX function is enabled by bit 7 of CR6.
B4 ... External interrupt signal
Goes to a logic “0” when any change has been found in the tone detection results for call
progress tone, DTMF tone, and 2100 Hz tone.
Goes to a logic “1” when the CR7 control register is read out .
The inverted state of this bit (B4) is output to the INT pin.
30/38
MSM7718-01
¡ Semiconductor
B3 ... Detection of a call progress tone
1: Detected
B2 ... Detection of a DTMF tone
1: Detected
B1 ... PCMLNI input 2100 Hz tone detection (DET21L:
expansion mode)
1: Detected
0: Not detected
B0 ... PCMACI input 2100 Hz tone detection (DET21A:
expansion mode)
1: Detected
0: Not detected
0: Not detected
0: Not detected
valid only in the line echo canceler
valid only in the line echo canceler
(9) CR8 (Setting of line echo canceler operating mode)
B7
CR8
Initial value
LECTHR
(HCL)*1
1
B6
B5
LECCLR1 LECCLR2
0
0
B4
LECHD
0
B3
B2
B1
B0
LECCCLP
LECHLD
LECATT
LECGC
(NLP)*1
(ADP)*1
(ATT)*1
(GC)*1
0
0
0
0
*1 Names of control pins used in the MSM7602
B7 ... “Through” mode control bit for the line echo canceler.
In the “Through” mode, RinL and SinL data is output directly to RoutL and SoutL
respectively.
1: “Through” mode 0: Normal mode (echo cancellation)
B6 ... Selects whether or not to clear the coefficient 1 of the adaptive FIR filter (LAFF) used by the
line echo canceler.
1: Resets the coefficient
0: Normal operation
B5 ... Selects whether or not to clear the coefficient 2 of the adaptive FIR filter (LAFF) used by the
line echo canceler.
1: Resets the coefficient
0: Normal operation
B4 ... Howling detector (HD) ON/OFF control
1: ON 0: OFF
B3 ... Turns ON or OFF the center clip function which forcibly sets the SoutL output of the line echo
canceler to minimum positive value when it is –57 dBm0 or less.
1: Center clip function ON
0: Center clip function OFF
B2 ... Selects whether or not to update the coefficient of the adaptive FIR filter (LAFF) for the line echo
canceler.
1: Coefficient fixed mode
0: Normal mode (updates the coefficient)
B1 ... Turns ON or OFF the ATT function which prevents howling from occurring by means of
attenuators ATTsL and ATTrL provided for the RinL input and the SoutL output of the line
echo canceler.
When a signal is input to RinL only, the attenuator ATTsL of the SoutL output is activated.
When a signal is input to SinL only or to both SinL and RinL, the attenuator ATTrL of the
RinL input is activated. Their ATT values are both about 6 dB.
1: ATT OFF
0: ATT ON
B0 ... Turns ON or OFF the gain control function which controls the RinL input level and
prevents howling from occurring by the gain controller (GainL) for the RinL input of the line
echo canceler.
The gain controller adjusts the RIN level when it is –24 dBm0 or above, and it has the control
range of 0 to –8.5 dB.
1: Gain control ON
0: Gain control OFF
31/38
MSM7718-01
¡ Semiconductor
(10) CR9 : Reserved (Setting of acoustic echo canceler operating mode)
B7
CR9
Initial value
AECTHR
(HCL)*1
1
B6
B5
B4
—
AECCLR
AECHD
0
0
0
B3
B2
B1
B0
AECCCLP
AECHLD
AECATT
AECGC
(NLP)*1
(ADP)*1
(ATT)*1
(GC)*1
0
0
0
0
*1 Names of control pins used in the MSM7602
B7 ... Acoustic echo canceler through-mode control bit
In this mode, RinA data and SinA data are through-output to RoutL and SoutL respectively.
1: Through mode 0: Normal mode (echo cancellation)
B6 ... Not used
B5 ... Selects whether or not to clear the coefficient of the adaptive FIR filter (AAFF) for the
acoustic echo canceler.
1: Resets the coefficient 0: Normal operation
B4 ... Howling detector (HD) ON/OFF control
1: ON 0: OFF
B3 ... Turns ON or OFF the center clip function which forcibly sets the Sout output of the acoustic
echo canceler to a minimum positive value when it is –57 dBm0 or less.
1: Center clip function ON
2: Center clip function OFF
B2 ... Selects whether or not to update the coefficient of the adaptive FIR filter (AAFF) for the
acoustic echo canceler.
1: Coefficient Fixed mode
0: Normal mode (updates the coefficient.)
B1 ... Turns ON or OFF the ATT function which prevents howling from occurring by means of
attenuators ATTrA and ATTsA provided for the RinA input and the SoutA output of the
acoustic echo canceler.
When a signal is input to RinA only, the attenuator ATTsA of the SoutA output is activated.
When a signal is input to SinA only or to both SinA and RinA, the attenuator ATTrA of the RinA
input is activated. Their ATT values are both about 6 dB.
1: ATT OFF
0: ATT ON
B0 ... Turns ON or OFF the gain control function which controls the RinA input level and
prevents howling from occurring by the gain controller (GainA) for the RinA input of the
acoustic echo canceler.
The gain controller starts controlling when the RIN level is –24 dBm0 or above and has the
control range of 0 to –8.5 dB.
1: Gain control ON
0: Gain control OFF
32/38
MSM7718-01
¡ Semiconductor
(11) CR10 (External memory (flash memory) interface control)
CR10
Initial value
B7
B6
B5
B4
SEND/
MEM
ADPCM
ADPCM
REC
SEL
MODE1
MODE0
0
0
0
0
B3
B2
B1
B0
CMD3
CMD2
CMD1
CMD0
0
0
0
0
B7 ... Reserved (connection to the recording interface)
B6 ... Reserved (selection of external memory)
B5, 4 ... Reserved (selection of recording/playback ADPCM compression mode)
B3, 2, 1, 0 ... Reserved (memory interface command)
(0, 0, 0, 0) : NOP
(0, 0, 0, 1) : Reserved
(0, 0, 1, 0) : Reserved
(0, 0, 1, 1) : Reserved
(0, 1, 0, 0) : Reserved
(0, 1, 0, 1) : Reserved
(0, 1, 1, 0) : Reserved
(0, 1, 1, 1) : Reserved
(1, 0, 0, 0) : Reserved
(1, 0, 0, 1) : Reserved
(1, 0, 1, 0) : Reserved
(1, 0, 1, 1) : Reserved
(1, 1, 0, 0) : Reserved
(1, 1, 0, 1) : MDWR (Change default)
Writes the data of CR17 (D0 to D7) and CR16 (D8 to D15) in the lower byte of
default storage memory. The address is specified by A0 to A7 of CR11 and A8
to A15 of CR12.
(1, 1, 1, 0) : Reserved
(1, 1, 1, 1) : Reserved
33/38
MSM7718-01
¡ Semiconductor
(12) CR11, 12, 13 (Memory address register 1)
CR11
Initial value
CR12
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
ST7/
ST6/
ST5/
ST4/
ST3/
ST2/
ST1/
ST0/
A7
A6
A5
A4
A3
A2
A1
A0
—
—
—
—
—
—
—
—
B7
B6
B5
B4
B3
B2
B1
B0
ST15/
ST14/
ST13/
ST12/
ST11/
ST10/
ST9/
ST8/
A15
A14
A13
A12
A11
A10
A9
A8
—
—
—
—
—
—
—
—
B7
B6
B5
CR13
—
—
—
Initial value
—
—
—
B4
B3
B2
B1
B0
ST20/
ST19/
ST18/
ST17/
ST16/
A20
A19
A18
A17
A16
—
—
—
—
—
CR11 to 13 : Registers storing an address (A0 to A20) required for the default value change
command
Since CR13 is assigned “0h”, no setting is requited for it.
(13) CR14, 15, 16 (Memory address register 2)
B7
B6
B5
B4
B3
B2
B1
B0
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
—
—
—
—
—
—
—
—
B7
B6
B5
B4
B3
B2
B1
B0
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
—
—
—
—
—
—
—
—
B7
B6
B5
B4
B3
B2
B1
B0
CR16
—
—
—
SP20
SP19
SP18
SP17
SP16
Initial value
—
—
—
—
—
—
—
—
CR14
Initial value
CR15
Initial value
CR14 to 16:
When the default value change command is used, the bit 7 to bit 0 of CR16 correspond to the D15 to D8 of write data.
Note : CR14 and CR15 are the reserved registers.
34/38
MSM7718-01
¡ Semiconductor
(14) CR17 (Memory data register)
CR17
B7
B6
B5
B4
B3
B2
B1
B0
D7/CA7
D6/CA6
D5/CA5
D4/CA4
D3/CA3
D2/CA2
D1/CA1
D0/CA0
—
—
—
—
—
—
—
—
Initial value
CR17 is the register to store the data used by the default value store command.
(15) CR18 (Setting of tone detection frequency, memory address register 3)
CR18
B7
B6
B5
B4
WA7
WA6
WA5
WA4
—
—
—
0
Initial value
B3
B2
B1
B0
D TONE3/ D TONE2/ D TONE1/ D TONE0/
WA3
WA2
WA1
WA0
0
0
0
0
D TONE3 to 0: Valid only when the tone generator is operating (except for the initial mode)
B7, 6, 5, 4 ... Not used
B3, 2, 1, 0 ... Setting of a tone frequency (see Table 7)
Table 7 Setting of Tone Detector Frequencies
B3
B2
B1
B0
Frequency
B3
B2
B1
B0
Frequency
0
0
0
0
697 Hz + 1209 Hz (1)
1
0
0
0
697 Hz + 1477 Hz (3)
0
0
0
1
770 Hz + 1209 Hz (4)
1
0
0
1
770 Hz + 1477 Hz (6)
0
0
1
0
852 Hz + 1209 Hz (7)
1
0
1
0
852 Hz + 1477 Hz (9)
0
0
1
1
941 Hz + 1209 Hz (*)
1
0
1
1
941 Hz + 1477 Hz (#)
0
1
0
0
697 Hz + 1336 Hz (2)
1
1
0
0
697 Hz + 1633 Hz (A)
0
1
0
1
770 Hz + 1336 Hz (5)
1
1
0
1
770 Hz + 1633 Hz (B)
0
1
1
0
852 Hz +1336 Hz (8)
1
1
1
0
852 Hz + 1633 Hz (C)
0
1
1
1
941 Hz + 1336 Hz (0)
1
1
1
1
941 Hz + 1633 Hz (D)
35/38
MSM7718-01
¡ Semiconductor
Direct Access to Default Store Memory (See Figs.8-1, 8-2)
The contents of the default store memory can be
changed (e.g., to change tone detection levels
and tone generation frequencies) in the initial
mode (CR0-B3 to CR0-B0="0000").
Refer to the following procedure:
Default Value Store Memory
Direct Access
Set address.
Set write data.
1.Set the default value store memory address
(CR11, CR12).
Set the write data into CR16 and CR17.
2.When writing data to the upper byte, set the
DMWR (change default) command (CR10-B3
to CR10-B0="1101").
Set command to
write in upper byte
(DMWR)
Yes
(1) CR12, CR11
CR16, CR17
(2) CR10
Continue to
write?
No
END
Figure 8-1 Flow Chart of Default Value Store
Memory Direct Access
Default Value Store Memory
Data (CR16, CR17)
Address (CR11, CR12)
Figure 8-2 Memory Map for Default Value Store Memory Direct Access
36/38
MSM7718-01
¡ Semiconductor
APPLICATION CIRCUIT
MSM7718
IS
IR
1 mF
+
–
10 mF
+
10 mF
–
1 mF
1 mF
Voice Analog Input (Vi)
Transmit Gain (VGSX2/Vi)
= (R2/R1) ¥ (R4/R3)
Receive Gain (VO/VVFRO)
= 2 ¥ R5/R6
Receiver Output VO
1 mF R1
R2
1 mF R3
R4
R6
R5
ZL = 120 nF +
350 W
VDDD1,2,3
VDDA
SGT
SGR
AG
DG1,2,3
AIN1+
AIN1–
GSX1
AIN2
GSX2
VFRO
PWI
AOUT–
BCLKA
SYNCA
VOXO
ADPCM
Transmit Data
ADPCM
Receive Data
ADPCM
Control
VOXI
PCMPCI
PCMPCO
PCMLNI
PCMLNO
PCMACI
PCMACO
PCMADI
PCMADO
BLKP
SYNCP
PCM
Control
AOUT+
A20-19
A18-0
D7-0
WE
OE
Basic
Controller
MCK
PDN/RST
PDWN
EXCK
DEN
DIN
DOUT
INT
RP
CS1
CS2
37/38
MSM7718-01
¡ Semiconductor
PACKAGE DIMENSIONS
(Unit : mm)
TQFP100-P-1414-0.50-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.55 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
38/38