E2O0018-27-X2 This version: Jan. 1998 MSM82C53-2RS/GS/JS Previous version: Aug. 1996 ¡ Semiconductor MSM82C53-2RS/GS/JS ¡ Semiconductor CMOS PROGRAMMABLE INTERVAL TIMER GENERAL DESCRIPTION The MSM82C53-2RS/GS/JS is programmable universal timers designed for use in microcomputer systems. Based on silicon gate CMOS technology, it requires a standby current of only 100 mA (max.) when the chip is in the nonselected state. During timer operation, power consumption is still very low only 8 mA (max.) at 8 MHz of current required. The device consists of three independent counters, and can count up to a maximum of 8 MHz (MSM82C53-2). The timer features six different counter modes, and binary count/BCD count functions. Count values can be set in byte or word units, and all functions are freely programmable. FEATURES • Maximum operating frequency of 8 MHz (MSM82C53-2) • High speed and low power consumption achieved through silicon gate CMOS technology • Completely static operation • Three independent 16-bit down-counters • 3 V to 6 V single power supply • Six counter modes available for each counter • Binary and decimal counting possible • 24-pin Plastic DIP (DIP24-P-600-2.54): (Product name: MSM82C53-2RS) • 28-pin Plastic QFJ (QFJ28-P-S450-1.27): (Product name: MSM82C53-2JS) • 32-pin Plastic SSOP(SSOP32-P-430-1.00-K): (Product name: MSM82C53-2GS-K) 1/19 ¡ Semiconductor MSM82C53-2RS/GS/JS FUNCTIONAL BLOCK DIAGRAM VCC GND 8 D7 - D0 Data Bus Buffer Counter CLK0 GATE0 #0 OUT0 Read/ Write Logic Counter CLK1 #1 OUT1 Control Word Register Counter CLK2 8 WR RD A0 GATE1 A1 CS GATE2 #2 OUT2 Internal Bus 2/19 ¡ Semiconductor MSM82C53-2RS/GS/JS PIN CONFIGURATION (TOP VIEW) 24 pin Plastic DIP D7 1 24 Vcc D6 2 23 WR D5 3 22 RD D4 4 21 CS D3 5 20 A1 D2 6 19 A0 D1 7 18 CLK2 D0 8 17 OUT2 CLK0 9 16 GATE2 OUT0 10 15 CLK1 GATE0 11 14 GATE1 13 OUT1 GND 12 NC D7 D6 D5 32 pin Plastic SSOP NC D4 D3 D2 D1 D0 CLK0 NC OUT0 GATE0 GND NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 NC Vcc WR RD NC CS A1 A0 CLK2 OUT2 GATE2 NC CLK1 GATE1 OUT1 NC 26 RD 27 WR 28 VCC 1 NC 2 D7 D4 5 25 NC D3 6 24 CS D2 7 23 A1 D1 8 22 A0 D0 9 21 CLK2 CLK0 10 20 OUT2 CLK1 18 OUT1 16 GATE1 17 NC 15 GND 14 19 GATE2 OUT0 12 NC 11 GATE0 13 28 pin Plastic QFJ 3 D6 4 D5 (NC denotes "not connected") 3/19 ¡ Semiconductor MSM82C53-2RS/GS/JS ABSOLUTE MAXIMUM RATINGS Parameter Rating Condition Symbol MSM82C53-2RS Supply Voltage Input Voltage Output Voltage Storage Temperature Power Dissipation VCC Respect to GND VIN VOUT TSTG — PD Ta = 25°C Units MSM82C53-2GS MSM82C53-2JS –0.5 to + 7 V –0.5 to VCC + 0.5 V –0.5 to VCC + 0.5 V –55 to + 150 0.9 °C 0.7 0.9 W OPERATING RANGES Parameter Symbol Condition Range Unit Supply Voltage VCC VIL = 0.2 V, VIH = VCC -0.2 V, Operating Frequency 2.6 MHz 3 to 6 V Operating Temperature Top –40 to +85 °C RECOMMENDED OPERATING CONDITIONS Symbol Min. Typ. Max. Unit Supply Voltage Parameter VCC 4.5 5 5.5 V Operating Temperature Top –40 +25 +85 °C "L" Input Voltage VIL –0.3 — +0.8 V "H" Input Voltage VIH 2.2 — VCC + 0.3 V DC CHARACTERISTICS Parameter Symbol Condition "L" Output Voltage VOL IOL = 4 mA Min. — Typ. Max. Unit — 0.45 V "H" Output Voltage VOH IOH = –1 mA 3.7 — — V Input Leak Current ILI 0 £ VIN £ VCC VCC = 4.5 V to 5.5 V –10 — 10 mA Output Leak Current ILO 0 £ VOUT £ VCC Ta = –40°C to +85°C –10 — 10 mA Standby Supply Current ICCS CS ≥ VCC - 0.2 V VIH ≥ VCC - 0.2 V VIL £ 0.2 V — — 100 mA Operating Supply Current ICC tCLK = 125 ns CL = 0 pF — — 8 mA 4/19 ¡ Semiconductor MSM82C53-2RS/GS/JS AC CHARACTERISTICS (VCC = 4.5 V to 5.5 V, Ta = –40 to +85°C) Parameter Address Set-up Time before Reading Address Hold Time after Reading Read Pulse Width Read Recovery Time Address Set-up Time before Writing Address Hold Time after Writing Write Pulse Width Data Input Set-up Time before Writing Data Input Hold Time after Writing Write Recovery Time Clock Cycle Time Clock "H" Pulse Width Clock "L" Pusle Width "H" Gate Pulse Width "L" Gate PUlse Width Gate Input Set-up Time before Clock Gate Input Hold Time after Clock Output Delay Time after Reading Output Floating Delay Time after Reading Output Delay Time after Gate Output Delay Time after Clock Output Delay Time after Address Symbol MSM82C53-2 Unit Min. 30 0 150 200 0 20 150 100 20 200 125 60 60 50 Max. — — — — — — — — — — D.C. — — — tGS tGH tRD 50 50 50 — — — — 120 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tDF 5 90 ns tODG tOD tAD — — — 120 150 180 ns ns ns tAR tRA tRR tRVR tAW tWA tWW tDW tWD tRVW tCLK tPWH tPWL tGW tGL Condition Read Cycle Write Cycle CL = 150 pF Clock and Gate Timing Delay Time Note: Timing measured at VL = 0.8 V and VH = 2.2 V for both inputs and outputs. 5/19 ¡ Semiconductor MSM82C53-2RS/GS/JS TIMING CHART WriteTiming A0 - 1 CS tAW tWA D0 - 7 tDW WR tWD tWW Read Timing A0 - 7, CS tAR tRA tRR RD tRD tAD D0 - 7 tDF Valid High Impedance High Impedance Clock & Gate Timing tCLK tPWL CLK tPWH tGH tGS tGS tGL GATE tGH tGW tODG tOD OUT 6/19 ¡ Semiconductor MSM82C53-2RS/GS/JS DESCRIPTION OF PIN FUNCTIONS Pin Symbol Name Input/Output Function D7 - D 0 Bidirectional Data Bus Input/Output Three-state 8-bit bidirectional data bus used when writing control words and count values, and reading count values upon reception of WR and RD signals from CPU. CS Chip Select Input Input RD Read Input Input Data can be transferred from MSM82C53-2 to CPU when this pin is at low level. WR Write Input Input Data can be transferred from CPU to MSM82C53-2 when this pin is at low level. A 0 - A1 Address Input Input One of the three internal counters or the control word register is selected by A0/A1 combination. These two pins are normally connected to the two lower order bits of the address bus. CLK0 - 2 Clock Input Input Supply of three clock signals to the three counters incorporated in MSM82C53-2. GATE0 - 2 Gate Input Input Control of starting, interruption, and restarting of counting in the three respective counters in accordance with the set control word contents. OUT0 - 2 Counter Output Output Data transfer with the CPU is enabled when this pin is at low level. When at high level, the data bus (D0 thru D7) is switched to high impedance state where neither writing nor reading can be executed. Internal registers, however, remain unchanged. Output of counter output waveform in accordance with the set mode and count value. SYSTEM INTERFACING Address Bus A1 A0 16 bits Control Bus Data Bus 8 bits 8 bits A1 A0 CS RD D7 - 0 MSM82C53-2 WR Counter #0 Counter #1 Counter #2 OUT GATE CLK OUT GATE CLK OUT GATE CLK 7/19 ¡ Semiconductor MSM82C53-2RS/GS/JS DESCRIPTION OF BASIC OPERATIONS Data transfers between the internal registers and the external data bus is outlined in the following table. CS RD WR A1 A0 0 1 0 0 0 Data Bus to Counter #0 Writing 0 1 0 0 1 Data Bus to Counter #1 Writing 0 1 0 1 0 Data Bus to Counter #2 Writing 0 1 0 1 1 Data Bus to Control Word Register Writing Function 0 0 1 0 0 Data Bus from Counter #0 Reading 0 0 1 0 1 Data Bus from Counter #1 Reading 0 0 1 1 0 Data Bus from Counter #2 Reading 0 0 1 1 1 1 ¥ ¥ ¥ ¥ 0 1 1 ¥ ¥ Data Bus High Impedance Status ¥ denotes "not specified". DESCRIPTION OF OPERATION MSM82C53-2 functions are selected by a control word from the CPU. In the required program sequence, the control word setting is followed by the count value setting and execution of the desired timer operation. Control Word and Count Value Program Each counter operation mode is set by control word programming. The control word format is out-lined below. D7 D6 D5 D4 D3 D2 D1 D0 SC1 SC0 RL1 RL0 M2 M1 M0 BCD Select Counter Read/Load Mode BCD (CS=0, A0, A1=1, 1, RD=1, WR=0) 8/19 ¡ Semiconductor MSM82C53-2RS/GS/JS • Select Counter (SC0, SC1): Selection of set counter SC1 SC0 0 0 Counter #0 Selection 0 1 Counter #1 Selection 1 0 Counter #2 Selection 1 1 Illegal Combination Set Contents • Read/Load (RL1, RL0): Count value Reading/Loading format setting Set Contents RL1 RL0 0 0 0 1 Reading/Loading of Least Significant Byte (LSB) 1 0 Reading/Loading of Most Significant Byte (MSB) 1 1 Reading/Loading of LSB Followed by MSB Counter Latch Operation • Mode (M2, M1, M0): Operation waveform mode setting M2 M1 M0 0 0 0 0 Set Contents Mode 0 (Interrupt on Terminal Count) 0 1 Mode 1 (Programmable One-Shot) ¥ 1 0 Mode 2 (Rate Generator) ¥ 1 1 Mode 3 (Square Wave Generator) 1 0 0 1 0 1 Mode 4 (Software Triggered Strobe) Mode 5 (Hardware Triggered Strobe) ¥ denotes "not specified". • BCD: Operation count mode setting Set Contents BCD 0 Binary Count (16-bit Binary) 1 BCD Count (4-decade Binary Coded Decimal) After setting Read/Load, Mode, and BCD in each counter as outlined above, next set the desired count value. (In some Modes, counting is started immediately after the count value has been written). This count value setting must conform with the Read/Load format set in advance. Note that the internal counters are reset to 0000H during control word setting. The counter value (0000H) can’t be read. If the two bytes (LSB and MSB) are written at this stage (RL0 and RL1 = 1,1), take note of the following precaution. Although the count values may be set in the three counters in any sequence after the control word has been set in each counter, count values must be set consecutively in the LSB - MSB order in any one counter. 9/19 ¡ Semiconductor MSM82C53-2RS/GS/JS • Example of control word and count value setting Counter #0: Read/Load LSB only, Mode 3, Binary count, count value 3H Counter #1: Read/Load MSB only, Mode 5, Binary count, count value AA00H Counter #2: Read/Load LSB and MSB, Mode 0, BCD count, count value 1234 MVI A, 1EH OUT n3 Counter #0 control word setting MVI A, 6AH OUT n3 Counter #1 control word setting MVI A, B1H OUT n3 Counter #2 control word setting MVI A, 03H OUT n0 Counter #0 control value setting MVI A, AAH OUT n1 Counter #1 control value setting MVI A, 34H OUT n2 Counter #2 count value setting (LSB then MSB) MVI A, 12H OUT n2 Notes: n0: Counter #0 address n1: Counter #1 address n2: Counter #2 address n3: Control word register address • The minimum and maximum count values which can be counted in each mode are listed below. Mode MIn. Max, 0 1 0 1 1 0 — 2 2 0 1 cannot be counted 3 2 1 1 executes 10001H count 4 1 0 5 1 0 Remarks 0 executes 10000H count (ditto in other modes) — — 10/19 ¡ Semiconductor MSM82C53-2RS/GS/JS Mode Definition • Mode 0 (terminal count) The counter output is set to “L” level by the mode setting. If the count value is then written in the counter with the gate input at “H” level (that is, upon completion of writing the MSB when there are two bytes), the clock input counting is started. When the terminal count is reached, the output is switched to “H” level and is maintained in this status until the control word and count value are set again. Counting is interrupted if the gate input is switched to “L” level, and restarted when switched back to “H” level. When Count Values are written during counting, the operation is as follows: 1-byte Read/Load. ............ When the new count value is written, counting is stopped immediately, and then restarted at the new count value by the next clock. 2-byte Read/Load ............. When byte 1 (LSB) of the new count value is written, counting is stopped immediately. Counting is restarted at the new count value when byte 2 (MSB) is written. • Mode 1 (programmable one-shot) The counter output is switched to “H” level by the mode setting. Note that in this mode, counting is not started if only the count value is written. Since counting has to be started in this mode by using the leading edge of the gate input as a trigger, the counter output is switched to “L” level by the next clock after the gate input trigger. This “L” level status is maintained during the set count value, and is switched back to “H” level when the terminal count is reached. Once counting has been started, there is no interruption until the terminal count is reached, even if the gate input is switched to “L” level in the meantime. And although counting continues even if a new count value is written during the counting, counting is started at the new count value if another trigger is applied by the gate input. • Mode 2 (rate generator) The counter output is switched to “H” level by the mode setting. When the gate input is at “H” level, counting is started by the next clock after the count value has been written. And if the gate input is at “L” level, counting is started by using the rising edge of the gate input as a trigger after the count value has been set. An “L” level output pulse appears at the counter output during a single clock duration once every n clock inputs where n is the set count value. If a new count value is written during while counting is in progress, counting is started at the new count value following output of the pulse currently being counted. And if the gate input is switched to “L” level during counting, the counter output is forced to switch to “H” level, the counting being restarted by the rising edge of the gate input. • Mode 3 (square waveform rate generator) The counter output is switched to “H” level by the mode setting. Counting is started in the same way as described for mode 2 above. The repeated square wave output appearing at the counter output contains half the number of counts as the set count value. If the set count value (n) is an odd number, the repeated square wave output consists of only (n+1)/2 clock inputs at “H” level and (n-1)/2 clock inputs at “L” level. If a new count value is written during counting, the new count value is reflected immediately after the change (“H” to “L” or “L” to “H”) in the next counter output to be executed. The counting operation at the gate input is done the same as in mode 2. 11/19 ¡ Semiconductor MSM82C53-2RS/GS/JS • Mode 4 (software trigger strobe) The counter output is switched to “H” level by the mode setting. Counting is started in the same way as described for mode 0. A single “L” pulse equivalent to one clock width is generated at the counter output when the terminal count is reached. This mode differs from 2 in that the “L” level output appears one clock earlier in mode 2, and that pulses are not repeated in mode 4. Counting is stopped when the gate input is switched to “L” level, and restarted from the set count value when switched back to “H” level. • Mode 5 (hardware trigger strobe) The counter output is switched to “H” level by the mode setting. Counting is started, and the gate input used, in the same way as in mode 1. The counter output is identical to the mode 4 output. The various roles of the gate input signals in the above modes are summarized in the following table. Gate Mode 0 "L" Level Falling Edge Rising Edge Counting not possible "H" Level Counting possible (1) Start of counting (2) Retriggering 1 2 (1) Counting not possible (2) Counter output forced to "H" level Start of counting Counting possible 3 (1) Counting not possible (2) Counter output forced to "H" level Start of counting Counting possible 4 5 Counting not possible Counting possible (1) Start of counting (2) Retriggering 12/19 ¡ Semiconductor MSM82C53-2RS/GS/JS Mode 0 CLK WR (n = 4) OUT (GATE="H") (n = 2) 4 3 2 1 0 2 4 4 4 4 3 2 4 3 2 1 0 4 3 2 4 3 4 3 2 1 4 4 3 2 1 4 1 0 WR (n = 4) GATE OUT 1 0 2 1 0 2 1 2 1 2 4 3 2 1 Mode 1 CLK WR (n = 4) GATE OUT GATE OUT (n = 4) Mode 2 CLK WR (n = 4) OUT (GATE="H") (n = 2) 3 GATE OUT (n = 4) Mode 3 CLK WR (n = 4) OUT (GATE="H") GATE OUT (n = 5) 5 (n = 3) 4 4 2 4 2 5 2 4 3 2 2 4 2 4 2 3 2 3 3 5 4 2 5 2 5 4 4 3 2 1 0 3 2 1 0 Mode 4 CLK WR OUT 1 0 (GATE="H") GATE 4 OUT Mode 5 CLK GATE OUT GATE OUT 4 3 2 1 0 4 3 2 1 4 (n = 4) (n = 4) Note: "n" is the value set in the counter. Figures in these diagrams refer to counter values. 13/19 ¡ Semiconductor MSM82C53-2RS/GS/JS Reading of Counter Values All MSM82C53-2 counting is down-counting, the counting being in steps of 2 in mode 3. Counter values can be read during counting by (1) direct reading, and (2) counter latching (“read on the fly”). • Direct reading Counter values can be read by direct reading operations. Since the counter value read according to the timing of the RD and CLK signals is not guaranteed, it is necessary to stop the counting by a gate input signal, or to interrupt the clock input temporarily by an external circuit to ensure that the counter value is correctly read. • Counter latching In this method, the counter value is latched by writing counter latch command, thereby enabling a stable value to be read without effecting the counting in any way at all. An example of a counter latching program is given below. Counter latching executed for counter #1 (Read/Load 2-byte setting) MVI A 0 1 0 0 ¥ ¥ ¥ ¥ Dentotes counter latching OUT n3 Write in control word address (n3) The counter value at this point is latched. IN n1 Reading of the LSB of the counter value latched from counter #1 n1: Counter #1 address MOV B, A IN n1 MOV C, A Reading of MSB from counter #1 Example of Practical Application • MSM82C53-2 used as a 32-bit counter. MSM82C53-2 CLK0 OUT0 CLK1 OUT1 CLK2 OUT2 Use counter #1 and counter #2 Counter #1: mode 0, upper order 16-bit counter value Counter #2: mode 2, lower order 16-bit counter value This setting enables counting up to a maximum of 232. 14/19 ¡ Semiconductor MSM82C53-2RS/GS/JS NOTICE ON REPLACING LOW-SPEED DEVICES WITH HIGH-SPEED DEVICES The conventional low speed devices are replaced by high-speed devices as shown below. When you want to replace your low speed devices with high-speed devices, read the replacement notice given on the next pages. High-speed device (New) Remarks M80C85AH Low-speed device (Old) M80C85A/M80C85A-2 M80C86A-10 M80C86A/M80C86A-2 16bit MPU M80C88A-10 M80C88A/M80C88A-2 8bit MPU M82C84A-2 M82C84A/M82C84A-5 Clock generator M81C55-5 M82C37B-5 M81C55 M82C37A/M82C37A-5 RAM.I/O, timer DMA controller M82C51A-2 M82C51A USART M82C53-2 M82C55A-2 M82C53-5 M82C55A-5 Timer PPI 8bit MPU 15/19 ¡ Semiconductor MSM82C53-2RS/GS/JS Differences between MSM82C53-5 and MSM82C53-2 1) Manufacturing Process These devices use a 3 m Si-Gate CMOS process technology and have the same chip size. 2) Function These devices have the same logics except for changes in AC characteristics listed in (3-2). 3) Electrical Characteristics 3-1) DC Characteristics Parameter Average Operating Current Symbol MSM82C53-5 MSM82C53-2 ICC 5 mA maximum (tCLK=200 ns) 8 mA maximum (tCLK=125 ns) As shown above, the characteristics of these devices are identical under the same test condition. The MSM82C53-2 satisfies the characteristics of the MSM82C53-5. 3-2) AC Characteristics Parameter Symbol MSM82C53-5 MSM82C53-2 Address Hold Time After Write tWA 30 ns minimum 20 ns minimum Data Input Hold Time After Write tWD 30 ns minimum 20 ns minimum Clock Cycle Time tCLK 200 ns minimum 125 ns minimum As shown above, the MSM82C53-2 satisfies the characteristics of the MSM82C53-5. 16/19 ¡ Semiconductor MSM82C53-2RS/GS/JS PACKAGE DIMENSIONS (Unit : mm) DIP24-P-600-2.54 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 3.55 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 17/19 ¡ Semiconductor MSM82C53-2RS/GS/JS (Unit : mm) QFJ28-P-S450-1.27 Spherical surface Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin Cu alloy Solder plating 5 mm or more 1.00 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 18/19 ¡ Semiconductor MSM82C53-2RS/GS/JS (Unit : mm) SSOP32-P-430-1.00-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.60 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 19/19