E2O0020-27-X3 This version: Jan. 1998 MSM82C55A-2RS/GS/VJS Previous version: Aug. 1996 ¡ Semiconductor MSM82C55A-2RS/GS/VJS ¡ Semiconductor CMOS PROGRAMMABLE PERIPHERAL INTERFACE GENERAL DESCRIPTION The MSM82C55A-2 is a programmable universal I/O interface device which operates as high speed and on low power consumption due to 3m silicon gate CMOS technology. It is the best fit as an I/O port in a system which employs the 8-bit parallel processing MSM80C85AH CPU. This device has 24-bit I/O pins equivalent to three 8-bit I/O ports and all inputs/outputs are TTL interface compatible. FEATURES • High speed and low power consumption due to 3m silicon gate CMOS technology • 3 V to 6 V single power supply • Full static operation • Programmable 24-bit I/O ports • Bidirectional bus operation (Port A) • Bit set/reset function (Port C) • TTL compatible • Compatible with 8255A-5 • 40-pin Plastic DIP (DIP40-P-600-2.54): (Product name: MSM82C55A-2RS) • 44-pin Plastic QFJ (QFJ44-P-S650-1.27): (Product name: MSM82C55A-2VJS) • 44-pin Plastic QFP (QFP44-P-910-0.80-2K): (Product name: MSM82C55A-2GS-2K) 1/26 ¡ Semiconductor MSM82C55A-2RS/GS/VJS CIRCUIT CONFIGURATION 8 VCC 8 GND Group A Port A (8) 8 PA0 - PA7 8 Group A Control 8 D 0 - D7 Data Bus Buffer Internal Bus Line 4 8 4 8 RD WR RESET CS Read/ Write Control Logic Group A Port C (High Order 4 Bits) Group B Port C (Low Order 4 Bits) 4 PC4 - PC7 4 PC0 - PC3 Group B Control 8 Group B Port B (8) 8 PB0 - PB7 A0 A1 2/26 ¡ Semiconductor MSM82C55A-2RS/GS/VJS PIN CONFIGURATION (TOP VIEW) 40 pin Plastic DIP 1 2 3 4 RD 5 CS 6 GND 7 A1 8 A0 9 PC7 10 PC6 11 PC5 12 PC4 13 PC0 14 PC1 15 PC2 16 PC3 17 PB0 18 PB1 19 PB2 20 PA3 PA2 PA1 PA0 34 WR 24 23 22 21 PB6 PB5 PB4 PB3 D4 D5 D6 D7 VCC PB7 D0 D1 D2. D3 D4 D5 D6 D7 VCC PB7 40 WR 41 PA7 43 PA5 42 PA6 1 NC 44 PA4 2 PA3 6 RD 5 PA0 39 38 37 36 35 34 33 32 31 30 29 RESET D0 D1 D2. D3 NC D4 D5 D6 D7 VCC PB7 28 PB5 26 PB6 27 PB3 24 PB4 25 PB2 22 NC 23 7 8 9 10 11 12 13 14 15 16 17 PB0 20 PB1 21 CS GND A1 A0 PC7 NC PC6 PC5 PC4 PC0 PC1 4 PA1 3 PA2 44 pin Plastic QFJ PB6 21 NC 22 PB3 18 PB4 19 PB5 20 VCC 17 PB1 15 PB2 16 PA4 PA5 PA6 PA7 WR RESET D0 D1 D2 D3 RESET PC2 18 PC3 19 35 PA7 37 PA5 36 PA6 38 PA4 39 VCC 40 PA3 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 NC 12 PC3 13 PB0 14 CS GND A1 A0 PC7 PC6 PC5 PC4 PC0 PC1 PC2 42 PA1 41 PA2 44 RD 43 PA0 44 pin Plastic QFP 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 3/26 ¡ Semiconductor MSM82C55A-2RS/GS/VJS ABSOLUTE MAXIMUM RATINGS Parameter Rating Conditions Symbol Unit MSM82C55A-2RS MSM82C55A-2GS MSM82C55A-2vJS Supply Voltage VCC Input Voltage VIN Output Voltage Ta = 25°C with respect to GND VOUT TSTG Storage Temperature Power Dissipation — PD Ta = 25°C –0.5 to +7 V –0.5 to VCC +0.5 V –0.5 to VCC +0.5 V –55 to +150 °C 1.0 0.7 1.0 W OPERATING RANGE Symbol Range Unit Supply Voltage Parameter VCC 3 to 6 V Operating Temperature Top –40 to 85 °C RECOMMENDED OPERATING RANGE Parameter Symbol Min. Typ. Max. Unit Supply Voltage VCC 4.5 5 5.5 V Operating Temperature Top –40 +25 +85 °C "L" Input Voltage VIL –0.3 — +0.8 V "H" Input Voltage VIH 2.2 — VCC + 0.3 V DC CHARACTERISTICS Parameter Symbol "L" Output Voltage VOL "H" Output Voltage VOH Conditions MSM82C55A-2 Unit Min. Typ. Max. IOL = 2.5 mA — — 0.4 V IOH = –40 mA 4.2 — — V IOH = –2.5 mA 3.7 — — V Input Leak Current ILI 0 £ VIN £ VCC Output Leak Current ILO 0 £ VOUT £ VCC Supply Current (Standby) ICCS CS ≥ VCC –0.2 V VIH ≥ VCC –0.2 V VIL £ 0.2 V Average Supply Current (Active) ICC I/O Wire Cycle 82C55A-2 ...8 MHzCPU Timing VCC = 4.5 V to 5.5 V Ta = –40°C to +85°C (CL = 0 pF) –1 — 1 mA –10 — 10 mA — 0.1 10 mA — — 8 mA 4/26 ¡ Semiconductor AC CHARACTERISTICS Parameter Setup Time of Address to the Falling Edge of RD MSM82C55A-2RS/GS/VJS (VCC = 4.5 V to 5.5 V, Ta = –40 to +85°C) MSM82C55A-2 Symbol Unit Remarks Min. Max. tAR 20 — ns Hold Time of Address to the Rising Edge of RD tRA 0 — ns RD Pulse Width tRR 100 — ns Delay Time from the Falling Edge of RD to the Output of Defined Data tRD — 120 ns Delay Time from the Rising Edge of RD to the Floating of Data Bus tDF 10 75 ns Time from the Rising Edge of RD or WR to the Next Falling Edge of RD or WR tRV 200 — ns Setup Time of Address before the Falling Edge of WR tAW 0 — ns Hold Time of Address after the Rising Edge of WR tWA 20 — ns WR Pulse Width tWW 150 — ns Setup Time of Bus Data before the Rising Edge of WR tDW 50 — ns Hold Time of Bus Data after the Rising Edge of WR tWD 30 — ns Delay Time from the rising Edge of WR to the Output of Defined Data tWB — 200 ns Setup Time of Port Data before the Falling Edge of RD tIR 20 — ns Hold Time of Port Data after the Rising Edge of RD tHR 10 — ns ACK Pulse Width tAK 100 — ns STB Pulse Width tST 100 — ns Setup Time of Port Data before the rising Edge of STB tPS 20 — ns Hold Time of Port Bus Data after the rising Edge of STB tPH 50 — ns Delay Time from the Falling Edge of ACK to the Output of Defined Data tAD — 150 ns Delay Time from the Rising Edge of ACK to the Floating of Port (Port A in Mode 2) tKD 20 250 ns Delay Time from the Rising Edge of WR to the Falling Edge of OBF tWOB — 150 ns Delay Time from the Falling Edge of ACK to the Rising Edge of OBF tAOB — 150 ns Delay Time from the Falling Edge of STB to the Rising Edge of IBF tSIB — 150 ns Delay Time from the Rising Edge of RD to the Falling Edge of IBF tRIB — 150 ns Delay Time from the the Falling Edge of RD to the Falling Edge of INTR tRIT — 200 ns Delay Time from the Rising Edge of STB to the Rising Edge of INTR tSIT — 150 ns Delay Time from the Rising Edge of ACK to the Rising Edge of INTR tAIT — 150 ns Delay Time from the Falling Edge of WR to the Falling Edge of INTR tWIT — 250 ns Load 150 pF Note: Timing measured at VL = 0.8 V and VH = 2.2 V for both inputs and outputs. 5/26 ¡ Semiconductor MSM82C55A-2RS/GS/VJS TIMING DIAGRAM Basic Input Operation (Mode 0) tRR RD tIR tHR Port Input tAR tRA CS, A1, A0 D7 - D0 tRD tDF Basic Output Operation (Mode 0) tWW WR tDW tWD D 7 - D0 tAW tWA CS, A1, A0 Port Output tWB Strobe Input Operation (Mode 1) tST STB tSIB IBF tSIT tRIB INTR tRIT RD tPH Port Input tPS 6/26 ¡ Semiconductor MSM82C55A-2RS/GS/VJS Strobe Output Operation (Mode 1) WR tAOB OBF tWOB INTR tWIT ACK tAIT tAK Port Output tWB Bidirectional Bus Operation (Mode 2) WR tAOB OBF tWOB INTR tAK ACK STB tST tSIB IBF tAD tPS tKD Port A RD tPH tRIB 7/26 ¡ Semiconductor MSM82C55A-2RS/GS/VJS OUTPUT CHARACTERISTICS (REFERENCE VALUE) 1 Output "H" Voltage (VOH) vs. Output Current (IOH) Output "H" Voltage VOH (V) 5 Ta = –40 to + 85°C VCC = 5.0 V 4 3 2 1 0 0 –1 –2 –3 –4 –5 Output Current IOH (mA) Output "L" Voltage (VOL) vs. Output Current (IOL) 5 Output "L" Voltage VOL (V) 2 4 3 2 VCC = 5.0 V Ta = –40 to +85°C 1 0 0 1 2 3 4 5 Output Current IOL (mA) Note: The direction of flowing into the device is taken as positive for the output current. 8/26 ¡ Semiconductor MSM82C55A-2RS/GS/VJS PIN DESCRIPTION Pin No. D 7 - D0 Item Bidirectional Data Bus Input/Output Function Input and Output These are three-state 8-bit bidirectional buses used to write and read data upon receipt of the WR and RD signals from CPU and also used when control words and bit set/reset data are transferred from CPU to MSM82C55A-2. This signal is used to reset the control register and all internal registers when it is in high level. At this time, ports are all made into the input mode (high impedance status). all port latches are cleared to 0. and all ports groups are set to mode 0. RESET Reset Input Input CS Chip Select Input Input RD Read Input Input When RD is in low level, data is transferred from MSM82C55A-2 to CPU. WR Write Input Input When WR is in low level, data or control words are transferred from CPU to MSM82C55A-2. A0 , A 1 Port Select Input (Address) Input By combination of A0 and A1, either one is selected from among port A, port B, port C, and control register. These pins are usually connected to low order 2 bits of the address bus. PA7 - PA0 Port A Input and Output These are universal 8-bit I/O ports. The direction of inputs/ outputs can be determined by writing a control word. Especially, port A can be used as a bidirectional port when it is set to mode 2. PB7 - PB0 Port B Input and Output These are universal 8-bit I/O ports. The direction of inputs/outputs ports can be determined by writing a control word. These are universal 8-bit I/O ports. The direction of inputs/outputs can be determined by writing a control word as 2 ports with 4 bits each. When port A or port B is used in mode 1 or mode 2 (port A only), they become control pins. Especially, when port C is used as an output port, each bit can set/reset independently. When the CS is in low level, data transmission is enabled with CPU. When it is in high level, the data bus is made into the high impedance status where no write nor read operation is performed. Internal registers hold their previous status, however. PC7 - PC0 Port C Input and Output VCC – – +5V power supply. GND – – GND 9/26 ¡ Semiconductor MSM82C55A-2RS/GS/VJS BASIC FUNCTIONAL DESCRIPTION Group A and Group B When setting a mode to a port having 24 bits, set it by dividing it into two groups of 12 bits each. Group A: Port A (8 bits) and high order 4 bits of port C (PC7~PC4) Group B: Port B (8 bits) and low order 4 bits of port C (PC3~PC0) Mode 0, 1, 2 There are 3 types of modes to be set by grouping as follows: Mode 0: Basic input operation/output operation (Available for both groups A and B) Mode 1: Strobe input operation/output operation (Available for both groups A and B) Mode 2: Bidirectional bus operation (Available for group A only) When used in mode 1 or mode 2, however, port C has bits to be defined as ports for control signal for operation ports (port A for group A and port B for group B) of their respective groups. Port A, B, C The internal structure of 3 ports is as follows: Port A: One 8-bit data output latch/buffer and one 8-bit data input latch Port B: One 8-bit data input/output latch/buffer and one 8-bit data input buffer Port C: One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input) Single bit set/reset function for port C When port C is defined as an output port, it is possible to set (to turn to high level) or reset (to turn to low level) any one of 8 bits individually without affecting other bits. 10/26 ¡ Semiconductor MSM82C55A-2RS/GS/VJS OPERATIONAL DESCRIPTION Control Logic Operations by addresses and control signals, e.g., read and write, etc. are as shown in the table below: Operaiton Input Output Control Others RD A0 CS 0 0 0 1 0 Port A Æ Data Bus 0 1 1 0 0 0 1 1 0 0 Port B Æ Data Bus 0 0 0 0 1 Data Bus Æ Port A A1 WR Operation Port C Æ Data Bus 0 1 0 0 1 Data Bus Æ Port B 1 0 0 0 1 1 1 0 0 1 Data Bus Æ Port C Data Bus Æ Control Register 1 1 0 1 0 Illegal Condition ¥ ¥ 1 ¥ ¥ Data bus is in the high impedance status. Setting of Control Word The control register is composed of 7-bit latch circuit and 1-bit flag as shown below. Group A Control Bits D7 D6 D5 D4 Group B Control Bits D3 D2 D1 D0 Definition of input/ output of low order 4 bits of port C. Definition of input/ output of 8 bits of port B. Mode definition of group B. Definition of input/ output of high order 4 bits of port C. Definition of input/ output of 8 bits of port A. 0 = Output 1 = Input 0 = Output 1 = Input 0 = Mode 0 1 = Mode 1 0 = Output 1 = Input 0 = Output 1 = Input Mode definition of group A. Control word Identification flag Be sure to set 1 for the control word to define a mode and input/output. When set to 0, it becomes the control word for bit set/ reset. D6 D5 0 0 0 1 1 ¥ Mode Mode 0 Mode 1 Mode 2 11/26 ¡ Semiconductor MSM82C55A-2RS/GS/VJS Precaution for Mode Selection The output registers for ports A and C are cleared to f each time data is written in the command register and the mode is changed, but the port B state is undefined. Bit Set/Reset Function When port C is defined as output port, it is possible to set (set output to 1) or reset (set output to 0) any one of 8 bits without affecting other bits as shown below. D7 D6 D5 D4 D3 D2 D1 D0 Definition of set/reset for a desired bit. 0 = Reset 1 = Set Definition of bit wanted to be set or reset. Dont's Care Control word Identification flag Be sure to set to 0 for bit set/reset When set to 1, it becomes the control word to define a mode and input/output. Port C PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 D3 D2 D1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Interrupt Control Function When the MSM82C55A-2 is used in mode 1 or mode 2, the interrupt signal for the CPU is provided. The interrupt request signal is output from port C. When the internal flip-flop INTE is set beforehand at this time, the desired interrupt request signal is output. When it is reset beforehand, however, the interrupt request signal is not output. The set/reset of the internal flip-flop is made by the bit set/reset operation for port C virtually. Bit set Æ INTE is set Æ Interrupt allowed Bit reset Æ INTE is reset Æ Interrupt inhibited Operational Description by Mode 1. Mode 0 (Basic input/output operation) Mode 0 makes the MSM82C55A-2 operate as a basic input port or output port. No control signals such as interrupt request, etc. are required in this mode. All 24 bits can be used as two-8-bit ports and two 4-bit ports. Sixteen combinations are then possible for inputs/ outputs. The inputs are not latched, but the outputs are. 12/26 ¡ Semiconductor MSM82C55A-2RS/GS/VJS Control Word Group A Type D7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Group B Port A High Order 4 Bits of Port C Port B Low Order 4 Bits of Port C Output 1 1 0 0 0 0 0 0 0 Output Output Output 2 1 0 0 0 0 0 0 1 Output Output Output Input 3 1 0 0 0 0 0 1 0 Output Output Input Output 4 1 0 0 0 0 0 1 1 Output Output Input Input 5 1 0 0 0 1 0 0 0 Output Input Output Output 6 1 0 0 0 1 0 0 1 Output Input Output Input 7 1 0 0 0 1 0 1 0 Output Input Input Ouput 8 1 0 0 0 1 0 1 1 Output Input Input Input 9 1 0 0 1 0 0 0 0 Input Output Output Output 10 1 0 0 1 0 0 0 1 Input Output Output Input 11 1 0 0 1 0 0 1 0 Input Output Input Output 12 1 0 0 1 0 0 1 1 Input Output Input Input 13 1 0 0 1 1 0 0 0 Input Input Output Output 14 1 0 0 1 1 0 0 1 Input Input Output Input 15 1 0 0 1 1 0 1 0 Input Input Input Output 16 1 0 0 1 1 0 1 1 Input Input Input Input Notes: When used in mode 0 for both groups A and B 2. Mode 1 (Strobe input/output operation) In mode 1, the strobe, interrupt and other control signals are used when input/output operations are made from a specified port. This mode is available for both groups A and B. In group A at this time, port A is used as the data line and port C as the control signal. Following is a description of the input operation in mode 1. STB (Strobe input) When this signal is low level, the data output from terminal to port is fetched into the internal latch of the port. This can be made independent from the CPU, and the data is not output to the data bus until the RD signal arrives from the CPU. IBF (Input buffer full flag output) This is the response signal for the STB. This signal when turned to high level indicates that data is fetched into the input latch. This signal turns to high level at the falling edge of STB and to low level at the rising edge of RD. INTR (Interrupt request output) This is the interrupt request signal for the CPU of the data fetched into the input latch. It is indicated by high level only when the internal INTE flip-flop is set. This signal turns to high level at the rising edge of the STB (IBF = 1 at this time) and low level at the falling edge of the RD when the INTE is set. INTE A of group A is set when the bit for PC4 is set, while INTE B of group B is set when the bit for PC2 is set. Following is a description of the output operation of mode 1. 13/26 ¡ Semiconductor MSM82C55A-2RS/GS/VJS OBF (Output buffer full flag output) This signal when turned to low level indicates that data is written to the specified port upon receipt of the WR signal from the CPU. This signal turns to low level at the rising edge of the WR and high level at the falling edge of the ACK. ACK (Acknowledge input) This signal when turned to low level indicates that the terminal has received data. INTR (Interrupt request output) This is the signal used to interrupt the CPU when a terminal receives data from the CPU via the MSM82C55A-5. It indicates the occurrence of the interrupt in high level only when the internal INTE flip-flop is set. This signal turns to high level at the rising edge of the ACK (OBF = 1 at this time) and low level at the falling edge of WR when the INTE B is set. INTE A of group A is set when the bit for PC6 is set, while INTE B of group B is set when the bit for PC2 is set. Mode 1 Input (Group A) (Group B) 8 INTEA 8 - PB7 - PA7 INTEB PA0 PB0 PC4 STBA PC2 STBB PC5 IBFA PC1 IBFB PC3 INTRA PC0 INTRB RD RD Note: Although belonging to group B, PC3 operates as the control signal of group A functionally. Mode 1 Output (Group A) (Group B) 8 INTEA 8 - PB7 - PA7 INTEB PA0 PB0 PC7 OBFA PC1 OBFB PC6 ACKA PC2 ACKB PC0 INTRB WR WR PC3 INTRA 14/26 ¡ Semiconductor MSM82C55A-2RS/GS/VJS Port C Function Allocation in Mode 1 Combination of Input/Output Port C Group A: Input Group B: Input PC0 Group A: Input Group A: Output Group B: Output Group B: Input INTRB INTRB Group A: Output Group B: Output INTRB INTRB OBFB PC1 IBFB OBFB IBFB PC2 STBB ACKB STBB ACKB PC3 INTRA INTRA INTRA INTRA PC4 STBA STBA I/O I/O PC5 IBFA IBFA I/O I/O PC6 I/O I/O ACKA ACKA PC7 I/O I/O OBFA OBFA Note: I/O is a bit not used as the control signal, but it is available as a port of mode 0. Examples of the relation between the control words and pins when used in mode 1 are shown below: (a) When group A is mode 1 output and group B is mode 1 input. Control Word D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 1/0 1 1 ¥ Selection of I/O of PC4 and PC5 when not defined as a control pin. 1 = Input 0 = Output As all of PC0 - PC3 bits become a control pin in this case, this bit is "Don't Care". 8 WR RD PA7 - PA0 PC7 PC6 PC3 PC4, PC5 2 PB7 - PB0 PC2 PC1 PC0 OBFA ACKA INTRA I/O 8 Group A: Mode 1 Output Group B: Mode 1 Input STBB IBFB INTRB 15/26 ¡ Semiconductor MSM82C55A-2RS/GS/VJS (b) When group A is mode 1 input and group B is mode 1 output. D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 1 1/0 1 0 ¥ Selection of I/O of PC6 and PC7 when not defined as a control pin. 1 = Input 0 = Output RD WR PA7 - PA0 PC4 PC5 PC3 PC6, PC7 PB7 - PB0 PC1 PC2 PC0 8 2 STBA IBFA INTRA I/O 8 Group A: Mode 1 Input Group B: Mode 1 Output OBFB ACKB INTRB 3. Mode 2 (Strobe bidirectional bus I/O operation) In mode 2, it is possible to transfer data in 2 directions through a single 8-bit port. This operation is akin to a combination between input and output operations. Port C waits for the control signal in this case, too. Mode 2 is available only for group A, however. Next, a description is made on mode 2. OBF (Output buffer full flag output) This signal when turned to low level indicates that data has been written to the internal output latch upon receipt of the WR signal from the CPU. At this time, port A is still in the high impedance status and the data is not yet output to the outside. This signal turns to low level at the rising edge of the WR and high level at the falling edge of the ACK. ACK (Acknowledge input) When a low level signal is input to this pin, the high impedance status of port A is cleared, the buffer is enabled, and the data written to the internal output latch is output to port A. When the input returns to high level, port A is made into the high impedance status. STB (Strobe input) When this signal turns to low level, the data output to the port from the pin is fetched into the internal input latch. The data is output to the data bus upon receipt of the RD signal from the CPU, but it remains in the high impedance status until then. IBF (Input buffer full flag output) This signal when turned to high level indicates that data from the pin has been fetched into the input latch. This signal turns to high level at the falling edge of the STB and low level at the rising edge of the RD. 16/26 ¡ Semiconductor MSM82C55A-2RS/GS/VJS INTR (Interrupt request output) This signal is used to interrupt the CPU and its operation in the same as in mode 1. There are two INTE flip-flops internally available for input and output to select either interrupt of input or output operation. The INTE1 is used to control the interrupt request for output operation and it can be reset by the bit set for PC6. INTE2 is used to control the interrupt request for the input operation and it can be set by the bit set for PC4. Mode 2 I/O Operation PC3 - PA7 INTRA 8 PA0 WR RD PC7 OBFA INTE1 PC6 ACKA INTE2 PC4 STBA PC5 IBFA Port C Function Allocation in Mode 2 Port C Function PC0 PC1 Confirmed to the Group B Mode PC2 PC3 PC4 INTRA STBA PC5 IBFA PC6 ACKA PC7 OBFA Following is an example of the relation between the control word and the pin when used in mode 2. When input in mode 2 for group A and in mode 1 for group B. 17/26 ¡ Semiconductor MSM82C55A-2RS/GS/VJS D7 D6 D5 D4 D3 D2 D1 D0 1 1 ¥ ¥ ¥ 1 1 ¥ As all of 8 bits of port C become control pins in this case, D3 and D0 bits are treated as "Don't Care". No I/O specification is required for mode 2, since it is a bidirectional operation. This bit is therefore treated as "Don't Care". When group A is set to mode 2, this bit is treated as "Don't Care". PC3 PA7 - PA0 PC7 PC6 PC4 PC5 RD WR PB7 - PB0 PC2 PC1 PC0 INTRA 8 OBFA ACKA STBA IBFA Group A: Mode 2 Group B: Mode 1 Input 8 STBB IBFB INTRB 18/26 ¡ Semiconductor MSM82C55A-2RS/GS/VJS 4. When Group A is Different in Mode from Group B Group A and group B can be used by setting them in different modes each other at the same time. When either group is set to mode 1 or mode 2, it is possible to set the one not defined as a control pin in port C to both input and output as port which operates in mode 0 at the 3rd and 0th bits of the control word. (Mode combinations that define no control bit at port C) PC7 PC6 PC5 Port C PC4 PC3 Mode 0 I/O I/O IBFA STBA INTRA I/O I/O I/O Mode 0 Output Mode 0 OBFA ACKA I/O I/O INTRA I/O I/O I/O 3 Mode 0 Mode 1 Input I/O I/O I/O I/O I/O STBB IBFB INTRB 4 Mode 0 Mode 1 Output I/O I/O I/O I/O I/O ACKB OBFB INTRB 5 Mode 1 Input Mode 1 Input I/O I/O IBFA STBA INTRA STBB IBFB INTRB 6 Mode 1 Input Mode 1 Output I/O I/O IBFA STBA INTRA ACKB OBFB INTRB 7 Mode 1 Output Mode 1 Input OBFA ACKA I/O I/O INTRA STBB IBFB INTRB 8 Mode 1 Output OBFA ACKA I/O I/O INTRA ACKB OBFB INTRB 9 Mode 2 Mode 1 Output Mode 0 OBFA ACKA IBFA STBA INTRA I/O I/O I/O Group A Group B 1 Mode 1 input 2 Controlled at the 3rd bit (D3) of the Control Word PC2 PC1 PC0 Controlled at the 0th bit (D0) of the Control Word When the I/O bit is set to input in this case, it is possible to access data by the normal port C read operation. When set to output, PC7-PC4 bits can be accessed by the bit set/reset function only. Meanwhile, 3 bits from PC2 to PC0 can be accessed by normal write operation. The bit set/reset function can be used for all of PC3-PC0 bits. Note that the status of port C varies according to the combination of modes like this. 19/26 ¡ Semiconductor MSM82C55A-2RS/GS/VJS 5. Port C Status Read When port C is used for the control signal, that is, in either mode 1 or mode 2, each control signal and bus status signal can be read out by reading the content of port C. The status read out is as follows: D7 D6 Status Read on the Data Bus D5 D4 D3 D2 Mode 0 I/O I/O IBFA INTEA INTRA Mode 1 Output Mode 0 OBFA INTEA I/O I/O 3 Mode 0 Mode 1 Input I/O I/O I/O 4 Mode 0 Mode 1 Output I/O I/O 5 Mode 1 Input Mode 1 Input I/O 6 Mode 1 Input Mode 1 Output 7 Mode 1 Output Mode 1 Input 8 Mode 1 Output 9 Mode 2 10 11 Group A Group B 1 Mode 1 Input 2 D1 D0 I/O I/O I/O INTRA I/O I/O I/O I/O I/O INTEB IBFB INTRB I/O I/O I/O INTEB OBFB INTRB I/O IBFA INTEA INTRA INTEB IBFB INTRB I/O I/O IBFA INTEA INTRA INTEB OBFB INTRB OBFA INTEA I/O I/O INTRA INTEB IBFB INTRB Mode 1 Output Mode 0 OBFA INTEA I/O I/O INTRA INTEB OBFB INTRB OBFA INTE1 IBFA INTE2 INTRA I/O I/O I/O Mode 2 Mode 1 Input OBFA INTE1 IBFA INTE2 INTRA INTEB IBFB INTRB Mode 2 Mode 1 Output OBFA INTE1 IBFA INTE2 INTRA INTEB OBFB INTRB 6. Reset of MSM82C55A-2 Be sure to keep the RESET signal at power ON in the high level at least for 50 ms. Subsequently, it becomes the input mode at a high level pulse above 500 ns. Note: Comparison of MSM82C55A-5 and MSM82C55A-2 MSM82C55A-5 After a write command is executed to the command register, the internal latch is cleared in PORTA PORTC. For instance, 00H is output at the beginning of a write command when the output port is assigned. However, if PORTB is not cleared at this time, PORTB is unstable. In other words, PORTB only outputs ineffective data (unstable value according to the device) during the period from after a write command is executed till the first data is written to PORTB. MSM82C55A-2 After a write command is executed to the command register, the internal latch is cleared in All Ports (PORTA, PORTB, PORTC). 00H is output at the beginning of a write command when the output port is assigned. 20/26 ¡ Semiconductor MSM82C55A-2RS/GS/VJS NOTICE ON REPLACING LOW-SPEED DEVICES WITH HIGH-SPEED DEVICES The conventional low speed devices are replaced by high-speed devices as shown below. When you want to replace your low speed devices with high-speed devices, read the replacement notice given on the next pages. High-speed device (New) Remarks M80C85AH Low-speed device (Old) M80C85A/M80C85A-2 M80C86A-10 M80C86A/M80C86A-2 16bit MPU M80C88A-10 M80C88A/M80C88A-2 8bit MPU M82C84A-2 M82C84A/M82C84A-5 Clock generator M81C55-5 M82C37B-5 M81C55 M82C37A/M82C37A-5 RAM.I/O, timer DMA controller M82C51A-2 M82C51A USART M82C53-2 M82C55A-2 M82C53-5 M82C55A-5 Timer PPI 8bit MPU 21/26 ¡ Semiconductor MSM82C55A-2RS/GS/VJS Differences between MSM82C55A-5 and MSM82C55A-2 1) Manufacturing Process These devices use a 3 m Si-Gate CMOS process technology. The MSM82C55A-2 is about 7% smaller in chip size than the MSM82C55A-5 as the MSM82C55A2 changed its output characteristics. 2) Function Item Internal latch during writing into the command register MSM82C55A-5 Only ports A and C are cleared. Port B is not cleared. MSM82C55A-2 All ports are cleared. The above function has been improved to remove bugs and other logics are not different between the two devices. 3) Electrical Characteristics 3-1) DC Characteristics Parameter Symbol MSM82C55A-5 MSM82C55A-2 ''L'' Output Voltage VOL 0.45 V (IOL = +2.5 mA) 0.40 V (IOL = +2.5 mA) ''H'' Output Voltage VOH 2.4 V (IOH = -400 mA) 3.7 V (IOH = -2.5 mA) Average Operating Current ICC 5 mA maximum (I/O Cycle = 1 ms) 8 mA maximum (I/O Cycle = 375 ns) As shown above, the DC characteristics of the MSM82C55A-2 satisfies the DC characteristics of the MSM82C55A-5. 3-2) AC Characteristics Parameter Symbol MSM82C55A-5 MSM82C55A-2 Address Hold Time for RD Rising tRA 20 ns minimum 0 ns minimum RD Pulse Width tRR 300 ns minimum 100 ns minimum Difined Data Output Delay Time From RD Falling tRD 200 ns maximum 120 ns maximum Data Floating Delay Time From RD Rising tRF 100 ns maximum 75 ns maximum RD/WR Recovery Time tRV 850 ns minimum 200 ns minimum 22/26 ¡ Semiconductor Parameter MSM82C55A-2RS/GS/VJS Symbol MSM82C55A-5 MSM82C55A-2 Address Hold Time for WR Rising tWA 30 ns minimum 20 ns minimum WR Pulse Width tWW 300 ns minimum 150 ns minimum Data Setup Time for WR Rising tDW 1000 ns minimum 50 ns minimum Data Hold Time for WR Rising tWD 40 ns minimum 30 ns minimum Defined Data Output Time From WR Rising tWB 350 ns maximum 200 ns maximum Port Data Hold Time for RD Rising tHR 20 ns minimum 10 ns minimum ACK Pulse Width tAK 300 ns minimum 100 ns minimum STB Pulse Width tST 300 ns minimum 100 ns minimum Port Data Hold Time for STB Falling tPH 180 ns minimum 50 ns minimum ACK Falling to Defined Data Output tAD 300 ns maximum 150 ns maximum WR Falling to OBF Falling Delay Time tWOB 650 ns maximum 150 ns maximum ACK Falling to OBF Rising Delay Time tAOB 350 ns maximum 150 ns maximum STB Falling to IBF Rising Delay Time tSIB 300 ns maximum 150 ns maximum RD Rising to IBF Falling Delay Time tRIB 300 ns maximum 150 ns maximum RD Falling to INTR Falling Delay Time tRIT 400 ns maximum 200 ns maximum STB Rising to INTR Rising Delay Time tSIT 300 ns maximum 150 ns maximum ACK Rising to INTR Rising Delay Time tAIT 350 ns maximum 150 ns maximum WR Falling to INTR Falling Delay Time tWIT 850 ns minimum 250 ns maximum As shown above, the MSM82C55A-2 satisfies the characteristics of the MSM82C55A-5. 23/26 ¡ Semiconductor MSM82C55A-2RS/GS/VJS PACKAGE DIMENSIONS (Unit : mm) DIP40-P-600-2.54 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 6.10 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 24/26 ¡ Semiconductor MSM82C55A-2RS/GS/VJS (Unit : mm) QFJ44-P-S650-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin Cu alloy Solder plating 5 mm or more 2.00 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 25/26 ¡ Semiconductor MSM82C55A-2RS/GS/VJS (Unit : mm) QFP44-P-910-0.80-2K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Epoxy resin 42 alloy Solder plating 5 mm or more Package weight (g) 0.41 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 26/26