24AA32A 32K 1.8V I2C Serial EEPROM FEATURES PACKAGE TYPE • Single supply with operation down to 1.8V - Maximum write current 3 mA at 6.0V - Standby current 1 µA max at 1.8V • 2-wire serial interface bus, I2C compatible • 100 kHz (1.8V) and 400 kHz (5V) compatibility • Self-timed ERASE and WRITE cycles • Power on/off data protection circuitry • Hardware write protect • 1,000,000 Erase/Write cycles guaranteed • 32 byte page or byte write modes available • Schmitt trigger inputs for noise suppression • Output slope control to eliminate ground bounce • 2 ms typical write cycle time, byte or page • Up to eight devices may be connected to the same bus for up to 256K bits total memory • Electrostatic discharge protection > 4000V • Data retention > 200 years • 8-pin PDIP and SOIC packages • Temperature ranges - Commercial (C): 0°C to +70°C PDIP 1 8 Vcc A1 2 7 WP A2 3 6 SCL Vss 4 5 SDA A0 1 8 Vcc A1 2 7 WP A2 3 6 SCL Vss 4 5 SDA 24AA32A A0 SOIC The Microchip Technology Inc. 24AA32A is a 4K x 8 (32K bit) Serial Electrically Erasable PROM capable of operation across a broad voltage range (1.8V to 6.0V). It has been developed for advanced, low power applications such as personal communications or data acquisition. The 24AA32A also has a page-write capability of up to 32 bytes of data. The 24AA32A is capable of both random and sequential reads up to the 32K boundary. Functional address lines allow up to eight 24AA32A devices on the same bus, for up to 256K bits address space. Advanced CMOS technology and broad voltage range make this device ideal for low-power/low-voltage, nonvolatile code and data applications. The 24AA32A is available in the standard 8-pin plastic DIP and both 150 mil and 200 mil SOIC packages. 24AA32A DESCRIPTION BLOCK DIAGRAM A0..A2 WP I/O CONTROL LOGIC WP MEMORY CONTROL LOGIC HV GENERATOR XDEC EEPROM ARRAY PAGE LATCHES I/O SCL YDEC SDA VCC VSS SENSE AMP R/W CONTROL I2C is a trademark of Philips Corporation. 1996 Microchip Technology Inc. Preliminary This document was created with FrameMaker 4 0 4 DS21162B-page 1 24AA32A 1.0 ELECTRICAL CHARACTERISTICS 1.1 Maximum Ratings* TABLE 1-1: VCC...................................................................................7.0V All inputs and outputs w.r.t. VSS ............... -0.6V to VCC +1.0V Storage temperature ..................................... -65˚C to +150˚C Ambient temp. with power applied ................ -65˚C to +125˚C Soldering temperature of leads (10 seconds) ............. +300˚C ESD protection on all pins ..................................................≥ 4 kV *Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-2: PIN FUNCTION TABLE Name Function A0..A2 VSS SDA SCL WP VCC User Configurable Chip Selects Ground Serial Address/Data I/O Serial Clock Write Protect Input +1.8V to 6.0V Power Supply DC CHARACTERISTICS Vcc = +1.8V to 6.0V Commercial (C) Tamb = 0°C to +70°C Parameter Symbol Min High level input voltage VIH Low level input voltage VIL Hysteresis of Schmitt Trigger inputs VHYS Low level output voltage Typ Max Units Conditions .7 VCC — V — .3 Vcc V .05 VCC — V VOL — .40 V IOL = 3.0 mA ILI -10 10 µA VIN = .1V to VCC ILO -10 10 µA VOUT = .1V to VCC CIN,COUT — 10 pF VCC = 5.0V (Note) Tamb = 25˚C, Fc = 1 MHz A0, A1, A2, SCL , SDA and WP pins: Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Standby current ICC Write — 3 mA VCC = 6.0V ICC Read — 0.5 mA VCC = 6.0V, SCL = 400kHz ICCS — 1 ICCS Note: (Note) 5 µA SCL = SDA = VCC = 5.5V 1 µA VCC = 1.8V (Note) This parameter is periodically sampled and not 100% tested. FIGURE 1-1: BUS TIMING START/STOP VHYS SCL THD:STA TSU:STA TSU:STO SDA START DS21162B-page 2 STOP Preliminary 1996 Microchip Technology Inc. 24AA32A TABLE 1-3: AC CHARACTERISTICS Parameter Vcc = 1.8-6.0V STD. MODE Symbol Vcc = 4.5-6.0V FAST MODE Min Max Min Max Units Remarks Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time START condition hold time FCLK THIGH TLOW TR TF THD:STA — 4000 4700 — — 4000 100 — — 1000 300 — — 600 1300 — — 600 400 — — 300 300 — kHz ns ns ns ns ns START condition setup time Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time TSU:STA 4700 — 600 — ns THD:DAT TSU:DAT TSU:STO TAA TBUF 0 250 4000 — 4700 — — — 3500 — 0 100 600 — 1300 — — — 900 — ns ns ns ns ns TOF — 250 250 ns TSP — 50 20 +0.1CB — (Note 2) Time the bus must be free before a new transmission can start (Note 1), CB ≤ 100 pF 50 ns (Note 3) TWR — — 1M 5 — — 1M 5 — ms cycles Output fall time from VIH min to VIL max Input filter spike suppression (SDA and SCL pins) Write cycle time Endurance (Note 1) (Note 1) After this period the first clock pulse is generated Only relevant for repeated START condition Byte or Page Mode 25°C, Vcc = 5.0V, Block Mode (Note 4) Note 1: Not 100% tested. CB = Total capacitance of one bus line in pF. 2: As a trasmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to Schmitt trigger inputs which provide improved noise and spike suppression. This eliminates the need for a Ti specification for standard operation. 4: This application is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website. FIGURE 1-2: BUS TIMING DATA TR TF THIGH TLOW SCL TSU:STA SDA IN THD:DAT TSU:DAT TSU:STO THD:STA TSP TAA THD:STA TAA TBUF SDA OUT 1996 Microchip Technology Inc. Preliminary DS21162B-page 3 24AA32A 2.0 FUNCTIONAL DESCRIPTION 3.4 The 24AA32A supports a Bi-directional two-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus must be controlled by a master device which generates the Serial Clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24AA32A works as slave. Both master and slave can operate as transmitter or receiver but the master device determines which mode is activated. 3.0 BUS CHARACTERISTICS Data Valid (D) The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device. The following bus protocol has been defined: 3.5 • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Each receiving device, when addressed, is obliged to generate an acknowledge signal after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. Note: Accordingly, the following bus conditions have been defined (Figure 3-1). 3.1 Bus not Busy (A) Both data and clock lines remain HIGH. 3.2 Start Data Transfer (B) A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition. 3.3 Stop Data Transfer (C) Acknowledge The 24AA32A does not generate any acknowledge bits if an internal programming cycle is in progress. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by NOT generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24AA32A) will leave the data line HIGH to enable the master to generate the STOP condition. A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition. FIGURE 3-1: (A) DATA TRANSFER SEQUENCE ON THE SERIAL BUS (B) (D) (D) START CONDITION ADDRESS OR ACKNOWLEDGE VALID (C) (A) SCL SDA DS21162B-page 4 DATA ALLOWED TO CHANGE Preliminary STOP CONDITION 1996 Microchip Technology Inc. 24AA32A 3.6 Device Addressing Following the start condition, the 24AA32A monitors the SDA bus checking the device type identifier being transmitted. Upon receiving a 1010 code and appropriate device select bits, the slave device outputs an acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24AA32A will select a read or write operation. A control byte is the first byte received following the start condition from the master device. The control byte consists of a 4-bit control code; for the 24AA32A this is set as 1010 binary for read and write (R/W) operations. The next three bits of the control byte are the device select bits (A2, A1, A0). They are used by the master device to select which of the eight devices are to be accessed. These bits are in effect the three most significant bits of the word address. The last bit of the control byte defines the operation to be performed. When set to a one a read operation is selected, and when set to a zero a write operation is selected. The next two bytes received define the address of the first data byte (Figure 3-3). Because only A11...A0 are used, the upper four address bits must be zeros. The most significant bit of the most significant byte of the address is transferred first. FIGURE 3-2: 0 1 FIGURE 3-3: R/W 0 A2 A1 R/W Read Write 1010 1010 Device Address Device Address 1 0 A A0 ADDRESS SEQUENCE BIT ASSIGNMENTS ADDRESS BYTE 1 CONTROL BYTE 0 Device Select READ/WRITE SLAVE ADDRESS 1 Control Code CONTROL BYTE ALLOCATION START 1 Operation 1 SLAVE ADDRESS 0 A 2 A 1 A 0 R/W 0 0 0 0 A 11 A 10 A 9 ADDRESS BYTE 0 A 8 A 7 • • • • • • A 0 DEVICE SELECT BUS 1996 Microchip Technology Inc. Preliminary DS21162B-page 5 24AA32A 4.0 WRITE OPERATION 4.2 4.1 Byte Write The write control byte, word address and the first data byte are transmitted to the 24AA32A in the same way as in a byte write. But instead of generating a stop condition, the master transmits up to 32 bytes which are temporarily stored in the on-chip page buffer and will be written into memory after the master has transmitted a stop condition. After receipt of each word, the five lower address pointer bits are internally incremented by one. If the master should transmit more than 32 bytes prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received, an internal write cycle will begin. (Figure 4-2). Following the start condition from the master, the control code (four bits), the device select (three bits), and the R/W bit which is a logic low are clocked onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the high-order byte of the word address and will be written into the address pointer of the 24AA32A. The next byte is the least significant address byte. After receiving another acknowledge signal from the 24AA32A the master device will transmit the data word to be written into the addressed memory location. Page Write The 24AA32A acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and during this time the 24AA32A will not generate acknowledge signals (Figure 4-1). FIGURE 4-1: BYTE WRITE BUS ACTIVITY MASTER S T A R T SDA LINE A C K CONTROL BYTE A C K ADDRESS HIGH BYTE SDA LINE DS21162B-page 6 DATA A C K A C K PAGE WRITE S BUS ACTIVITY T A MASTER R T BUS ACTIVITY S T O P 0 0 0 0 BUS ACTIVITY FIGURE 4-2: ADDRESS LOW BYTE ADDRESS HIGH BYTE CONTROL BYTE ADDRESS LOW BYTE DATA BYTE 0 S T O P DATA BYTE 31 0 0 0 0 A C K A C K Preliminary A C K A C K 1996 Microchip Technology Inc. 24AA32A 5.0 ACKNOWLEDGE POLLING 6.0 Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. Acknowledge Polling (ACK) can be initiated immediately. This involves the master sending a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 5-1 for flow diagram. FIGURE 5-1: ACKNOWLEDGE POLLING FLOW Send Write Command Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read, and sequential read. 6.1 Current Address Read The 24AA32A contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n (n is any legal address), the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to one, the 24AA32A issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24AA32A discontinues transmission (Figure 6-1). 6.2 Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24AA32A as part of a write operation (R/W bit set to zero). After the word address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W bit set to a one. The 24AA32A will then issue an acknowledge and transmit the 8-bit data word. The master will not acknowledge the transfer but does generate a stop condition which causes the 24AA32A to discontinue transmission (Figure 6-2). Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? READ OPERATION NO YES Next Operation FIGURE 6-1: CURRENT ADDRESS READ BUS ACTIVITY MASTER S T A R T SDA LINE S BUS ACTIVITY CONTROL BYTE S T O P DATA BYTE P A C K N O A C K 1996 Microchip Technology Inc. Preliminary DS21162B-page 7 24AA32A 6.3 Contiguous Addressing Across Multiple Devices 6.4 Sequential Read Sequential reads are initiated in the same way as a random read except that after the 24AA32A transmits the first data byte, the master issues an acknowledge as opposed to the stop condition used in a random read. This acknowledge directs the 24AA32A to transmit the next sequentially addressed 8-bit word (Figure 6-3). Following the final byte transmitted to the master, the master will NOT generate an acknowledge but will generate a stop condition. The device select bits A2, A1, A0 can be used to expand the contiguous address space for up to 256K bits by adding up to eight 24AA32A's on the same bus. In this case, software can use A0 of the control byte as address bit A12, A1 as address bit A13, and A2 as address bit A14. To provide sequential reads the 24AA32A contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation. The internal address pointer will automatically roll over from address 0FFF to address 000 if the master acknowledges the byte received from the array address 0FFF. FIGURE 6-2: RANDOM READ S T BUS ACTIVITY A MASTER R T CONTROL BYTE ADDRESS HIGH BYTE S T A R T ADDRESS LOW BYTE CONTROL BYTE S T O P DATA BYTE 0 0 0 0 SDA LINE A C K A C K BUS ACTIVITY A C K A C K N O A C K FIGURE 6-3: SEQUENTIAL READ BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY CONTROL BYTE A C K DATA n DATA n + 1 A C K DATA n + 2 A C K S T O P DATA n + x A C K N O A C K DS21162B-page 8 Preliminary 1996 Microchip Technology Inc. 24AA32A 7.0 PIN DESCRIPTIONS 8.0 7.1 A0, A1, A2 Chip Address Inputs The SCL and SDA inputs have filter circuits which suppress noise spikes to ensure proper device operation even on a noisy bus. All I/O lines incorporate Schmitt triggers for 400 kHz (Fast Mode) compatibility. The A0..A2 inputs are used by the 24AA32A for multiple device operation and conform to the 2-wire bus standard. The levels applied to these pins define the address block occupied by the device in the address map. A particular device is selected by transmitting the corresponding bits (A2, A1, A0) in the control byte (Figure 3-3). 7.2 SDA Serial Address/Data Input/Output This is a Bi-directional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pullup resistor to VCC (typical 10KΩ for 100 kHz, 1KΩ for 400 kHz) 9.0 NOISE PROTECTION POWER MANAGEMENT This design incorporates a power standby mode when the device is not in use and automatically powers off after the normal termination of any operation when a stop bit is received and all internal functions are complete. This includes any error conditions, i.e., not receiving an acknowledge or stop condition per the 2-wire bus specification. The device also incorporates VDD monitor circuitry to prevent inadvertent writes (data corruption) during low-voltage conditions. The VDD monitor circuitry is powered off when the device is in standby mode in order to further reduce power consumption. For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL HIGH are reserved for indicating the START and STOP conditions. 7.3 SCL Serial Clock This input is used to synchronize the data transfer from and to the device. 7.4 WP This pin must be connected to either VSS or VCC. If tied to VSS, normal memory operation is enabled (read/write the entire memory 000-FFF). If tied to VCC, WRITE operations are inhibited. The entire memory will be write-protected. Read operations are not affected. 1996 Microchip Technology Inc. Preliminary DS21162B-page 9 24AA32A NOTES: DS21162B-page 10 Preliminary 1996 Microchip Technology Inc. 24AA32A 24AA32A Product Identification System To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices. 24AA32A – /P Package: Temperature Range: Device: 1996 Microchip Technology Inc. P = Plastic DIP (300 mil Body), 8-lead SN = Plastic SOIC (150 mil Body, EIAJ standard) SM = Plastic SOIC (207 mil Body, EIAJ standard) Blank = 0°C to +70°C 24AA32A 24AA32AT 32K I2C Serial EEPROM (100 kHz, 400 kHz) 32K I2C Serial EEPROM (Tape and Reel) Preliminary DS21162B-page 11 WORLDWIDE SALES & SERVICE AMERICAS ASIA/PACIFIC EUROPE Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602 786-7200 Fax: 602 786-7277 Technical Support: 602 786-7627 Web: http://www.microchip.com Atlanta Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770 640-0034 Fax: 770 640-0307 Boston Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508 480-9990 Fax: 508 480-8575 Chicago Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 708 285-0071 Fax: 708 285-0075 Dallas Microchip Technology Inc. 14651 Dallas Parkway, Suite 816 Dallas, TX 75240-8809 Tel: 972 991-7177 Fax: 972 991-8588 Dayton Microchip Technology Inc. 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Unit 6, The Courtyard Meadow Bank, Furlong Road Bourne End, Buckinghamshire SL8 5AJ Tel: 44 1628 850303 Fax: 44 1628 850178 France Arizona Microchip Technology SARL Zone Industrielle de la Bonde 2 Rue du Buisson aux Fraises 91300 Massy - France Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79 Germany Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Muenchen, Germany Tel: 49 89 627 144 0 Fax: 49 89 627 144 44 Italy Arizona Microchip Technology SRL Centro Direzionale Colleone Pas Taurus 1 Viale Colleoni 1 20041 Agrate Brianza Milan Italy Tel: 39 39 6899939 Fax: 39 39 689 9883 JAPAN Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shin Yokohama Kohoku-Ku, Yokohama Kanagawa 222 Japan Tel: 81 45 471 6166 Fax: 81 45 471 6122 9/3/96 All rights reserved. 1996, Microchip Technology Incorporated, USA. 9/96 Printed on recycled paper. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. DS21162B-page 12 Preliminary 1996 Microchip Technology Inc.