PI6C185-01 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Precision 1-5 Clock Buffer Features Description • High-speed, low-noise non-inverting 1-5 buffer The PI6C185-01 is a high-speed low-noise 1-5 non-inverting buffer designed for SDRAM clock buffer applications. • Switching speed up to 140 MHz This buffer is intended to be used with the PI6C10X clock generator for Intel Architecture-based Mobile systems. • Supports up to two SODIMMs • Low skew (<250ps) between any two output clocks At power-up, all SDRAM outputs are enabled and active. The I2C Serial control may be used to individually activate/deactivate any of the 5 output drivers. • I2C Serial Configuration interface • Multiple VDD, VSS pins for noise reduction Note: Purchase of I2C components from Pericom conveys a license to use them in an I2C system as defined by Philips®. • 3.3V power supply voltage • Packaging (Pb-free & Green available): -16-pin TSSOP (L) - 16-pin QSOP (Q) Block Diagram Pin Configuration SDRAM0 SDRAM1 BUF_IN SDRAM2 SDRAM3 VDD 1 16 VDD SDRAM0 2 15 SDRAM4 SDRAM1 3 14 VSS VSS 4 13 VDD BUF_IN 5 12 SDRAM3 VDD 6 11 SDRAM2 SDATA 7 10 VSS SCLK 8 9 VSS SDRAM4 SDATA SCLOCK I2C I/O 1 PS8318E 10/14/04 PI6C185-01 Precision 1-5 Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Pin Description Pin Signal Type Qty De s cription 2,3,11,12,15 SDRAM [0.4] I 5 Buffered Clock Outputs 5 BUF_IN I 1 Clock Buffer Input 7 SDATA I/O 1 Serial Data for I2C interface, internal pull- up 8 SCLK I 1 Serial Clock for I2C interface, internal pull- up 1,6,13,16 VDD Power 4 3.3V Power Supply 4,9,10,14 VSS Ground 4 Ground I2C Address Assignment A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 1 0 0 1 0 Serial Configuration Map Byte1: SDRAM Active/Inactive Register (1 = enable, 0 = disable) Byte0: SDRAM Active/Inactive Register (1 = enable, 0 = disable) Bit Pin # Bit 7 12 Bit 6 De s cription Bit Pin# De s cription SDRAM3 (Active/Inactive) Bit 7 - NC (Initialize to 0) 11 SDRAM2 (Active/Inactive) Bit 6 - NC (Initialize to 0) Bit 5 - NC (Initialize to 0) Bit 5 - NC (Initialize to 0) Bit 4 - NC (Initialize to 0) Bit 4 - NC (Initialize to 0) Bit 3 - NC (Initialize to 0) Bit 3 - NC (Initialize to 0) Bit 2 - NC (Initialize to 0) Bit 2 - NC (Initialize to 0) Bit 1 3 SDRAM1 (Active/Inactive) Bit 1 - NC (Initialize to 0) Bit 0 2 SDRAM0 (Active/Inactive) Bit 0 15 SDRAM4 (Active/Inactive) Note: Inactive means outputs are held LOW and are disabled from switching 2 PS8318E 10/14/04 PI6C185-01 Precision 1-5 Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 2-Wire I2C Control 1 The I2C interface permits individual enable/disable of each clock output and test mode enable. Each data transfer is initiated with a start condition and ended with a stop condition. The first byte after a start condition is always a 7-bit address byte followed by a read/write bit. (HIGH = read from addressed device, LOW = write to addressed device). If the device’s own address is detected, PI6C185-01 generates an acknowledge by pulling SDATA line LOW during ninth clock pulse, then accepts the following data bytes until another start or stop condition is detected. The PI6C185-01 is a slave receiver device. It can not be read back. Sub-addressing is not supported. All preceding bytes must be sent in order to change one of the control bytes. Every bite put on the SDATA line must be 8-bits long (MSB first), followed by an acknowledge bit generated by the receiving device. Following acknowledgement of the address byte (0D2H), two more bytes must be sent: 1. “Command Code” byte, and 2. “Byte Count” byte. During normal data transfers SDATA changes only when SCLK is LOW. Exceptions: A HIGH-to-LOW transition on SDATA while SCLK is HIGH indicates a “start” condition. A LOW-to-HIGH transition on SDATA while SCLK is HIGH is a “stop” condition and indicates the end of a data transfer cycle. Although the data bits on these two bytes are “don’t care,” they must be sent and acknowledged. 2 3 4 5 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) 6 Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Storage Temperature ...................................... –65°C to +150°C Ambient Temperature with Power Applied ....... –40°C to +85°C 3.3V Supply Voltage to Ground Potential ........... –0.5V to +4.6V DC Input Voltage .............................................. –0.5V to +4.6V Supply Current (VDD = +3.465V, CLOAD = Max.) Symbol Parame te r Te s t Condition M in. Typ. IDD Supply Current BUF_IN = 0 MHz IDD Supply Current BUF_IN = 66.66 MHz 70 IDD Supply Current BUF_IN = 100.0 MHz 120 IDD Supply Current BUF_IN = 133.3 MHz 200 M ax. 7 8 9 Units 3 10 mA 11 12 13 14 15 3 PS8318E 10/14/04 PI6C185-01 Precision 1-5 Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Operating Specifications (VDD = +3.3V ±5%, TA = 0°C - 70°C) Symbol Parame te r Condition M in. M a x. VDD 2.0 VDD +0.3 VSS –0.3 0.8 0 < VIN < VDD -5 +5 2.4 Units Input Voltage VIH Input High Voltage VIL Input Low Voltage IIL Input Leakage Current V µA VDD = 3.3V ± 5% VOH Output High Voltage IOH = - 1mA VOL Output Low Voltage IOL = 1mA CIN Input Pin Capacitance 5 COUT Output pins Capacitance 6 LPIN Pin Inductance 7 nH 70 ºC TA Ambient Temperature No Airflow V 0.4 0 pF SDRAM Clock Buffer Operating Specification Symbol Parame te r Condition IOHMIN Pull- up current VOUT = 2.0V IOHMAX Pull- up current VOUT = 3.135V IOLMIN Pull- down current VOUT = 1.0V IOLMAX Pull- down current VOUT = 0.4V M in. Typ. M ax. Units –54 –46 mA 54 53 tRHSDRAM Output rise edge rate SDRAM only 3.3V ±5% @0.4V- 2.4V 1.5 4 tFHSDRAM Output fall edge rate SDRAM only 3.3V ±5% @2.4V- 0.4V 1.5 4 V/ns AC Timing Symbol Parameter 66 MHz Min. Max. TDSKP SDRAM CLK period 15.0 15.5 TSDKH SDRAM CLK high time 5.6 TSDKL SDRAM CLK low time 5.3 TSDRISE SDRAM CLK rise time 1.5 4.0 TSDFALL SDRAM CLK fall time 1.5 4.0 t PLH SDRAM Buffer LH prop delay 1.0 5.5 t PHL SDRAM Buffer HL prop delay 1.0 5.5 DutyCycle Measured at 1.5V 45 55 tSDSKW SDRAM Output to Output Skew 250 100 MHz Min. Max. 10.0 10.5 3.3 3.1 1.5 4.0 1.5 4.0 1.0 5.0 1.0 5.0 45 55 250 4 133 MHz Min. Max. 7.5 8.0 2.2 2.0 1.4 4.0 1.4 4.0 1.0 5.0 1.0 5.0 45 55 250 Units ns ns ns V/ns V/ns ns ns % ps PS8318E 10/14/04 PI6C185-01 Precision 1-5 Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 1 Test Point Output Buffer 2 Test Load 3 tSDKP tSDKH 3.3V Clocking Interface (TTL) 2.4 1.5 0.4 4 5 tSDKL tSDRISE tSDFALL 6 Input Waveform 1.5V 1.5V tplh 7 tphl Output Waveform 1.5V 8 1.5V 9 Figure 1. Clock Waveforms 10 Minimum and Maximum Expected Capacitive Loads Clock M in Load M ax Load SDRAM 20 30 Units pF Note s SDRAM DIMM Specification 11 Notes: 1. Maximum rise/fall times are guaranteed at maximum specified load. 2. Minimum rise/fall times are guaranteed at minimum specified load. 3. Rise/fall times are specified with pure capacitive load as shown. Testing is done with an additional 500Ω resistor in parallel. 12 13 Design Guidelines to Reduce EMI 14 1. Place R series resistors and CI capacitors as close as possible to the respective clock pins. Typical value for CI is 10 pF. R Series resistor value can be increased to reduce EMI provided that the rise and fall time are still within the specified values. 2. Minimize the number of “vias” of the clock traces. 3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing clock traces from plane to plane (refer to rule #2). 4. Position clock signals away from signals that go to any cables or any external connectors. S S 5 15 PS8318E 10/14/04 PI6C185-01 Precision 1-5 Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 100/66 MHz Clock from Chipset SDRAM 5 Rs CL SDRAM DIMM Spec. Figure 2. Design Guidelines Packaging Mechanical: 16-Pin TSSOP (L) 16 .169 .177 4.3 4.5 1 .193 .201 4.9 5.1 .004 .008 .047 max. 1.20 0.45 .018 0.75 .030 SEATING PLANE .0256 BSC 0.65 .007 .012 0.19 0.30 .002 .006 0.09 0.20 .252 BSC 6.4 0.05 0.15 X.XX DENOTES CONTROLLING X.XX DIMENSIONS IN MILLIMETERS 6 PS8318E 10/14/04 PI6C185-01 Precision 1-5 Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 1 Packaging Mechanical: 16-Pin QSOP (Q) 2 16 .008 0.20 MIN. .150 .157 .008 .013 0.20 0.33 3.81 3.99 .010 0.254 1 0˚-6˚ .016 .035 0.41 0.89 Detail A .189 .197 4.80 5.00 .041 1.04 REF 4 .015 x 45° 0.38 .008 0.203 REF .053 1.35 .069 1.75 Detail A SEATING PLANE .025 BSC 0.635 3 Guage Plane .008 .012 0.203 0.305 .007 .010 5 0.178 0.254 0.41 .016 1.27 .050 6 .228 .244 5.79 6.19 .004 0.101 .010 0.254 7 X.XX DENOTES DIMENSIONS IN MILLIMETERS X.XX 8 Ordering Information Ordering Code PI6C185-01L PI6C185-01LE PI6C185-01Q PI6C185-01QE PI6C185-01QI PI6C185-01QIE Packaging Code L L Q Q Q Q Package Description 16-Pin TSSOP Pb-free & Green, 16-Pin TSSOP 16-Pin QSOP Pb-free & Green, 16-Pin QSOP 16-Pin QSOP Pb-free & Green, 16-Pin QSOP Operating Temperature Commercial Commercial Commercial Commercial Industrial Industrial 9 10 11 Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 12 13 14 15 Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 7 PS8318E 10/14/04