PI6C2305-1 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 3.3V Zero-Delay Buffer Features Description • Zero-input-output propagation delay • 350ps phase error • Multiple low-skew outputs – Output-output skew less than 250ps – Device-device skew less than 700ps • 10 MHz to 100 MHz operating range • Low Jitter <200ps • High drive option (PI6C2305-1H) • 3.3V operation • Commercial Operation: 0°C to +70°C • Industrial Operation: –40°C to +85°C • Package: Space-saving 8-pin, 150-mil SOIC package (W) Providing five low-skew clocks, the PI6C2305-1 is a 3.3V zero-delay buffer designed to distribute clock signals in applications including PC, workstation, datacom, telecom, and high-performance systems. The PI6C2305-1 provides 5 copies of clocks that have less than 350ps propagation delay compared to a reference clock. The skew among the output clock signals for PI6C2305-1 is less than 250ps. When there are no rising edges on the REF input, the PI6C2305-1 enters a power-down state. In this mode, the PLL is off and all outputs are three-stated. This results in less than 50µA of current draw. Featuring faster rise and fall times, the PI6C2305-1H is the high-drive version of the PI6C2305-1. Block Diagram REF Pin Configuration FBK PLL CLK0 REF 1 CLK1 CLK2 2 CLK2 CLK1 3 GND 4 CLK3 8-Pin W 8 CLK0 7 CLK4 6 VDD 5 CLK3 CLK4 Pin Description Pin Signal 1 REF(1) 2 CLK2(2) Buffered Clock output 3 CLK1(2) Buffered Clock output 4 GND (2) De s cription Input reference frequency, 5V Tolerant input Ground Buffered Clock output 5 CLK3 6 VDD 7 CLK4(2) Buffered Clock output 8 CLK0(2) Buffered Clock output, internal feedback on this pin 3.3V Supply 1 Notes: 1. Weak pull-down. 2. Weak pull-down on all outputs. PS9477A 06/06/00 PI6C2305-1 3.3V Zero-Delay Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Zero-Delay and Skew Control REF. Input to CLK[1:4] Delay vs. Difference in Loading between CLK[0] pin and CLK[1:4] pins. 800 600 REF - Input to Output Clock Delay (ps) 400 200 0 -25 -20 -15 -10 -5 0 5 10 15 20 25 -200 -400 PI6C2305-1H -600 -800 PI6C2305-1 -900 -1000 Output Load Difference: CLK0 Load - CLK[1:4] Load (pF) Maximum Ratings To achieve a Zero Delay between the input and output, all outputs should be uniformly loaded. The relative loading of CLK0 (with respect to the remaining outputs) can adjust the input-output delay. This is shown in the graph above. Supply Voltage to Ground Potential .................–0.5V to +7.0V DC Input Voltage (Except REF) ............... –0.5V to VDD +0.5V DC Input Voltage REF .............................................. –0.5 to 7V Storage Temperature ..................................... –65º C to +150ºC Maximum Soldering Temperature (10 seconds) .............. 260ºC Junction Temperature ..................................................... 150ºC Static Discharge Voltage (per MIL-STD-883, Method 3015) ................................ >2000V For applications requiring zero input-output delay, all outputs including CLK0 should be equally loaded. Even if CLK0 is not used, it must have a capacitive load that is equal to that on every other output. If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. 2 PS9477A 06/06/00 PI6C2305-1 3.3V Zero-Delay Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Operating Conditions Parame te r De s cription M in. M ax. Units Supply Voltage 3 3.6 V TA (2305, 2305- 1H) Commercial Temperature (Ambient) 0 70 TA (2305I- 2305- 1HI) Industrial Temperature (Ambient) –40 85 CL Load Capacitance 30 CIN Input Capacitance 7 VDD ºC pF Electrical Characteristics (Over operating conditions) Parame te r De s cription Te s t Conditions M in. M ax. Units VIL Input LOW Voltage(3) — — 0.8 VIH Input HIGH Voltage(3) — 2.0 — IIL Input LOW Current VIN = 0V — 50.0 IIH Input HIGH Current VIN = VDD — 200.0 VOL Output LOW Voltage(4) IOL = 8mA (2305- 1) IOL = 12mA (2305- 1H) — 0.4 VOH Output HIGH Voltage(4) IOH = –8mA (2305- 1) IOH = –12mA (2305- 1H) 2.4 — IDD (PD mode) Power Down Supply Current REF = 0 MHz — 50.0 µA IDD Supply Current Unloaded outputs, 66.66 MHz, — 50.0 mA V µA V Notes: 3. REF and CLK0 inputs have a threshhold voltage of VDD/2. 4. Parameter is guaranteed by design and characterization. Not 100% tested in production. 3 PS9477A 06/06/00 PI6C2305-1 3.3V Zero-Delay Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Switching Characteristics(4, 5) (Over operating conditions) Parame te rs FCLK Name Te s t Conditions M in. Output Frequency 30pF load 10 Duty Cycle(4) = t2 ÷ t1 Measured at VDD/2, FOUT < 66.66 MHz 45 Duty Cycle(4) Measured at 1.4V, FOUT ≤ 45 MHz Typ. 50 M ax. Units 100 MHz 55 % = t2 ÷ t1 40 50 60 t3 Rise Time(4) @30pF t3 Rise Time(4)@30pF (H) t4 Fall Time(4) @30pF t4 Fall Time(4)@30pF (H) t5 Output to Output Skew(4) All outputs equally loaded t6 Delay, REF Rising Edge to CLK0 Rising Edge(4) Measured at VDD/2 0 ±350 t7 Device to Device Skew(4) Measured at VDD/2 on the output pins of devices 0 700 t8 Output Slew Rate(4) Measured between 0.8V and 2.0V on - H device using Test Circuit #2 tJ Cycle to Cycle Jitter(4) Measured at 66.67 MHz, loaded outputs 200 ps PLL Lock Time(4) Stable power supply, valid clocks presented on REFpins 1. 0 ms tLOCK 2.5 1.5 Measured between 0.8V and 2.0V ns 2.5 1.5 250 1 ps V/ns Notes: 4. Parameter is guaranteed by design and characterization. Not 100% tested in production. 5. For definition of t1-8, see Switching Waveforms on page 5. 4 PS9477A 06/06/00 PI6C2305-1 3.3V Zero-Delay Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Switching Waveforms Duty Cycle Timing t1 t2 1.4V 1.4V 1.4V All Outputs Rise/Fall Time 2.0V OUTPUT 3.3V 2.0V 0.8V 0.8V t 3,t8 0V t 4,t8 Output-Output Skew 1.4V OUTPUT 1.4V OUTPUT t5 Input-Output Propagation Delay VDD/2 INPUT VDD/2 CLK[1:4] t6 Device-Device Skew OUTPUT Device 1 VDD/2 VDD/2 OUTPUT Device 2 t7 Test Circuit #1 Test Circuit #2 VDD µF Ω VDD µF 1k 0.1 0.1 OUTPUTS OUTPUTS CLOAD Ω 1k µF 0.1 GND 10pF VDD VDD GND µF 0.1 GND Test Circuit for Test Circuit for all parameters except t 8 GND t 8 ,Output slew rate on PI6C2305-1H device 5 PS9477A 06/06/00 PI6C2305-1 3.3V Zero-Delay Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 8-Pin SOIC Package Mechanical (W) 8 .149 .157 3.78 3.99 .0099 .0196 0.25 x 45˚ 0.50 1 .189 .196 4.80 5.00 .0075 .0098 0-8˚ 0.19 0.25 0.40 .016 1.27 .050 .016 .026 0.406 0.660 .2284 .2440 5.80 6.20 1.35 1.75 .053 .068 SEATING PLANE REF .050 BSC 1.27 .0040 0.10 .0098 0.25 .013 0.330 .020 0.508 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Ordering Information Orde ring Code De s cription PI6C2305- 1W Normal Drive PI6C2305- 1HW High Drive PI6C2305- 1WI Normal Drive PI6C2305- 1HWI High Drive Package Type Ope rating Range 8- pin 150- mil SOIC Commercial 8- pin 150- mil SOIC Industrial Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 6 PS9477A 06/06/00