SN54LV540A, SN74LV540A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS409B – APRIL 1998 – REVISED NOVEMBER 1998 D D D D SN54LV540A . . . J OR W PACKAGE SN74LV540A . . . DB, DGV, DW, NS, OR PW PACKAGE (TOP VIEW) OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 SN54LV540A . . . FK PACKAGE (TOP VIEW) description A3 A4 A5 A6 A7 The ’LV540A devices are octal buffers/drivers designed for 2-V to 5.5-V VCC operation. 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 Y1 Y2 Y3 Y4 Y5 A8 GND Y8 Y7 Y6 These devices are ideal for driving bus lines or buffer memory address registers. They feature inputs and outputs on opposite sides of the package to facilitate printed circuit board layout. OE2 D EPIC (Enhanced-Performance Implanted CMOS) Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Small-Outline (DW, NS), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages, Ceramic Flat (W) Packages, Chip Carriers (FK), and DIPs (J) A2 A1 OE1 VCC D The 3-state control gate is a two-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2) input is high, all corresponding outputs are in the high-impedance state. The outputs provide inverted data when they are not in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54LV540A is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74LV540A is characterized for operation from –40°C to 85°C. FUNCTION TABLE (each buffer/driver) INPUTS OE1 OE2 A OUTPUT Y L L L H L L H L H X X Z X H X Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1998, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LV540A, SN74LV540A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS409B – APRIL 1998 – REVISED NOVEMBER 1998 logic symbol† OE1 OE2 A1 A2 A3 A4 A5 A6 A7 A8 1 & 19 EN 2 18 1 3 17 4 16 5 15 6 14 7 13 8 12 9 11 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) OE1 1 19 OE2 A1 18 2 Y1 To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output voltage range applied in the high or low state, VO (see Notes 1 and 2) . . . . . . –0.5 V to VCC + 0.5 V Output voltage range applied in high-impedance or power-off state, VO (see Note 1) . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 7 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LV540A, SN74LV540A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS409B – APRIL 1998 – REVISED NOVEMBER 1998 recommended operating conditions (see Note 4) SN54LV540A VCC VIH Supply voltage High level input voltage High-level VIL Low level input voltage Low-level VI Input voltage VO IOH IOL ∆t/∆v Output voltage High level output current High-level Low level output current Low-level Input transition rise or fall rate VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V SN74LV540A MIN MAX 2 5.5 1.5 MIN MAX 2 5.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 0.5 0 High or low state 0 3-state 0 VCC × 0.3 5.5 VCC 5.5 V 0.5 VCC × 0.3 VCC × 0.3 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC × 0.3 VCC × 0.3 0 0 0 VCC × 0.3 5.5 V V µA –50 –50 –2 –2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V –8 –8 –16 –16 VCC = 2 V VCC = 2.3 V to 2.7 V 50 50 2 2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 8 8 16 V VCC 5.5 VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V V 1.5 VCC × 0.7 VCC × 0.7 VCC = 2 V VCC = 2.3 V to 2.7 V UNIT mA µA mA 16 0 200 0 200 0 100 0 100 ns/V VCC = 4.5 V to 5.5 V 0 20 0 20 TA Operating free-air temperature –55 125 –40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LV540A, SN74LV540A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS409B – APRIL 1998 – REVISED NOVEMBER 1998 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL VCC IOH = –50 µA IOH = –2 mA 2 V to 5.5 V IOL = 50 µA IOL = 2 mA ICC Ioff VI = VCC or GND, VI or VO = 0 to 5.5 V TYP SN74LV540A MAX MIN TYP VCC–0.1 2 3V 2.48 2.48 4.5 V 3.8 MAX UNIT V 3.8 2 V to 5.5 V 0.1 0.1 2.3 V 0.4 0.4 3V 0.44 0.44 4.5 V 0.55 0.55 5.5 V ±1 ±1 µA IOL = 8 mA IOL = 16 mA VI = VCC or GND VO = VCC or GND MIN VCC–0.1 2 2.3 V IOH = –8 mA IOH = –16 mA II IOZ Ci SN54LV540A TEST CONDITIONS IO = 0 5.5 V ±5 ±5 µA 5.5 V 20 20 µA 5 µA 0V VI = VCC or GND V 5 3.3 V 2.5 2.5 5V 2.5 2.5 pF switching characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tpd∗ ten∗ A Y OE Y tdis∗ OE Y A Y OE Y OE Y tpd ten tdis LOAD CAPACITANCE CL = 15 pF CL = 50 pF MIN TA = 25°C TYP MAX SN54LV540A SN74LV540A MIN MAX MIN MAX 5.6 12 1 14.5 1 14.5 7.8 17.4 1 21 1 21 5.7 16 1 19 1 19 7.9 16.8 1 18.5 1 18.5 10.1 22.2 1 25.5 1 25.5 8.1 22.3 1 25.5 1 25.5 tsk(o)† ∗ On products compliant to MIL-PRF-38535, this parameter is not production tested. † Skew between any two outputs of the same package switching in the same direction 2 UNIT ns ns 2 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TO (OUTPUT) A Y 4.1 7 OE Y 5.6 10.5 OE Y 4.2 A Y ten OE Y tdis OE tpd∗ ten∗ tdis∗ tpd Y LOAD CAPACITANCE TA = 25°C MIN TYP MAX FROM (INPUT) PARAMETER CL = 15 pF CL = 50 pF MIN 1 8.5 1 8.5 1 12.5 1 12.5 10.5 1 12.5 1 12.5 5.8 10.5 1 12 1 12 7.3 14 1 16 1 16 5.8 15.4 1 17.5 1 17.5 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1.5 MIN SN74LV540A MAX tsk(o)† ∗ On products compliant to MIL-PRF-38535, this parameter is not production tested. † Skew between any two outputs of the same package switching in the same direction 4 SN54LV540A MAX 1.5 UNIT ns ns SN54LV540A, SN74LV540A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS409B – APRIL 1998 – REVISED NOVEMBER 1998 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tpd∗ ten∗ A Y OE Y tdis∗ OE LOAD CAPACITANCE MIN TA = 25°C TYP MAX CL = 15 pF SN54LV540A SN74LV540A MIN MAX MIN MAX 3 5 1 6 1 6 4.1 7.2 1 8.5 1 8.5 Y 2.9 7 1 8 1 8 tpd ten A Y 4.2 7 1 8 1 8 OE Y 5.3 9.2 1 10.5 1 10.5 tdis OE Y 3.5 8.8 1 10 1 10 CL = 50 pF tsk(o)† 1 UNIT ns ns 1 ∗ On products compliant to MIL-PRF-38535, this parameter is not production tested. † Skew between any two outputs of the same package switching in the same direction noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5) SN74LV540A PARAMETER MIN TYP MAX UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 0.54 0.8 V Quiet output, minimum dynamic VOL –0.28 –0.8 V VOH(V) VIH(D) Quiet output, minimum dynamic VOH 3.03 High-level dynamic input voltage V 2.3 V VIL(D) Low-level dynamic input voltage NOTE 5: Characteristics are for surface-mount packages only. 0.97 V VCC 3.3 V TYP UNIT 5V 11 operating characteristics, TA = 25°C PARAMETER Cpd d Power dissipation capacitance TEST CONDITIONS Outputs enabled Outputs enabled CL = 50 pF, pF f = 10 MHz 10 pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54LV540A, SN74LV540A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS409B – APRIL 1998 – REVISED NOVEMBER 1998 PARAMETER MEASUREMENT INFORMATION RL = 1 kΩ From Output Under Test Test Point From Output Under Test VCC Open S1 TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC 50% VCC Input th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC Input 50% VCC tPLH In-Phase Output 50% VCC VOH 50% VCC VOL 50% VCC Output Waveform 2 S1 at GND (see Note B) 50% VCC 0V Output Waveform 1 S1 at VCC (see Note B) tPLH VOH 50% VCC VOL 50% VCC tPZL tPHL tPHL Out-of-Phase Output 0V VCC Output Control tPLZ 50% VCC tPZH VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS ≈ VCC VOL + 0.3 V VOL tPHZ 50% VCC VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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