PM7342 S/UNI®-IMA-32 Preliminary 32 Link Inverse Multiplexer for ATM (IMA) / UNI PHY UNI UTOPIA / ANY-PHY INTERFACE • Each link is software configurable as either a UNI or part of an IMA group. • Performs receive cell Header Error Check (HEC) checking and transmit cell HEC generation. • Optionally supports receive cell payload unscrambling and transmit cell payload scrambling. • Provides TC layer statistics counts and alarms for MIB support. • Supports 8- and 16-bit UTOPIA L2 and Any-PHY cell interfaces at clock rates up to 52 MHz. • Any-PHY transmit slave appears as a 32 port multi-PHY. The PHY-ID of each cell is identified using in-band addressing. • Any-PHY receive slave appears as a single device. The PHY-ID of each cell is identified using in-band addressing. • UTOPIA L2 transmit and receive slave appears as a 31-port multi-PHY. • UTOPIA L2 receive slave can also appear as a single port with the logical port provided as a prepend. ATM OVER FRACTIONAL T1/E1 TCK TMS TDI TRSTB TDO OE BLOCK DIAGRAM D[15:0] A[10:1] ALE WRB RDB CSB INTB • Supports ATM over Fractional T1/E1 compliant with the ATM Forum AF-PHY-0130.00 specification. • 32 T1, E1, G.SHDSL or unchannelized links via 2-pin line interfaces. • Supports a 19.44 MHz Scalable Bandwidth Interconnect (SBI) bus interface for seamless interconnect to the PM8315 TEMUX and PM8316 TEMUX-84. • SBI supports two Synchronous Payload Envelopes (SPE). Each SPE can carry up to 16 T1s or 16 E1s. SYSCLK • Supports up to 32 T1, E1, G.SHDSL or unchannelized links and up to 32 IMA groups with 1 to 32 links/group. • Link and Group State Machines implemented on-chip requiring no real time software in the data path. • Fully compliant with the ATM Forum Inverse Multiplexer for ATM (IMA) 1.1 specification and backward compatible to IMA 1.0. • Supports both independent transmit clock (ITC) and common transmit clock (CTC) modes. • Supports all IMA Group Symmetry modes: Symmetric/Asymmetric configuration and operation. • Differential delay tolerance of 279 ms (for T1 links) and 226 ms (for E1 links). • Performs IMA differential delay calculation and synchronization. • Provides programmable limit on allowable differential delay and minimum number of links per group. LINE INTERFACE REFCLK IMA • Performs ICP and stuff-cell insertion and removal. • Supports IMA frame length (M) equal to 32, 64, 128, or 256. • Provides IMA layer statistic counts and alarms for support of IMA Performance and Failure Alarm Monitoring and MIB support. • Provides per link counters for statistics and performance monitoring. RSTB FEATURES DLL MicroProcess I/F JTAG SBI Add Bus I/F AC1FP ADATA[7:0] ADP APL AV5 AJUST_REQ AACTIVE ADETECT INSBI TC Layer (TTTC32) 32 Clk/Data TSCLK[31:0] TSDATA[31:0] CTSCLK Tx Slave ATM I/F Null Framer (SDFR32) 32-chan x 7 cell FIFO (MCFD) Tx IMA Processor (TIMA) 32-chan x 3 cell FIFO Any-PHY/ UTOPIA Tx Slave (TXAPS) TCAS TCLK TPA TENB TADR[10:0] TCSB TSOP TSX TDAT[15:0] TPRTY IDCC Internal Bus Rx IMA Protocol Processor (RIPP) IDCC 32 Clk/Data RSCLK[31:0] RSDATA[31:0] RCAS TC Layer (RTTC32) SBI Drop Bus I/F 32-chan x 2 cell FIFO Rx IMA Data Processor (RDAT) Cell Writer EXSBI Cell Reader 31 chan 4 cell FIFO DeFramer (SDDF32) Any-PHY/ UTOPIA Rx Slave (RXAPS) RCLK RPA RENB RADR[4:0] RCSB RSOP RSX RDAT[15:0] RPRTY Memory Interface (MEMI) CBCSB CBRASB CBCASB CBWEB CBA[11:0] CBBS[1:0] CBDQM CBDQ[15:0] DC1FP DDATA[7:0] DDP DPL DV5 Rx Slave ATM I/F PMC-2001523 (p5) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE © Copyright PMC-Sierra, Inc. 2002 Preliminary PM7342 S/UNI®-IMA-32 32 Link Inverse Multiplexer for ATM (IMA) / UNI PHY LOOPBACK AND DIAGNOSTICS • Supports UTOPIA Side Loopback. • Supports Line Side Loopback. • Supports per group ICP cell trace capability. SOFTWARE • The S/UNI-IMA device driver, written in ANSI C, provides a well-defined Application Programming Interface (API) and low level utility functions for diagnostics and debugging purposes. • Software wrappers are used for RTOSrelated functions making the S/UNIIMA device driver portable to any Real Time Operating System (RTOS) environment. • Low-power 1.8 V CMOS with TTLcompatible I/O. • 416-pin plastic ball grid array (PBGA) package. GENERAL APPLICATIONS • 16-bit interface for 1M x 16 SDRAM. • Provides a 16-bit microprocessor interface for configuration, statistics gathering and Link and Unit Management. • Provides a standard 5-pin P1149 JTAG port. • • • • • Multiservice Switches. Optical Access Switches. DSLAMs. Wireless Basestation Controllers. Access Concentrators. TYPICAL APPLICATIONS DSLAM WITH IMA OVER DSL UTOPIA L2/ Any-PHY UTOPIA L2 xN PM7326 S/UNI-APEX UTOPIA L2 / Any-PHY PM7351 S/UNI-VORTEX x32 (x31 with UL2) PM7342 S/UNI-IMA-32 xDSL MODEM PM7350 S/UNI-DUPLEX PM7346 S/UNI-QJET PM7324 S/UNI-ATLAS LVDS 32 Clock/Data WIRELESS BASESTATION CONTROLLER RM7000 uP DS-3 Packet Card DS3 LIU L2 Address Resolution and SAR PM7381 FREEDM32A672 PM4328 TECT3 PM7329 S/UNI-APEX1K800 HMVIP PM7328 S/UNI-ATLAS1K800 32-port T1/E1 ATM Card SBI Bus Head Office: PMC-Sierra, Inc. 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: +1.604.415.6000 Fax: +1.604.415.6200 PM7342 S/UNI-IMA-32 PM4332 TE-32 PM4319 OCTLIU SBI Bus To order documentation, send email to: [email protected] or contact the head office, Attn: Document Coordinator AAL2 Processing UTOPIA L2/ Any-PHY UTOPIA Bus All product documentation is available on our web site at: http://www.pmc-sierra.com For corporate information, send email to: [email protected] PMC-2001523 (p5) © Copyright PMC-Sierra, Inc. 2002. All rights reserved. February 2002. S/UNI is a registered trademark of PMC-Sierra, Inc. SBI, AAL1gator, FREEDM, SPECTRA, COMET-QUAD, VORTEX, TEMUX, Any-PHY and PMCSierra are trademarks of PMC-Sierra, Inc. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE