PMC PM7382-PI

PM7382 FREEDM-32P256
RELEASED
DATA SHEET
PMC-2010333
ISSUE 3
FRAME ENGINE AND DATA LINK MANAGER 32P256
PM7382
FREEDM™-32P256
FRAME ENGINE AND DATALINK
MANAGER 32P256
DATA SHEET
RELEASED
ISSUE 3: AUGUST 2001
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PM7382 FREEDM-32P256
RELEASED
DATA SHEET
PMC-2010333
ISSUE 3
FRAME ENGINE AND DATA LINK MANAGER 32P256
PUBLIC REVISION HISTORY
Issue No.
Issue Date
Details of Change
Issue 1
April 11, 2001
Created Document.
Issue 2
August 13, 2001
Changed Status from Advance to Released
Issue 3
August 22, 2001
Added patent information to legal footer.
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FRAME ENGINE AND DATA LINK MANAGER 32P256
CONTENTS
1
FEATURES...............................................................................................1
2
APPLICATIONS........................................................................................4
3
REFERENCES .........................................................................................5
4
BLOCK DIAGRAM....................................................................................6
5
DESCRIPTION .........................................................................................7
6
PIN DIAGRAM ........................................................................................10
7
PIN DESCRIPTION ................................................................................ 11
8
FUNCTIONAL DESCRIPTION ...............................................................36
8.1
HIGH SPEED MULTI-VENDOR INTEGRATION PROTOCOL
(H-MVIP) ......................................................................................36
8.2
HIGH-LEVEL DATA LINK CONTROL (HDLC) PROTOCOL.........36
8.3
RECEIVE CHANNEL ASSIGNER ................................................37
8.4
8.5
8.3.1
LINE INTERFACE TRANSLATOR (LIT) ........................39
8.3.2
LINE INTERFACE..........................................................39
8.3.3
PRIORITY ENCODER ...................................................40
8.3.4
CHANNEL ASSIGNER ..................................................40
8.3.5
LOOPBACK CONTROLLER .........................................41
RECEIVE HDLC PROCESSOR / PARTIAL PACKET BUFFER...41
8.4.1
HDLC PROCESSOR .....................................................42
8.4.2
PARTIAL PACKET BUFFER PROCESSOR ..................42
RECEIVE DMA CONTROLLER ...................................................44
8.5.1
DATA STRUCTURES ....................................................44
8.5.2
DMA TRANSACTION CONTROLLER...........................54
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8.6
8.7
8.8
8.9
FRAME ENGINE AND DATA LINK MANAGER 32P256
8.5.3
WRITE DATA PIPELINE/MUX .......................................54
8.5.4
DESCRIPTOR INFORMATION CACHE ........................54
8.5.5
FREE QUEUE CACHE ..................................................55
PCI CONTROLLER......................................................................55
8.6.1
MASTER MACHINE ......................................................56
8.6.2
MASTER LOCAL BUS INTERFACE..............................58
8.6.3
TARGET MACHINE .......................................................59
8.6.4
CBI BUS INTERFACE ...................................................61
8.6.5
ERROR / BUS CONTROL .............................................61
TRANSMIT DMA CONTROLLER.................................................61
8.7.1
DATA STRUCTURES ....................................................62
8.7.2
TASK PRIORITIES ........................................................74
8.7.3
DMA TRANSACTION CONTROLLER...........................74
8.7.4
READ DATA PIPELINE..................................................74
8.7.5
DESCRIPTOR INFORMATION CACHE ........................74
8.7.6
FREE QUEUE CACHE ..................................................75
TRANSMIT HDLC CONTROLLER / PARTIAL PACKET BUFFER75
8.8.1
TRANSMIT HDLC PROCESSOR..................................75
8.8.2
TRANSMIT PARTIAL PACKET BUFFER PROCESSOR76
TRANSMIT CHANNEL ASSIGNER .............................................78
8.9.1
LINE INTERFACE TRANSLATOR (LIT) ........................80
8.9.2
LINE INTERFACE..........................................................80
8.9.3
PRIORITY ENCODER ...................................................81
8.9.4
CHANNEL ASSIGNER ..................................................81
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8.10
PERFORMANCE MONITOR .......................................................82
8.11
JTAG TEST ACCESS PORT INTERFACE...................................82
8.12
PCI HOST INTERFACE ...............................................................82
NORMAL MODE REGISTER DESCRIPTION ........................................87
9.1
10
12
13
PCI HOST ACCESSIBLE REGISTERS .......................................87
PCI CONFIGURATION REGISTER DESCRIPTION ............................250
10.1
11
FRAME ENGINE AND DATA LINK MANAGER 32P256
PCI CONFIGURATION REGISTERS.........................................250
TEST FEATURES DESCRIPTION .......................................................261
11.1
TEST MODE REGISTERS ........................................................261
11.2
JTAG TEST PORT .....................................................................262
11.2.1
IDENTIFICATION REGISTER .....................................263
11.2.2
BOUNDARY SCAN REGISTER ..................................263
OPERATIONS ......................................................................................280
12.1
TOCTL CONNECTIONS ............................................................280
12.2
JTAG SUPPORT........................................................................280
FUNCTIONAL TIMING .........................................................................287
13.1
RECEIVE H-MVIP LINK TIMING ...............................................287
13.2
TRANSMIT H-MVIP LINK TIMING.............................................288
13.3
RECEIVE NON H-MVIP LINK TIMING ......................................289
13.4
TRANSMIT NON H-MVIP LINK TIMING ....................................291
13.5
PCI INTERFACE ........................................................................292
13.6
BERT INTERFACE ....................................................................301
14
ABSOLUTE MAXIMUM RATINGS........................................................303
15
D.C. CHARACTERISTICS....................................................................304
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16
FREEDM-32P256 TIMING CHARACTERISTICS.................................306
17
ORDERING AND THERMAL INFORMATION ......................................316
18
MECHANICAL INFORMATION.............................................................317
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LIST OF FIGURES
FIGURE 1 – H-MVIP PROTOCOL ....................................................................36
FIGURE 2 – HDLC FRAME...............................................................................37
FIGURE 3 – CRC GENERATOR.......................................................................37
FIGURE 4 – PARTIAL PACKET BUFFER STRUCTURE ..................................43
FIGURE 5 – RECEIVE PACKET DESCRIPTOR...............................................45
FIGURE 6 – RECEIVE PACKET DESCRIPTOR TABLE...................................48
FIGURE 7 – RPDRF AND RPDRR QUEUES ...................................................50
FIGURE 8 – RPDRR QUEUE OPERATION......................................................52
FIGURE 9 – RECEIVE CHANNEL DESCRIPTOR REFERENCE TABLE.........53
FIGURE 10 – GPIC ADDRESS MAP ................................................................60
FIGURE 11 – TRANSMIT DESCRIPTOR..........................................................62
FIGURE 12 – TRANSMIT DESCRIPTOR TABLE .............................................66
FIGURE 13 – TDRR AND TDRF QUEUES .......................................................68
FIGURE 14 – TRANSMIT CHANNEL DESCRIPTOR REFERENCE TABLE ....70
FIGURE 15 – TD LINKING................................................................................73
FIGURE 16 – PARTIAL PACKET BUFFER STRUCTURE ................................77
FIGURE 17 – INPUT OBSERVATION CELL (IN_CELL) .................................277
FIGURE 18 – OUTPUT CELL (OUT_CELL) ...................................................278
FIGURE 19 – BI-DIRECTIONAL CELL (IO_CELL) .........................................278
FIGURE 20 – LAYOUT OF OUTPUT ENABLE AND BI-DIRECTIONAL CELLS
..............................................................................................................279
FIGURE 21 – BOUNDARY SCAN ARCHITECTURE ......................................281
FIGURE 22 – TAP CONTROLLER FINITE STATE MACHINE ........................283
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FIGURE 23 – RECEIVE 8.192 MBPS H-MVIP LINK TIMING .........................287
FIGURE 24 – RECEIVE 2.048 MBPS H-MVIP LINK TIMING .........................288
FIGURE 25 – TRANSMIT 8.192 MBPS H-MVIP LINK TIMING.......................288
FIGURE 26 – TRANSMIT 2.048 MBPS H-MVIP LINK TIMING.......................289
FIGURE 27 – UNCHANNELISED RECEIVE LINK TIMING ............................290
FIGURE 28 – CHANNELISED T1/J1 RECEIVE LINK TIMING .......................290
FIGURE 29 – CHANNELISED E1 RECEIVE LINK TIMING ............................291
FIGURE 30 – UNCHANNELISED TRANSMIT LINK TIMING..........................291
FIGURE 31 – CHANNELISED T1/J1 TRANSMIT LINK TIMING .....................292
FIGURE 32 – CHANNELISED E1 TRANSMIT LINK TIMING .........................292
FIGURE 33 – PCI READ CYCLE ....................................................................294
FIGURE 34 – PCI WRITE CYCLE ..................................................................295
FIGURE 35 – PCI TARGET DISCONNECT ....................................................296
FIGURE 36 – PCI TARGET ABORT................................................................297
FIGURE 37 – PCI BUS REQUEST CYCLE ....................................................297
FIGURE 38 – PCI INITIATOR ABORT TERMINATION ...................................298
FIGURE 39 – PCI EXCLUSIVE LOCK CYCLE ...............................................299
FIGURE 40 – PCI FAST BACK TO BACK.......................................................301
FIGURE 41 – RECEIVE BERT PORT TIMING ...............................................301
FIGURE 42 – TRANSMIT BERT PORT TIMING .............................................302
FIGURE 43 – RECEIVE DATA & FRAME PULSE TIMING (2.048 MBPS H-MVIP
MODE) ..................................................................................................308
FIGURE 44 – RECEIVE DATA & FRAME PULSE TIMING (8.192 MBPS H-MVIP
MODE) ..................................................................................................308
FIGURE 45 – RECEIVE DATA TIMING (NON H-MVIP MODE) ......................309
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FIGURE 46 – BERT INPUT TIMING ...............................................................309
FIGURE 47 – TRANSMIT DATA & FRAME PULSE TIMING (2.048 MBPS
H-MVIP MODE)..................................................................................... 311
FIGURE 48 – TRANSMIT DATA & FRAME PULSE TIMING (8.192 MBPS
H-MVIP MODE).....................................................................................312
FIGURE 49 – TRANSMIT DATA TIMING (NON H-MVIP MODE) ....................312
FIGURE 50 – BERT OUTPUT TIMING ...........................................................313
FIGURE 51 – PCI INTERFACE TIMING .........................................................314
FIGURE 52 – JTAG PORT INTERFACE TIMING............................................315
FIGURE 53 – 329 PIN PLASTIC BALL GRID ARRAY (PBGA) .......................317
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LIST OF TABLES
TABLE 1 – LINE SIDE INTERFACE SIGNALS (154) ........................................ 11
TABLE 2 – PCI HOST INTERFACE SIGNALS (52) ..........................................21
TABLE 3 – MISCELLANEOUS INTERFACE SIGNALS (58).............................30
TABLE 4 – PRODUCTION TEST INTERFACE SIGNALS (0 - MULTIPLEXED)31
TABLE 5 – POWER AND GROUND SIGNALS (65) .........................................33
TABLE 6 – RECEIVE PACKET DESCRIPTOR FIELDS....................................45
TABLE 7 – RPDRR QUEUE ELEMENT ............................................................51
TABLE 8 – RECEIVE CHANNEL DESCRIPTOR REFERENCE TABLE FIELDS
................................................................................................................53
TABLE 9 – TRANSMIT DESCRIPTOR FIELDS ................................................63
TABLE 10 – TRANSMIT DESCRIPTOR REFERENCE.....................................69
TABLE 11 – TRANSMIT CHANNEL DESCRIPTOR REFERENCE TABLE
FIELDS ...................................................................................................71
TABLE 12 – NORMAL MODE PCI HOST ACCESSIBLE REGISTER MEMORY
MAP ........................................................................................................82
TABLE 13 – PCI CONFIGURATION REGISTER MEMORY MAP.....................86
TABLE 14 – BIG ENDIAN FORMAT................................................................ 117
TABLE 15 – LITTLE ENDIAN FORMAT .......................................................... 117
TABLE 16 - RECEIVE LINKS #0 TO #2 CONFIGURATION ...........................128
TABLE 17 - RECEIVE LINKS #3 TO #31 CONFIGURATION .........................130
TABLE 18 – CRC[1:0] SETTINGS...................................................................137
TABLE 19 – RPQ_RDYN[2:0] SETTINGS ......................................................148
TABLE 20 – RPQ_LFN[1:0] SETTINGS..........................................................149
TABLE 21 – RPQ_SFN[1:0] SETTINGS .........................................................149
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TABLE 22 – TDQ_RDYN[2:0] SETTINGS.......................................................183
TABLE 23 – TDQ_FRN[1:0] SETTINGS .........................................................183
TABLE 24 – CRC[1:0] SETTINGS................................................................... 211
TABLE 25 – FLAG[2:0] SETTINGS .................................................................217
TABLE 26 – LEVEL[3:0]/TRANS SETTINGS ..................................................219
TABLE 27 - TRANSMIT LINKS #0 TO #2 CONFIGURATION .........................237
TABLE 28 - TRANSMIT LINKS #3 TO #31 CONFIGURATION .......................239
TABLE 29 – TEST MODE REGISTER MEMORY MAP ..................................262
TABLE 30 – INSTRUCTION REGISTER ........................................................263
TABLE 31 – BOUNDARY SCAN CHAIN .........................................................263
TABLE 32 – FREEDM–TOCTL CONNECTIONS ............................................280
TABLE 33 – FREEDM-32P256 ABSOLUTE MAXIMUM RATINGS.................303
TABLE 34 – FREEDM-32P256 D.C. CHARACTERISTICS.............................304
TABLE 35 – FREEDM-32P256 LINK INPUT (FIGURE 43 TO FIGURE 46)....306
TABLE 36 – FREEDM-32P256 LINK OUTPUT (FIGURE 47 TO FIGURE 50) 309
TABLE 37 – PCI INTERFACE (FIGURE 51) ...................................................313
TABLE 38 – JTAG PORT INTERFACE (FIGURE 52)......................................314
TABLE 39 – FREEDM-32P256 ORDERING INFORMATION..........................316
TABLE 40 – FREEDM-32P256 THERMAL INFORMATION ............................316
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FEATURES
·
Single-chip multi-channel HDLC controller with a 66 MHz, 32 bit Peripheral
Component Interconnect (PCI) Revision 2.1 bus for configuration, monitoring
and transfer of packet data, with an on-chip DMA controller with scatter/
gather capabilities.
·
Supports up to 256 bi-directional HDLC channels assigned to a maximum of
32 H-MVIP digital telephony buses at 2.048 Mbps per link. The links are
grouped into 4 logical groups of 8 links. A common clock and a type 0 frame
pulse is shared among links in each logical group. The number of time-slots
assigned to an HDLC channel is programmable from 1 to 32.
·
Supports up to 256 bi-directional HDLC channels assigned to a maximum of
8 H-MVIP digital telephony buses at 8.192 Mbps per link. The links share a
common clock and a type 0 frame pulse. The number of time-slots assigned
to an HDLC channel is programmable from 1 to 128.
·
Supports up to 256 bi-directional HDLC channels assigned to a maximum of
32 channelised T1/J1 or E1 links. The number of time-slots assigned to an
HDLC channel is programmable from 1 to 24 (for T1/J1) and from 1 to 31 (for
E1).
·
Supports up to 32 bi-directional HDLC channels each assigned to an
unchannelised arbitrary rate link, subject to a maximum aggregate link clock
rate of 64 MHz in each direction. Channels assigned to links 0 to 2 support a
clock rate of up to 51.84 MHz. Channels assigned to links 3 to 31 support a
clock rate of up to 10 MHz.
·
Supports three bi-directional HDLC channels each assigned to an
unchannelised arbitrary rate link of up to 51.84 MHz when SYSCLK is running
at 45 MHz.
·
Supports a mix of up to 32 channelised, unchannelised and H-MVIP links,
subject to the constraint of a maximum of 256 channels and a maximum
aggregate link clock rate of 64 MHz in each direction.
·
Links configured for channelised T1/J1/E1 or unchannelised operation
support the gapped-clock method for determining time-slots which is
backwards compatible with the FREEDM-8 and FREEDM-32 devices.
·
For each channel, the HDLC receiver supports programmable flag sequence
detection, bit de-stuffing and frame check sequence validation. The receiver
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supports the validation of both CRC-CCITT and CRC-32 frame check
sequences.
·
For each channel, the receiver checks for packet abort sequences, octet
aligned packet length and for minimum and maximum packet length. The
receiver supports filtering of packets that are larger than a user specified
maximum value.
·
Alternatively, for each channel, the receiver supports a transparent mode
where each octet is transferred transparently to host memory. For
channelised links, the octets are aligned with the receive time-slots.
·
For each channel, time-slots are selectable to be in 56 kbits/s format or 64
kbits/s clear channel format.
·
For each channel, the HDLC transmitter supports programmable flag
sequence generation, bit stuffing and frame check sequence generation. The
transmitter supports the generation of both CRC-CCITT and CRC-32 frame
check sequences. The transmitter also aborts packets under the direction of
the host or automatically when the channel underflows.
·
Supports two levels of non-preemptive packet priority on each transmit
channel. Low priority packets will not begin transmission until all high priority
packets are transmitted.
·
Alternatively, for each channel, the transmitter supports a transparent mode
where each octet is inserted transparently from host memory. For
channelised links, the octets are aligned with the transmit time-slots.
·
Provides 32 Kbytes of on-chip memory for partial packet buffering in both the
transmit and receive directions. This memory may be configured to support a
variety of different channel configurations from a single channel with 32
Kbytes of buffering to 256 channels, each with a minimum of 48 bytes of
buffering.
·
Supports PCI burst sizes of up to 256 bytes for transfers of packet data.
·
Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board
test purposes.
·
Supports 3.3 Volt PCI signaling environments.
·
Supports 5 Volt tolerant I/O (except PCI).
·
Low power 2.5 Volt 0.25 mm CMOS technology.
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FRAME ENGINE AND DATA LINK MANAGER 32P256
329 pin plastic ball grid array (PBGA) package.
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APPLICATIONS
·
IETF PPP interfaces for routers
·
TDM switches
·
Frame Relay interfaces for ATM or Frame Relay switches and multiplexors
·
FUNI or Frame Relay service inter-working interfaces for ATM switches and
multiplexors.
·
Internet/Intranet access equipment.
·
Packet-based DSLAM equipment.
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REFERENCES
1. International Organization for Standardization, ISO Standard 3309-1993,
"Information Technology - Telecommunications and information exchange
between systems - High-level data link control (HDLC) procedures - Frame
structure", December 1993.
2. RFC-1662 - "PPP in HDLC-like Framing" Internet Engineering Task Force,
July 1994.
3. PCI Special Interest Group, PCI Local Bus Specification, June 1, 1995,
Version 2.1.
4. GO-MVIP, “MVIP-90 Standard”, October 1994, release 1.1.
5. GO-MVIP, “H-MVIP Standard”, January 1997, release 1.1a.
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Transmit
Channel
Assigner
(TCAS256)
RBD
TD[31:0]
TCLK[31:0]
TFPB[3:0]
TMVCK[3:0]
TMV8DC
TMV8FPC
TFP8B
RBCLK
RSTB
JTAG Port
Transmit
DMA
Controller
(TMAC256)
PCI
Controller
(GPIC256)
FRAMEB
TRDYB
IRDYB
STOPB
DEVSELB
IDSEL
LOCKB
REQB
GNTB
PERRB
SERRB
PCIINTB
PCICLK
PCICLKO
M66EN
PMC-2010333
Transmit HDLC Processor/
Partial Packet Buffer
(THDL256)
Receive
DMA
Controller
(RMAC256)
SYSCLK
Performance Monitor
(PMON)
Receive HDLC Processor/
Partial Packet Buffer
(RHDL256)
PMCTEST
Receive
Channel
Assigner
(RCAS256)
AD[31:0]
C/BEB[3:0]
PAR
4
RD[31:0]
RCLK[31:0]
RFPB[3:0]
RMVCK[3:0]
RMV8DC
RMV8FPC
RFP8B
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BLOCK DIAGRAM
TDO
TDI
TCK
TMS
TRSTB
TBCLK
TBD
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DESCRIPTION
The PM7382 FREEDM-32P256 Frame Engine and Datalink Manager device is a
monolithic integrated circuit that implements HDLC processing, and PCI Bus
memory management functions for a maximum of 256 bi-directional channels.
The FREEDM-32P256 may be configured to support H-MVIP, channelised
T1/J1/E1 or unchannelised traffic across 32 physical links.
The FREEDM-32P256 may be configured to interface with H-MVIP digital
telephony buses at 2.048 Mbps. For 2.048 Mbps H-MVIP links, the FREEDM32P256 allows up to 256 bi-directional HDLC channels to be assigned to
individual time-slots within a maximum of 32 H-MVIP links. The channel
assignment supports the concatenation of time-slots (N x DS0) up to a maximum
of 32 concatenated time-slots for each 2.048 Mbps H-MVIP link. Time-slots
assigned to any particular channel need not be contiguous within the H-MVIP
link. When configured for 2.048 Mbps H-MVIP operation, the FREEDM-32P256
partitions the 32 physical links into 4 logical groups of 8 links. Links 0 through 7,
8 through 15, 16 through 23 and 24 through 31 make up the 4 logical groups.
Links in each logical group share a common clock and a common type 0 frame
pulse in each direction.
The FREEDM-32P256 may be configured to interface with H-MVIP digital
telephony buses at 8.192 Mbps. For 8.192 Mbps H-MVIP links, the FREEDM32P256 allows up to 256 bi-directional HDLC channels to be assigned to
individual time-slots within a maximum of 8 H-MVIP links. The channel
assignment supports the concatenation of time-slots (N x DS0) up to a maximum
of 128 concatenated time-slots for each 8.192 H-MVIP link. Time-slots assigned
to any particular channel need not be contiguous within the H-MVIP link. When
configured for 8.192 Mbps H-MVIP operation, the FREEDM-32P256 partitions
the 32 physical links into 8 logical groups of 4 links. Only the first link, which
must be located at physical links numbered 4m (0£m£7), of each logical group
can be configured for 8.192 Mbps operation. The remaining 3 physical links in
the logical group (numbered 4m+1, 4m+2 and 4m+3) are unused. All links
configured for 8.192 Mbps H-MVIP operation will share a common type 0 frame
pulse, a common frame pulse clock and a common data clock.
For channelised T1/J1/E1 links, the FREEDM-32P256 allows up to 256 bidirectional HDLC channels to be assigned to individual time-slots within a
maximum of 32 independently timed T1/J1 or E1 links. The gapped clock
method to determine time-slot positions as per the FREEDM-8 and FREEDM-32
devices is retained. The channel assignment supports the concatenation of
time-slots (N x DS0) up to a maximum of 24 concatenated time-slots for a T1/J1
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link and 31 concatenated time-slots for an E1 link. Time-slots assigned to any
particular channel need not be contiguous within the T1/J1 or E1 link.
For unchannelised links, the FREEDM-32P256 processes up to 32 bi-directional
HDLC channels within 32 independently timed links. The links can be of
arbitrary frame format. When limited to three unchannelised links, each link can
be rated at up to 51.84 MHz provided SYSCLK is running at 45 MHz. For lower
rate unchannelised links, the FREEDM-32P256 processes up to 32 links each
rated at up to 10 MHz. In this case, the aggregate clock rate of all the links is
limited to 64 MHz.
The FREEDM-32P256 supports mixing of up to 32 channelised T1/J1/E1,
unchannelised and H-MVIP links. The total number of channels in each direction
is limited to 256. The aggregate instantaneous clock rate over all 32 possible
links is limited to 64 MHz.
In the receive direction, the FREEDM-32P256 performs channel assignment and
packet extraction and validation. For each provisioned HDLC channel, the
FREEDM-32P256 delineates the packet boundaries using flag sequence
detection, and performs bit de-stuffing. Sharing of opening and closing flags, as
well as sharing of zeros between flags are supported. The resulting packet data
is placed into the internal 32 Kbyte partial packet buffer RAM. The partial packet
buffer acts as a logical FIFO for each of the assigned channels. Partial packets
are DMA'd out of the RAM, across the PCI bus and into host packet memory.
The FREEDM-32P256 validates the frame check sequence for each packet, and
verifies that the packet is an integral number of octets in length and is within a
programmable minimum and maximum length. The receive packet status is
updated before linking the packet into a receive ready queue. The FREEDM32P256 alerts the PCI Host that there are packets in a receive ready queue by,
optionally, asserting an interrupt on the PCI bus.
Alternatively, in the receive direction, the FREEDM-32P256 supports a
transparent operating mode. For each provisioned transparent channel, the
FREEDM-32P256 directly transfers the received octets into host memory
verbatim. If the transparent channel is assigned to a channelised link, then the
octets are aligned to the received time-slots.
In the transmit direction, the PCI Host provides packets to transmit using a
transmit ready queue. For each provisioned HDLC channel, the FREEDM32P256 DMA's partial packets across the PCI bus and into the transmit partial
packet buffer. The partial packets are read out of the packet buffer by the
FREEDM-32P256 and a frame check sequence is optionally calculated and
inserted at the end of each packet. Bit stuffing is performed before being
assigned to a particular link. The flag sequence is automatically inserted when
there is no packet data for a particular channel. Sequential packets are
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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FRAME ENGINE AND DATA LINK MANAGER 32P256
optionally separated by two flags (an opening flag and a closing flag) or a single
flag (combined opening and closing flag). Zeros between flags are not shared.
PCI bus latency may cause one or more channels to underflow, in which case,
the packets are aborted, and the host is notified. For normal traffic, an abort
sequence is generated, followed by inter-frame time fill characters (flags or allones bytes) until a new packet is sourced from the PCI host. No attempt is made
to automatically re-transmit an aborted packet.
Alternatively, in the transmit direction, the FREEDM-32P256 supports a
transparent operating mode. For each provisioned transparent channel, the
FREEDM-32P256 directly inserts the transmitted octets from host memory. If the
transparent channel is assigned to a channelised link, then the octets are aligned
to the transmitted time-slots. If a channel underflows due to excessive PCI bus
latency, an abort sequence is generated, followed by inter-frame time fill
characters (flags or all-ones bytes) to indicate idle channel. Data resumes
immediately when the FREEDM-32P256 receives new data from the host.
The FREEDM-32P256 is configured, controlled and monitored using the PCI bus
interface. The PCI bus supports 3.3 Volt signaling. The FREEDM-32P256 is
implemented in low power 2.5 Volt 0.25 mm CMOS technology. All non-PCI
FREEDM-32P256 I/O pins are 5 volt tolerant. The FREEDM-32P256 is
packaged in a 329 pin plastic ball grid array (PBGA) package.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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ISSUE 3
FRAME ENGINE AND DATA LINK MANAGER 32P256
PIN DIAGRAM
The FREEDM-32P256 is manufactured in a 329 pin plastic ball grid array
package.
23
22
21
A
RMVCK[2]
RD[16]
B
RFPB[2] RCLK[16]
C
RD[15]
RSTB
D
RCLK[13]
RD[13]
RCLK[14]
RD[17]
E
RD[12]
VDD2V5
RCLK[12]
F
RD[11]
12
11
10
9
8
7
6
5
4
3
2
1
VDD2V5
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
A
RCLK[31]
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
VDD2V5
N.C.
N.C.
N.C.
N.C.
B
RD[31]
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
C
VSS
N.C.
VDD3V3
N.C.
VSS
N.C.
VDD3V3
N.C.
N.C.
N.C.
N.C.
N.C.
D
RD[14]
N.C.
N.C.
VDD2V5
N.C.
E
VSS
VSS
N.C.
N.C.
N.C.
F
G
RD[10]
PCICLKO
PCICLK
N.C.
PCIINTB
G
H
RD[8]
J
RCLK[17] RCLK[19]
RD[18]
RD[20]
19
18
17
16
RD[21]
RD[22]
RD[23]
RD[24]
VDD2V5
RD[19]
15
VDD3V3
RCLK[23]
14
13
RCLK[25] RCLK[27] RCLK[29]
RCLK[22] RFPB[3] RCLK[24] RCLK[26]
RCLK[15] RCLK[18] RCLK[20] RCLK[21] RMVCK[3]
RCLK[10] RCLK[11]
RD[9]
20
RD[25]
RD[27]
VSS
RD[26]
RD[28]
RD[30]
RCLK[28] RCLK[30]
VDD3V3
RD[29]
RCLK[8]
RCLK[9]
RMVCK[1] RFPB[1]
VDD3V3
VDD3V3
AD[31]
REQB
GNTB
H
RCLK[7]
RCLK[6]
RD[6]
RD[7]
AD[29]
AD[27]
AD[28]
AD[30]
J
K
SYSCLK
RCLK[5]
RD[5]
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AD[24]
AD[25]
AD[26]
K
L
RD[4]
RD[3]
RCLK[3]
RCLK[4]
VSS
VSS
VSS
VSS
VSS
CBEB[3]
AD[22]
AD[23]
IDSEL
L
M
VDD2V5
RCLK[2]
RD[2]
VDD3V3
VSS
VSS
VSS
VSS
VSS
VDD3V3
AD[21]
AD[20]
VDD2V5
M
N
RCLK[0]
RD[1]
RCLK[1]
RD[0]
VSS
VSS
VSS
VSS
VSS
AD[16]
AD[18]
AD[19]
AD[17]
N
P
RMV8FPC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CBEB[2]
FRAMEB
IRDYB
P
R
RBD
RMV8DC
RFP8B
RBCLK
STOPB
TRDYB
DEVSELB
LOCKB
R
T
TCK
TMS
TRSTB
VDD3V3
VDD3V3
PERRB
SERRB
PAR
T
U
TFP8B
TDO
TDI
TMV8DC
AD[14]
CBEB[1]
AD[15]
AD[13]
U
V
TFPB[0]
VSS
VSS
AD[10]
AD[12]
AD[11]
V
W
TD[0]
VDD2V5
TCLK[0]
TD[2]
AD[6]
AD[8]
VDD2V5
AD[9]
W
Y
TCLK[1]
TD[1]
TCLK[2]
TD[4]
TMVCK[1]
VDD3V3
TD[12]
N.C.
AD[5]
CBEB[0]
AD[7]
Y
AA
TCLK[3]
TD[3]
TCLK[6]
TFPB[1]
TD[9]
TD[10]
TD[13]
TBCLK
AD[2]
AD[4]
AD[3]
AA
AB
TD[5]
TCLK[4]
TCLK[7]
TCLK[8]
VDD2V5
TD[11]
TCLK[12]
AC
TCLK[5]
TD[6]
TD[7]
TD[8]
23
22
21
20
RFPB[0] RMVCK[0]
TMV8FPC TMVCK[0]
BOTTOM VIEW
VSS
TCLK[15]
VDD3V3
TCLK[17]
VSS
TCLK[14] TMVCK[2]
TD[17]
TCLK[18]
TD[20]
TFPB[2] TCLK[16]
TD[19]
TCLK[19]
TD[15]
TD[16]
TD[18]
VDD2V5
15
14
13
12
TD[14]
TCLK[9] TCLK[10] TCLK[11] TCLK[13]
19
18
17
16
TD[22]
VDD3V3
TD[24]
TCLK[20] TCLK[22] TFPB[3]
TD[21]
TD[23]
10
TD[25]
9
TCLK[27]
VDD3V3
TBD
TCLK[26] TCLK[29] TCLK[30]
TD[27]
TCLK[28]
VDD2V5
TD[31]
PMCTEST
N.C.
AD[1]
AB
TD[26]
TD[28]
TD[29]
TD[30]
TCLK[31]
N.C.
M66EN
AD[0]
AC
8
7
6
5
4
3
2
1
TMVCK[3] TCLK[25]
TCLK[21] TCLK[23] TCLK[24]
11
VSS
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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FRAME ENGINE AND DATA LINK MANAGER 32P256
PIN DESCRIPTION
Table 1 – Line Side Interface Signals (154)
Pin Name
Type
Pin
No.
Function
RCLK[0]
RCLK[1]
RCLK[2]
RCLK[3]
RCLK[4]
RCLK[5]
RCLK[6]
RCLK[7]
RCLK[8]
RCLK[9]
RCLK[10]
RCLK[11]
RCLK[12]
RCLK[13]
RCLK[14]
RCLK[15]
RCLK[16]
RCLK[17]
RCLK[18]
RCLK[19]
RCLK[20]
RCLK[21]
RCLK[22]
RCLK[23]
RCLK[24]
RCLK[25]
RCLK[26]
RCLK[27]
RCLK[28]
RCLK[29]
RCLK[30]
RCLK[31]
Input
N23
N21
M22
L21
L20
K22
J22
J23
G21
G20
F22
F21
E21
D23
D21
C21
B22
A21
C20
A20
C19
C18
B18
D17
B16
A15
B15
A14
C14
A13
C13
B12
The receive line clock signals (RCLK[31:0])
contain the recovered line clock for the 32
independently timed links. Processing of the
receive links are on a priority basis, in
descending order from RCLK[0] to RCLK[31].
Therefore, the highest rate link should be
connected to RCLK[0] and the lowest to
RCLK[31].
For channelised T1/J1 or E1 links, RCLK[n]
must be gapped during the framing bit (for T1/J1
interfaces) or during time-slot 0 (for E1
interfaces) of the RD[n] stream. The FREEDM32P256 uses the gapping information to
determine the time-slot alignment in the receive
stream. RCLK[31:0] is nominally a 50% duty
cycle clock of frequency 1.544 MHz for T1/J1
links and 2.048 MHz for E1 links.
For unchannelised links, RCLK[n] must be
externally gapped during the bits or time-slots
that are not part of the transmission format
payload (i.e. not part of the HDLC packet).
RCLK[2:0] is nominally a 50% duty cycle clock
between 0 and 51.84 MHz. RCLK[31:3] is
nominally a 50% duty cycle clock between 0 and
10 MHz.
The RCLK[n] inputs are invalid and should be
forced to a low state when their associated link
is configured for operation in H-MVIP mode.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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FRAME ENGINE AND DATA LINK MANAGER 32P256
Pin Name
Type
Pin
No.
Function
RD[0]
RD[1]
RD[2]
RD[3]
RD[4]
RD[5]
RD[6]
RD[7]
RD[8]
RD[9]
RD[10]
RD[11]
RD[12]
RD[13]
RD[14]
RD[15]
RD[16]
RD[17]
RD[18]
RD[19]
RD[20]
RD[21]
RD[22]
RD[23]
RD[24]
RD[25]
RD[26]
RD[27]
RD[28]
RD[29]
RD[30]
RD[31]
Input
N20
N22
M21
L22
L23
K21
J21
J20
H23
G22
G23
F23
E23
D22
E20
C23
A22
D20
B21
D19
B20
A19
A18
A17
A16
C16
D15
C15
B14
D13
B13
C12
The receive data signals (RD[31:0]) contain the
recovered line data for the 32 independently
timed links in normal mode (PMCTEST set low).
Processing of the receive links is on a priority
basis, in descending order from RD[0] to
RD[31]. Therefore, the highest rate link should
be connected to RD[0] and the lowest to RD[31].
For H-MVIP links, RD[n] contains 32/128 timeslots, depending on the H-MVIP data rate
configured (2.048 or 8.192 Mbps). When
configured for 2.048 Mbps H-MVIP operation,
RD[31:24], RD[23:16], RD[15:8] and RD[7:0] are
nd
sampled on every 2 rising edge of RMVCK[3],
RMVCK[2], RMVCK[1] and RMVCK[0]
respectively (at the ¾ point of the bit interval).
When configured for 8.192 Mbps H-MVIP
operation, RD[4m] (0£m£7) are sampled on
nd
every 2 rising edge of RMV8DC (at the ¾ point
of the bit interval).
For channelised links, RD[n] contains the 24
(T1/J1) or 31 (E1) time-slots that comprise the
channelised link. RCLK[n] must be gapped
during the T1/J1 framing bit position or the E1
frame alignment signal (time-slot 0). The
FREEDM-32P256 uses the location of the gap
to determine the channel alignment on RD[n].
RD[31:0] are sampled on the rising edge of the
corresponding RCLK[31:0].
For unchannelised links, RD[n] contains the
HDLC packet data. For certain transmission
formats, RD[n] may contain place holder bits or
time-slots. RCLK[n] must be externally gapped
during the place holder positions in the RD[n]
stream. The FREEDM-32P256 supports a
maximum data rate of 10 Mbit/s on an individual
RD[31:3] link and a maximum data rate of 51.84
Mbit/s on RD[2:0]. RD[31:0] are sampled on the
rising edge of the corresponding RCLK[31:0].
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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FRAME ENGINE AND DATA LINK MANAGER 32P256
Pin Name
Type
Pin
No.
Function
RMVCK[0]
RMVCK[1]
RMVCK[2]
RMVCK[3]
Input
P21
H22
A23
C17
The receive MVIP data clock signals
(RMVCK[3:0]) provide the receive data clock for
the 32 links when configured to operate in 2.048
Mbps H-MVIP mode.
When configured for 2.048 Mbps H-MVIP
operation, the 32 links are partitioned into 4
groups of 8, and each group of 8 links share a
common data clock. RMVCK[0], RMVCK[1],
RMVCK[2] and RMVCK[3] sample the data on
links RD[7:0], RD[15:8], RD[23:16] and
RD[31:24] respectively. Each RMVCK[n] is
nominally a 50% duty cycle clock with a
frequency of 4.096 MHz.
RMVCK[n] is ignored and should be tied low
when no physical link within the associated
logical group of 8 links is configured for
operation in 2.048 Mbps H-MVIP mode.
RFPB[0]
RFPB[1]
RFPB[2]
RFPB[3]
Input
P22
H21
B23
B17
The receive frame pulse signals (RFPB[3:0])
reference the beginning of each frame for the 32
links when configured for operation in 2.048
Mbps H-MVIP mode.
When configured for 2.048 Mbps H-MVIP
operation, the 32 links are partitioned into 4
groups of 8, and each group of 8 links share a
common frame pulse. RFPB[0], RFPB[1],
RFPB[2] and RFPB[3] reference the beginning
of a frame on links RD[7:0], RD[15:8], RD[23:16]
and RD[31:24] respectively.
When configured for operation in 2.048 Mbps HMVIP mode, RFPB[n] is sampled on the falling
edge of RMVCK[n]. Otherwise, RFPB[n] is
ignored and should be tied low.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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FRAME ENGINE AND DATA LINK MANAGER 32P256
Pin Name
Type
Pin
No.
Function
RFP8B
Input
R21
The receive frame pulse for 8.192 Mbps H-MVIP
signal (RFP8B) references the beginning of
each frame for links configured for operation in
8.192 Mbps H-MVIP mode.
RFP8B references the beginning of a frame for
any link configured for 8.192 Mbps H-MVIP
operation. Only links 4m (0£m£7) may be
configured for 8.192 Mbps H-MVIP operation.
When one or more links are configured for
8.192 Mbps H-MVIP operation, RFP8B is
sampled on the falling edge of RMV8FPC.
When no links are configured for 8.192 Mbps HMVIP operation, RFP8B is ignored and should
be tied low.
RMV8FPC
Input
P23
The receive 8.192 Mbps H-MVIP frame pulse
clock signal (RMV8FPC) provides the receive
frame pulse clock for links configured for
operation in 8.192 Mbps H-MVIP mode.
RMV8FPC is used to sample RFP8B.
RMV8FPC is nominally a 50% duty cycle, clock
with a frequency of 4.096 MHz. The falling edge
of RMV8FPC must be aligned with the falling
edge of RMV8DC with no more than ±10 ns
skew.
RMV8FPC is ignored and should be tied low
when no physical links are configured for
operation in 8.192 Mbps H-MVIP mode.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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FRAME ENGINE AND DATA LINK MANAGER 32P256
Pin Name
Type
Pin
No.
Function
RMV8DC
Input
R22
The receive 8.192 Mbps H-MVIP data clock
signal (RMV8DC) provides the receive data
clock for links configured to operate in 8.192
Mbps H-MVIP mode.
RMV8DC is used to sample data on RD[4m]
(0£m£7) when link 4m is configured for 8.192
Mbps H-MVIP operation. RMV8DC is nominally
a 50% duty cycle clock with a frequency of
16.384 MHz.
RMV8DC is ignored and should be tied low
when no physical links are configured for
operation in 8.192 Mbps H-MVIP mode.
RBD
Tristate
Output
R23
The receive BERT data signal (RBD) contains
the receive bit error rate test data. RBD reports
the data on the selected one of the receive data
signals (RD[31:0]) and is updated on the falling
edge of RBCLK. RBD may be tristated by
setting the RBEN bit in the FREEDM-32P256
Master BERT Control register low. BERT is not
supported for H-MVIP links.
RBCLK
Tristate
Output
R20
The receive BERT clock signal (RBCLK)
contains the receive bit error rate test clock.
RBCLK is a buffered version of the selected one
of the receive clock signals (RCLK[31:0]).
RBCLK may be tristated by setting the RBEN bit
in the FREEDM-32P256 Master BERT Control
register low. BERT is not supported for H-MVIP
links.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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FRAME ENGINE AND DATA LINK MANAGER 32P256
Pin Name
Type
Pin
No.
Function
TCLK[0]
TCLK[1]
TCLK[2]
TCLK[3]
TCLK[4]
TCLK[5]
TCLK[6]
TCLK[7]
TCLK[8]
TCLK[9]
TCLK[10]
TCLK[11]
TCLK[12]
TCLK[13]
TCLK[14]
TCLK[15]
TCLK[16]
TCLK[17]
TCLK[18]
TCLK[19]
TCLK[20]
TCLK[21]
TCLK[22]
TCLK[23]
TCLK[24]
TCLK[25]
TCLK[26]
TCLK[27]
TCLK[28]
TCLK[29]
TCLK[30]
TCLK[31]
Input
W21
Y23
Y21
AA23
AB22
AC23
AA21
AB21
AB20
AC19
AC18
AC17
AB17
AC16
AA16
Y15
AB14
Y13
AA13
AB12
AA11
AC11
AA10
AC10
AC9
AB8
AA7
Y7
AB6
AA6
AA5
AC4
The transmit line clock signals (TCLK[31:0])
contain the transmit clocks for the 32
independently timed links. Processing of the
transmit links is on a priority basis, in
descending order from TCLK[0] to TCLK[31].
Therefore, the highest rate link should be
connected to TCLK[0] and the lowest to
TCLK[31].
For channelised T1/J1 or E1 links, TCLK[n] must
be gapped during the framing bit (for T1/J1
interfaces) or during time-slot 0 (for E1
interfaces) of the TD[n] stream. The FREEDM32P256 uses the gapping information to
determine the time-slot alignment in the transmit
stream.
For unchannelised links, TCLK[n] must be
externally gapped during the bits or time-slots
that are not part of the transmission format
payload (i.e. not part of the HDLC packet).
TCLK[2:0] is nominally a 50% duty cycle clock
between 0 and 51.84 MHz. TCLK[31:3] is
nominally a 50% duty cycle clock between 0 and
10 MHz. Typical values for TCLK[31:0] include
1.544 MHz (for T1/J1 links) and 2.048 MHz (for
E1 links).
The TCLK[n] inputs are invalid and should be
tied low when their associated link is configured
for operation in H-MVIP mode.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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ISSUE 3
FRAME ENGINE AND DATA LINK MANAGER 32P256
Pin Name
Type
Pin
No.
Function
TD[0]
TD[1]
TD[2]
TD[3]
TD[4]
TD[5]
TD[6]
TD[7]
TD[8]
TD[9]
TD[10]
TD[11]
TD[12]
TD[13]
TD[14]
TD[15]
TD[16]
TD[17]
TD[18]
TD[19]
TD[20]
TD[21]
TD[22]
TD[23]
TD[24]
TD[25]
TD[26]
TD[27]
TD[28]
TD[29]
TD[30]
TD[31]
Output
W23
Y22
W20
AA22
Y20
AB23
AC22
AC21
AC20
AA19
AA18
AB18
Y17
AA17
AB16
AC15
AC14
AA14
AC13
AB13
AA12
AB11
Y11
AB10
Y9
AA8
AC8
AB7
AC7
AC6
AC5
AB4
The transmit data signals (TD[31:0]) contain the
transmit data for the 32 independently timed
links in normal mode (PMCTEST set low).
Processing of the transmit links is on a priority
basis, in descending order from TD[0] to TD[31].
Therefore, the highest rate link should be
connected to TD[0] and the lowest to TD[31].
For H-MVIP links, TD[n] contain 32/128 timeslots, depending on the H-MVIP data rate
configured (2.048 or 8.192 Mbps). When
configured for 2.048 Mbps H-MVIP operation,
TD[31:24], TD[23:16], TD[15:8] and TD[7:0] are
nd
updated on every 2 falling edge of TMVCK[3],
TMVCK[2], TMVCK[1] and TMVCK[0]
respectively. When configured for 8.192 Mbps
H-MVIP operation, TD[4m] (0£m£7) are updated
on every 2nd falling edge of TMV8DC.
For channelised links, TD[n] contains the 24
(T1/J1) or 31 (E1) time-slots that comprise the
channelised link. TCLK[n] must be gapped
during the T1/J1 framing bit position or during
the E1 frame alignment signal (time-slot 0). The
FREEDM-32P256 uses the location of the gap
to determine the channel alignment on TD[n].
TD[31:0] are updated on the falling edge of the
corresponding TCLK[31:0].
For unchannelised links, TD[n] contains the
HDLC packet data. For certain transmission
formats, TD[n] may contain place holder bits or
time-slots. TCLK[n] must be externally gapped
during the place holder positions in the TD[n]
stream. The FREEDM-32P256 supports a
maximum data rate of 10 Mbit/s on an individual
TD[31:3] link and a maximum data rate of 51.84
Mbit/s on TD[2:0].
TD[31:0] are updated on the falling edge of the
corresponding TCLK[31:0] clock.
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Pin Name
Type
Pin
No.
Function
TMVCK[0]
TMVCK[1]
TMVCK[2]
TMVCK[3]
Input
V21
Y19
AA15
AB9
The transmit MVIP data clock signals
(TMVCK[3:0]) provide the transmit data clocks
for the 32 links when configured to operate in
2.048 Mbps H-MVIP mode.
When configured for 2.048 Mbps H-MVIP
operation, the 32 links are partitioned into 4
groups of 8, and each group of 8 links share a
common clock. TMVCK[0], TMVCK[1],
TMVCK[2] and TMVCK[3] update the data on
links TD[7:0], TD[15:8], TD[23:16] and TD[31:24]
respectively. Each TMVCK[n] is nominally a
50% duty cycle clock with a frequency of 4.096
MHz.
TMVCK[n] is ignored and should be tied low
when no physical link within the associated
group of 8 logical links is configured for
operation in 2.048 Mbps H-MVIP mode.
TFPB[0]
TFPB[1]
TFPB[2]
TFPB[3]
Input
V23
AA20
AB15
AA9
The transmit frame pulse signals (TFPB[3:0])
reference the beginning of each frame when
configured for operation in 2.048 Mbps H-MVIP
mode.
When configured for 2.048 Mbps H-MVIP
operation, the 32 links are partitioned into 4
groups of 8, and each group of 8 links share a
common frame pulse. TFPB[0], TFPB[1],
TFPB[2] and TFPB[3] reference the beginning of
a frame on links TD[7:0], TD[15:8], TD[23:16]
and TD[31:24] respectively.
When configured for operation in 2.048 Mbps HMVIP mode, TFPB[n] is sampled on the falling
edge of TMVCK[n]. Otherwise, TFPB[n] is
ignored and should be tied low.
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Pin Name
Type
Pin
No.
Function
TFP8B
Input
U23
The transmit frame pulse for 8.192 Mbps HMVIP signal (TFP8B) references the beginning
of each frame for links configured to operate in
8.192 Mbps H-MVIP mode.
TFP8B references the beginning of a frame for
any link configured for 8.192 Mbps H-MVIP
operation. Only links 4m (0£m£7) may be
configured for 8.192 Mbps H-MVIP operation.
When one or more links are configured for
8.192 Mbps H-MVIP operation, TFP8B is
sampled on the falling edge of TMV8FPC.
When no links are configured for 8.192 Mbps HMVIP operation, TFPB[n] is ignored and should
be tied low.
TMV8FPC
Input
V22
The transmit 8.192 Mbps H-MVIP frame pulse
clock signal (TMV8FPC) provides the transmit
frame pulse clock for links configured for
operation in 8.192 Mbps H-MVIP mode.
TMV8FPC is used to sample TFP8B.
TMV8FPC is nominally a 50% duty cycle, clock
with a frequency of 4.096 MHz. The falling edge
of TMV8FPC must be aligned with the falling
edge of TMV8DC with no more than ±10 ns
skew.
TMV8FPC[n] is ignored and should be tied low
when no physical links are configured for
operation in 8.192 Mbps H-MVIP mode.
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Pin Name
Type
Pin
No.
Function
TMV8DC
Input
U20
The transmit 8.192 Mbps H-MVIP data clock
signal (TMV8DC) provides the transmit data
clock for links configured to operate in 8.192
Mbps H-MVIP mode.
TMV8DC is used to update data on TD[4m]
(0£m£7) when link 4m is configured for 8.192
Mbps H-MVIP operation. TMV8DC is nominally
a 50% duty cycle clock with a frequency of
16.384 MHz.
TMV8DC is ignored and should be tied low
when no physical links are configured for
operation in 8.192 Mbps H-MVIP mode.
TBD
Input
Y5
The transmit BERT data signal (TBD) contains
the transmit bit error rate test data. When the
TBERTEN bit in the BERT Control register is set
high, the data on TBD is transmitted on the
selected one of the transmit data signals
(TD[31:0]). TBD is sampled on the rising edge
of TBCLK. BERT is not supported for H-MVIP
links.
TBCLK
Tristate
Output
AA4
The transmit BERT clock signal (TBCLK)
contains the transmit bit error rate test clock.
TBCLK is a buffered version of the selected one
of the transmit clock signals (TCLK[31:0]).
TBCLK may be tristated by setting the TBEN bit
in the FREEDM-32P256 Master BERT Control
register low. BERT is not supported for H-MVIP
links.
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Table 2 – PCI Host Interface Signals (52)
Pin Name
Type
Pin
No.
Function
PCICLK
Input
G3
The PCI clock signal (PCICLK) provides timing
for PCI bus accesses. PCICLK is a nominally
50% duty cycle, 25 to 66 MHz clock.
PCICLKO
Output
G4
The PCI clock output signal (PCICLKO) is a
buffered version of the PCICLK. PCICLKO may
be used to derive the SYSCLK input.
C/BEB[0]
C/BEB[1]
C/BEB[2]
C/BEB[3]
I/O
Y2
U3
P3
L4
The PCI bus command and byte enable bus
(C/BEB[3:0]) contains the bus command or the
byte valid indications. During the first clock cycle
of a transaction, C/BEB[3:0] contains the bus
command code. For subsequent clock cycles,
C/BEB[3:0] identifies which bytes on the AD[31:0]
bus carry valid data. C/BEB[3] is associated with
byte 3 (AD[31:24]) while C/BEB[0] is associated
with byte 0 (AD[7:0]). When C/BEB[n] is set
high, the associated byte is invalid. When
C/BEB[n] is set low, the associated byte is valid.
When the FREEDM-32P256 is the initiator,
C/BEB[3:0] is an output bus.
When the FREEDM-32P256 is the target,
C/BEB[3:0] is an input bus.
When the FREEDM-32P256 is not involved in
the current transaction, C/BEB[3:0] is tristated.
As an output bus, C/BEB[3:0] is updated on the
rising edge of PCICLK. As an input bus,
C/BEB[3:0] is sampled on the rising edge of
PCICLK.
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Pin Name
Type
Pin
No.
Function
AD[0]
AD[1]
AD[2]
AD[3]
AD[4]
AD[5]
AD[6]
AD[7]
AD[8]
AD[9]
AD[10]
AD[11]
AD[12]
AD[13]
AD[14]
AD[15]
AD[16]
AD[17]
AD[18]
AD[19]
AD[20]
AD[21]
AD[22]
AD[23]
AD[24]
AD[25]
AD[26]
AD[27]
AD[28]
AD[29]
AD[30]
AD[31]
I/O
AC1
AB1
AA3
AA1
AA2
Y3
W4
Y1
W3
W1
V3
V1
V2
U1
U4
U2
N4
N1
N3
N2
M2
M3
L3
L2
K3
K2
K1
J3
J2
J4
J1
H3
The PCI address and data bus (AD[31:0]) carries
the PCI bus multiplexed address and data.
During the first clock cycle of a transaction,
AD[31:0] contains a physical byte address.
During subsequent clock cycles of a transaction,
AD[31:0] contains data.
A transaction is defined as an address phase
followed by one or more data phases. When
Little-Endian byte formatting is selected,
AD[31:24] contain the most significant byte of a
DWORD while AD[7:0] contain the least
significant byte. When Big-Endian byte
formatting is selected. AD[7:0] contain the most
significant byte of a DWORD while AD[31:24]
contain the least significant byte. When the
FREEDM-32P256 is the initiator, AD[31:0] is an
output bus during the first (address) phase of a
transaction. For write transactions, AD[31:0]
remains an output bus for the data phases of the
transaction. For read transactions, AD[31:0] is
an input bus during the data phases.
When the FREEDM-32P256 is the target,
AD[31:0] is an input bus during the first (address)
phase of a transaction. For write transactions,
AD[31:0] remains an input bus during the data
phases of the transaction. For read transactions,
AD[31:0] is an output bus during the data
phases.
When the FREEDM-32P256 is not involved in
the current transaction, AD[31:0] is tristated.
As an output bus, AD[31:0] is updated on the
rising edge of PCICLK. As an input bus,
AD[31:0] is sampled on the rising edge of
PCICLK.
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Pin Name
Type
Pin
No.
Function
PAR
I/O
T1
The parity signal (PAR) indicates the parity of the
AD[31:0] and C/BEB[3:0] buses. Even parity is
calculated over all 36 signals in the buses
regardless of whether any or all the bytes on the
AD[31:0] are valid. PAR always reports the parity
of the previous PCICLK cycle. Parity errors
detected by the FREEDM-32P256 are indicated
on output PERRB and in the FREEDM-32P256
Interrupt Status register.
When the FREEDM-32P256 is the initiator, PAR
is an output for writes and an input for reads.
When the FREEDM-32P256 is the target, PAR is
an input for writes and an output for reads.
When the FREEDM-32P256 is not involved in
the current transaction, PAR is tristated.
As an output signal, PAR is updated on the rising
edge of PCICLK. As an input signal, PAR is
sampled on the rising edge of PCICLK.
FRAMEB
I/O
P2
The active low cycle frame signal (FRAMEB)
identifies a transaction cycle. When FRAMEB
transitions low, the start of a bus transaction is
indicated. FRAMEB remains low to define the
duration of the cycle. When FRAMEB transitions
high, the last data phase of the current
transaction is indicated.
When the FREEDM-32P256 is the initiator,
FRAMEB is an output.
When the FREEDM-32P256 is the target,
FRAMEB is an input.
When the FREEDM-32P256 is not involved in
the current transaction, FRAMEB is tristated.
As an output signal, FRAMEB is updated on the
rising edge of PCICLK. As an input signal,
FRAMEB is sampled on the rising edge of
PCICLK.
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Pin Name
Type
Pin
No.
Function
TRDYB
I/O
R3
The active low target ready signal (TRDYB)
indicates when the target is ready to start or
continue with a transaction. TRDYB works in
conjunction with IRDYB to complete transaction
data phases. During a transaction in progress,
TRDYB is set high to indicate that the target
cannot complete the current data phase and to
force a wait state. TRDYB is set low to indicate
that the target can complete the current data
phase. The data phase is completed when
TRDYB is set low and the initiator ready signal
(IRDYB) is also set low.
When the FREEDM-32P256 is the initiator,
TRDYB is an input.
When the FREEDM-32P256 is the target,
TRDYB is an output. During accesses to
FREEDM-32P256 registers, TRDYB is set high
to extend data phases over multiple PCICLK
cycles.
When the FREEDM-32P256 is not involved in
the current transaction, TRDYB is tristated.
As an output signal, TRDYB is updated on the
rising edge of PCICLK. As an input signal,
TRDYB is sampled on the rising edge of
PCICLK.
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Pin Name
Type
Pin
No.
Function
IRDYB
I/O
P1
The active low initiator ready (IRDYB) signal is
used to indicate whether the initiator is ready to
start or continue with a transaction. IRDYB
works in conjunction with TRDYB to complete
transaction data phases. When IRDYB is set
high and a transaction is in progress, the initiator
is indicating it cannot complete the current data
phase and is forcing a wait state. When IRDYB
is set low and a transaction is in progress, the
initiator is indicating it has completed the current
data phase. The data phase is completed when
IRDYB is set low and the target ready signal
(IRDYB) is also set low.
When the FREEDM-32P256 is the initiator,
IRDYB is an output.
When the FREEDM-32P256 is the target, IRDYB
is an input.
When the FREEDM-32P256 is not involved in
the current transaction, IRDYB is tristated.
IRDYB is updated on the rising edge of PCICLK
or sampled on the rising edge of PCICLK
depending on whether it is an output or an input.
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Pin Name
Type
Pin
No.
Function
STOPB
I/O
R4
The active low stop signal (STOPB) requests the
initiator to stop the current bus transaction.
When STOPB is set high by a target, the initiator
continues with the transaction. When STOPB is
set low, the initiator will stop the current
transaction.
When the FREEDM-32P256 is the initiator,
STOPB is an input. When STOPB is sampled
low, the FREEDM-32P256 will terminate the
current transaction in the next PCICLK cycle.
When the FREEDM-32P256 is the target,
STOPB is an output. The FREEDM-32P256 only
issues transaction stop requests when
responding to reads and writes to configuration
space (disconnecting after 1 DWORD
transferred) or if an initiator introduces wait
states during a transaction.
When the FREEDM-32P256 is not involved in
the current transaction, STOPB is tristated.
STOPB is updated on the rising edge of PCICLK
or sampled on the rising edge of PCICLK
depending on whether it is an output or an input.
IDSEL
Input
L1
The initialization device select signal (IDSEL)
enables read and write access to the PCI
configuration registers. When IDSEL is set high
during the address phase of a transaction and
the C/BEB[3:0] code indicates a register read or
write, the FREEDM-32P256 performs a PCI
configuration register transaction and asserts
the DEVSELB signal in the next PCICLK period.
IDSEL is sampled on the rising edge of PCICLK.
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Pin Name
Type
Pin
No.
Function
DEVSELB
I/O
R2
The active low device select signal (DEVSELB)
indicates that a target claims the current bus
transaction. During the address phase of a
transaction, all targets decode the address on
the AD[31:0] bus. When a target, recognizes the
address as its own, it sets DEVSELB low to
indicate to the initiator that the address is valid.
If no target claims the address in six bus clock
cycles, the initiator assumes that the target does
not exist or cannot respond and aborts the
transaction.
When the FREEDM-32P256 is the initiator,
DEVSELB is an input. If no target responds to
an address in six PCICLK cycles, the FREEDM32P256 will abort the current transaction and
alerts the PCI Host via an interrupt.
When the FREEDM-32P256 is the target,
DEVSELB is an output. DELSELB is set low
when the address on AD[31:0] is recognised.
When the FREEDM-32P256 is not involved in
the current transaction, DEVSELB is tristated.
FREEDM-32P256 is updated on the rising edge
of PCICLK or sampled on the rising edge of
PCICLK depending on whether it is an output or
an input.
LOCKB
Input
R1
The active low bus lock signal (LOCKB) locks a
target device. When LOCKB and FRAME are
set low, and the FREEDM-32P256 is the target,
an initiator is locking the FREEDM-32P256 as an
"owned" target. Under these circumstances, the
FREEDM-32P256 will reject all transaction with
other initiators. The FREEDM-32P256 will
continue to reject other initiators until its owner
releases the lock by forcing both FRAMEB and
LOCKB high. As a initiator, the FREEDM32P256 will never lock a target.
LOCKB is sampled using the rising edge of
PCICLK.
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Pin Name
Type
Pin
No.
Function
REQB
Tristate
Output
H2
The active low PCI bus request signal (REQB)
requests an external arbiter for control of the PCI
bus. REQB is set low when the FREEDM32P256 desires access to the host memory.
REQB is set high when access is not desired.
REQB is updated on the rising edge of PCICLK.
GNTB
Input
H1
The active low PCI bus grant signal (GNTB)
indicates the granting of control over the PCI in
response to a bus request via the REQB output.
When GNTB is set high, the FREEDM-32P256
does not have control over the PCI bus. When
GNTB is set low, the external arbiter has granted
the FREEDM-32P256 control over the PCI bus.
However, the FREEDM-32P256 will not proceed
until the FRAMEB signal is sampled high,
indicating no current transactions are in
progress.
GNTB is sampled on the rising edge of PCICLK.
PCIINTB
OD
Output
G1
The active low PCI interrupt signal (PCIINTB) is
set low when a FREEDM-32P256 interrupt
source is active, and that source is unmasked.
The FREEDM-32P256 may be enabled to report
many alarms or events via interrupts. PCIINTB
returns high when the interrupt is acknowledged
via an appropriate register access.
PCIINTB is an open drain output and is
asynchronous to PCICLK.
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Pin Name
Type
Pin
No.
Function
PERRB
I/O
T3
The active low parity error signal (PERRB)
indicates a parity error over the AD[31:0] and
C/BEB[3:0] buses. Parity error is signalled when
even parity calculations do not match the PAR
signal. PERRB is set low at the cycle
immediately following an offending PAR cycle.
PERRB is set high when no parity error is
detected.
PERRB is enabled by setting the PERREN bit in
the Control/Status register in the PCI
Configuration registers space. Regardless of the
setting of PERREN, parity errors are always
reported by the PERR bit in the Control/Status
register in the PCI Configuration registers space.
PERRB is updated on the rising edge of PCICLK.
SERRB
OD
Output
T2
The active low system error signal (SERRB)
indicates an address parity error. Address parity
errors are detected when the even parity
calculations during the address phase do not
match the PAR signal. When the FREEDM32P256 detects a system error, SERRB is set
low for one PCICLK period.
SERRB is enabled by setting the SERREN bit in
the Control/Status register in the PCI
Configuration registers space. Regardless of the
setting of SERREN, parity errors are always
reported by the SERR bit in the Control/Status
register in the PCI Configuration registers space.
SERRB is an open drain output and is updated
on the rising edge of PCICLK.
M66EN
Input
AC2
The active high 66 MHz mode enable signal
(M66EN) reflects the speed of operation of the
PCI bus. M66EN should be set high for 66 MHz
operation on the PCI bus. M66EN should be set
low for 33 MHz operation on the PCI bus.
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Table 3 – Miscellaneous Interface Signals (58)
Pin Name
Type
Pin
No.
Function
SYSCLK
Input
K23
The system clock (SYSCLK) provides timing for
the core logic. SYSCLK is nominally a 50%
duty cycle, 25 to 45 MHz clock.
RSTB
Input
C22
The active low reset signal (RSTB) signal
provides an asynchronous FREEDM-32P256
reset. RSTB is an asynchronous input. When
RSTB is set low, all FREEDM-32P256 registers
are forced to their default states. In addition,
TD[31:0] are forced high and all PCI output pins
are forced tristate and will remain high or
tristated, respectively, until RSTB is set high.
PMCTEST
Input
AB3
The PMC production test enable signal
(PMCTEST) places the FREEDM-32P256 is test
mode. When PMCTEST is set high, production
test vectors can be executed to verify
manufacturing via the test mode interface
signals TA[11:0], TA[12]/TRS, TRDB, TWRB and
TDAT[15:0]. PMCTEST must be tied low for
normal operation.
TCK
Input
T23
The test clock signal (TCK) provides timing for
test operations that can be carried out using the
IEEE P1149.1 test access port. TMS and TDI
are sampled on the rising edge of TCK. TDO is
updated on the falling edge of TCK.
TMS
Input
T22
The test mode select signal (TMS) controls the
test operations that can be carried out using the
IEEE P1149.1 test access port. TMS is
sampled on the rising edge of TCK. TMS has
an integral pull up resistor.
TDI
Input
U21
The test data input signal (TDI) carries test data
into the FREEDM-32P256 via the IEEE P1149.1
test access port. TDI is sampled on the rising
edge of TCK.
TDI has an integral pull up resistor.
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Pin Name
Type
Pin
No.
Function
TDO
Tristate
Output
U22
The test data output signal (TDO) carries test
data out of the FREEDM-32P256 via the IEEE
P1149.1 test access port. TDO is updated on
the falling edge of TCK. TDO is a tristate output
which is inactive except when scanning of data
is in progress.
TRSTB
Input
T21
The active low test reset signal (TRSTB)
provides an asynchronous FREEDM-32P256
test access port reset via the IEEE P1149.1 test
access port. TRSTB is an asynchronous input
with an integral pull up resistor.
Note that when TRSTB is not being used, it
must be connected to the RSTB input.
NC1-50
Open
These pins must be left unconnected.
Table 4 – Production Test Interface Signals (0 - Multiplexed)
Pin Name
Type
Pin
No.
Function
TA[0]
TA[1]
TA[2]
TA[3]
TA[4]
TA[5]
TA[6]
TA[7]
TA[8]
TA[9]
TA[10]
TA[11]
Input
G23
F23
E23
D22
E20
C23
A22
D20
B21
D19
B20
A19
The test mode address bus (TA[11:0]) selects
specific registers during production test
(PMCTEST set high) read and write accesses.
TA[11:0] replace RD[21:10] when PMCTEST is
set high.
TA[12]
/TRS
Input
A16
The test register select signal (TA[12]/TRS)
selects between normal and test mode register
accesses during production test (PMCTEST set
high). TRS is set high to select test registers
and is set low to select normal registers.
TA[12]/TRS replaces RD[24] when PMCTEST is
set high.
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Pin Name
Type
Pin
No.
Function
TRDB
Input
A18
The test mode read enable signal (TRDB) is set
low during FREEDM-32P256 register read
accesses during production test (PMCTEST set
high). The FREEDM-32P256 drives the test
data bus (TDAT[15:0]) with the contents of the
addressed register while TRDB is low. TRDB
replaces RD[22] when PMCTEST is set high.
TWRB
Input
A17
The test mode write enable signal (TWRB) is set
low during FREEDM-32P256 register write
accesses during production test (PMCTEST set
high). The contents of the test data bus
(TDAT[15:0]) are clocked into the addressed
register on the rising edge of TWRB. TWRB
replaces RD[23] when PMCTEST is set high.
TDAT[0]
TDAT[1]
TDAT[2]
TDAT[3]
TDAT[4]
TDAT[5]
TDAT[6]
TDAT[7]
TDAT[8]
TDAT[9]
TDAT[10]
TDAT[11]
TDAT[12]
TDAT[13]
TDAT[14]
TDAT[15]
I/O
AC14
AA14
AC13
AB13
AA12
AB11
Y11
AB10
Y9
AA8
AC8
AB7
AC7
AC6
AC5
AB4
The bi-directional test mode data bus
(TDAT[15:0]) carries data read from or written to
FREEDM-32P256 registers during production
test. TDAT[15:0] replace TD[31:16] when
PMCTEST is set high.
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Table 5 – Power and Ground Signals (65)
Pin Name
Type
Pin
No.
Function
VDD3V3[1]
VDD3V3[2]
VDD3V3[3]
VDD3V3[4]
VDD3V3[5]
VDD3V3[6]
VDD3V3[7]
VDD3V3[8]
VDD3V3[9]
VDD3V3[10]
VDD3V3[11]
VDD3V3[12]
VDD3V3[13]
VDD3V3[14]
Power
D6
D10
D14
D18
H4
H20
M4
M20
T4
T20
Y6
Y10
Y14
Y18
The VDD3V3[14:1] DC power pins should be
connected to a well decoupled +3.3 V DC
supply. These power pins provide DC current
to the I/O pads.
VDD2V5[1]
VDD2V5[2]
VDD2V5[3]
VDD2V5[4]
VDD2V5[5]
VDD2V5[6]
VDD2V5[7]
VDD2V5[8]
VDD2V5[9]
VDD2V5[10]
VDD2V5[11]
VDD2V5[12]
Power
E2
M1
W2
AB5
AC12
AB19
W22
M23
E22
B19
A12
B5
The VDD2V5[12:1] DC power pins should be
connected to a well decoupled +2.5 V DC
supply. These power pins provide DC current
to the digital core.
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Pin Name
Type
Pin
No.
Function
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
Ground
D8
D12
D16
F4
F20
K4
K20
P4
P20
V4
V20
Y8
Y12
Y16
The VSS[14:1] DC ground pins should be
connected to ground. They provide a ground
reference for the 3.3 V rail. They also provide
a ground reference for the 2.5 V rail.
K10
K11
K12
K13
K14
L10
L11
L12
L13
L14
M10
M11
M12
M13
M14
N10
N11
N12
N13
N14
P10
P11
P12
P13
P14
The VSS[39:15] DC ground pins should be
connected to ground. They provide improved
thermal properties for the 329 PBGA package.
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
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Notes on Pin Description:
1. All FREEDM-32P256 non-PCI inputs and bi-directionals present minimum
capacitive loading and are 5 Volt tolerant. PCI signals conform to the 3.3 Volt
signaling environment.
2. All FREEDM-32P256 non-PCI outputs and bi-directionals have 4 mA drive
capability, except the PCICLKO, RBCLK, TBCLK and RBD outputs which
have 8 mA drive capability.
3. All FREEDM-32P256 outputs can be tristated under control of the IEEE
P1149.1 test access port, even those which do not tristate under normal
operation. All non-PCI outputs and bi-directionals are 5 V tolerant when
tristated.
4. All non-PCI inputs are Schmitt triggered. Inputs TMS, TDI and TRSTB have
internal pull-up resistors.
5. Power to the VDD3V3 pins should be applied before power to the VDD2V5
pins is applied. Similarly, power to the VDD2V5 pins should be removed
before power to the VDD3V3 pins is removed.
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FUNCTIONAL DESCRIPTION
8.1
High Speed Multi-Vendor Integration Protocol (H-MVIP)
H-MVIP defines a synchronous, time division multiplexed (TDM) bus of Nx64
Kbps constant bit rate (CBR) data streams. Each 64 Kbps data stream (timeslot) carries an 8-bit byte of HDLC traffic, as described in the following section,
and is characterised by 8 KHz framing. H-MVIP supports higher bandwidth
applications on existing telephony networks by fitting more time-slots into a 125
ms frame. The FREEDM-32P256 supports H-MVIP data rates of 2.048 Mbps
and 8.192 Mbps with 32 or 128 time-slots per frame and associated clocking
frequencies of 4.096 and 16.384 MHz respectively. Figure 1 shows a diagram of
the H-MVIP protocol supported by the FREEDM-32P256 device.
Figure 1 – H-MVIP Protocol
125 us
Data Clock
(4, 16 MH z)
Fram e Pulse C lock
(4 MHz)
Fram e P ulse
(8 KHz)
Serial Data
B7
B8
TS 31/127
8.2
B1
B2
B8
TS 0
B1
B2
B7
TS 1
B8
TS 31/127
High-Level Data Link Control (HDLC) Protocol
Figure 2 shows a diagram of the synchronous HDLC protocol supported by the
FREEDM-32P256 device. The incoming stream is examined for flag bytes
(01111110 bit pattern) which delineate the opening and closing of the HDLC
packet. The packet is bit de-stuffed which discards a "0" bit which directly
follows five contiguous "1" bits. The resulting HDLC packet size must be a
multiple of an octet (8 bits) and within the expected minimum and maximum
packet length limits. The minimum packet length is that of a packet containing
two information bytes (address and control) and FCS bytes. For packets with
CRC-CCITT as FCS, the minimum packet length is four bytes while those with
CRC-32 as FCS, the minimum length is six bytes. An HDLC packet is aborted
when seven contiguous "1" bits (with no inserted "0" bits) are received. At least
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one flag byte must exist between HDLC packets for delineation. Contiguous flag
bytes, or all ones bytes between packets are used as an "inter-frame time fill".
Adjacent flag bytes may share zeros.
Figure 2 – HDLC Frame
Flag
Information
FCS
Flag
Flag
HDLC Packet
The CRC algorithm for the frame checking sequence (FCS) field is either a
CRC-CCITT or CRC-32 function. Figure 3 shows a CRC encoder block diagram
using the generating polynomial g(X) = 1 + g1X + g2X2 +…+ gn-1Xn-1 + Xn. The
CRC-CCITT FCS is two bytes in size and has a generating polynomial g(X) = 1 +
X5 + X12 + X16. The CRC-32 FCS is four bytes in size and has a generating
polynomial g(X) = 1 + X + X2 + X4 + X5 + X7 + X8 + X10 + X11 + X12 + X16 + X22
+ X23 + X26 + X32. The first FCS bit received is the residue of the highest term.
Figure 3 – CRC Generator
g1
D0
g2
D1
LSB
8.3
gn-1
D2
Message
Dn-1
Parity Check Digits
MSB
Receive Channel Assigner
The Receive Channel Assigner block (RCAS256) processes up to 32 serial links.
Links may be configured to support 2.048 or 8.192 Mbps H-MVIP traffic, to
support T1/J1/E1 channelised traffic or to support unchannelised traffic. When
configured to support 2.048 Mbps H-MVIP traffic, each group of 8 links share a
clock and frame pulse. All links configured for 8.192 Mbps H-MVIP traffic share
a common clock and frame pulse. For T1/J1/E1 channelised traffic or for
unchannelised traffic, each link is independent and has its own associated clock.
For each link, the RCAS256 performs a serial to parallel conversion to form data
bytes. The data bytes are multiplexed, in byte serial format, for delivery to the
Receive HDLC Processor / Partial Packet Buffer block (RHDL256) at SYSCLK
rate. In the event where multiple streams have accumulated a byte of data,
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multiplexing is performed on a fixed priority basis with link #0 having the highest
priority and link #31 the lowest.
From the point of view of the RCAS256, links configured for H-MVIP traffic
behave identically to links configured for T1/J1/E1 channelised or unchannelised
traffic in the back end, only differing on the link side as described herein. First,
the number of time-slots in each frame is programmable to be 32 or 128 and has
an associated data clock frequency that is double the data rate. This provides
more bandwidth per link for applications requiring higher data densities on a
single link. Second, H-MVIP links reference the start of each frame with a frame
pulse, thereby avoiding having to gap the link clock during the framing bits/bytes
of each frame. The frame pulse is provided by an H-MVIP bus master and
ensures that all agents sharing the H-MVIP bus remain synchronized. When
configured for operation in 2.048 Mbps mode, the frame pulse is sampled using
the same clock which samples the data. When configured for operation in 8.192
Mbps H-MVIP mode, the frame pulse is sampled using a separate frame pulse
clock provided by an H-MVIP bus master. The frame pulse clock has a
synchronous timing relationship to the data clock. Third, not all links are
independent. When configured for operation in 2.048 Mbps H-MVIP mode, each
group of 8 links share a clock and a frame pulse. Links 0 through 7, 8 through
15, 16 through 23 and 24 through 31 each share a clock and a frame pulse. Not
all 8 links within each group need to be configured for operation in 2.048 Mbps
H-MVIP mode. However, any link within each logical group of 8 which is
configured for 2.048 Mbps H-MVIP operation will share the same clock and
frame pulse. When configured for operation in 8.192 Mbps H-MVIP mode, links
4m (0£m£7) share a frame pulse, a data clock and a frame pulse clock. Again,
not all eight 4m (0£m£7) links need to be configured for operation in 8.192 Mbps
H-MVIP mode, however, any link which is configured for 8.192 Mbps H-MVIP
operation will share the same frame pulse, data clock and frame pulse clock. If
link 4m is configured for 8.192 Mbps H-MVIP operation, then data transferred on
that link is “spread” over links 4m, 4m+1, 4m+2 and 4m+3 from a channel
assigner point of view. Accordingly, when link 4m is configured for operation in
8.192 Mbps H-MVIP mode, links 4m+1, 4m+2 and 4m+3 must also be
configured for operation in 8.192 Mbps H-MVIP mode. In the back end, the
RCAS256 extracts and processes the time-slots in the same way as channelised
T1/J1/E1 traffic.
Links containing a T1/J1 or an E1 stream may be channelised. Data at each
time-slot may be independently assigned to a different channel. The RCAS256
performs a table lookup to associate the link and time-slot identity with a
channel. T1/J1 and E1 framing bits/bytes are identified by observing the gap in
the link clock which is squelched during the framing bits/bytes. For
unchannelised links, clock rates are limited to 51.84 MHz for links #0 to #2 and
limited to 10 MHz for the remaining links. All data on each link belongs to one
channel. For the case of a mixture of channelised, unchannelised and H-MVIP
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links, the total instantaneous link rate over all the links is limited to 64 MHz. The
RCAS256 performs a table lookup using only the link number to determine the
associated channel, as time-slots are non-existent in unchannelised links.
The RCAS256 provides diagnostic loopback that is selectable on a per channel
basis. The RCAS256 does not support diagnostic loopback for links configured
as H-MVIP. When a channel is in diagnostic loopback, stream data on the
received links originally destined for that channel is ignored. Transmit data of
that channel is substituted in its place.
8.3.1 Line Interface Translator (LIT)
The LIT block translates the information on the 32 physical links into a suitable
format for interpretation by the Line Interface block. The LIT block performs
three functions: data translation, clock translation and frame pulse generation.
When link 4m (0£m£7) is configured for operation in 8.192 Mbps H-MVIP mode,
the LIT block translates the 128 time-slots on link 4m to the Line Interface block
across links 4m, 4m+1, 4m+2 and 4m+3. The LIT block provides time-slots 0
through 31, 32 through 63, 64 through 95 and 96 through 127 to the Line
Interface block on links 4m, 4m+1, 4m+2 and 4m+3 respectively. When link 4m
is configured for operation in 8.192 Mbps H-MVIP mode, data cannot be
received on inputs RD[4m+3:4m+1]. However, links 4m+1, 4m+2 and 4m+3
must be programmed in the RCAS256 Link Configuration register for 8.192 Mbps
H-MVIP operation. When links are configured for operation in 2.048 Mbps HMVIP mode, channelised T1/J1/E1 mode or unchannelised mode, the LIT block
does not perform any translation on the link data.
When a link is configured for operation in H-MVIP mode, the LIT block divides
the appropriate clock (RMVCK[n] for 2.048 Mbps H-MVIP and RMV8DC for
8.192 Mbps H-MVIP) by two and provides this divided down clock to the Line
Interface block. When a link is configured for operation in channelised T1/J1/E1
or unchannelised mode, the LIT block does not perform any translation on the
link clock.
When a link is configured for operation in H-MVIP mode, the LIT block samples
the appropriate frame pulse (RFPB[n] for 2.048 Mbps H-MVIP and RFP8B for
8.192 Mbps H-MVIP) and presents the sampled frame pulse to the Line Interface
block. When a link is configured for operation in channelised T1/J1/E1 or
unchannelised mode, the gapped clock is passed to the LIT block unmodified.
8.3.2 Line Interface
There are 32 identical line interface blocks in the RCAS256. Each line interface
block contains 2 sub-blocks; one supporting channelised T1/J1/E1 streams and
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the other H-MVIP streams. Based on configuration, only one of the sub-blocks
are active at one time; the other is held reset. Each sub-block contains a bit
counter, an 8-bit shift register and a holding register. Each sub-block performs
serial to parallel conversion. Whenever the holding register is updated, a
request for service is sent to the priority encoder block. When acknowledged by
the priority encoder, the line interface would respond with the data residing in the
holding register in the active sub-block.
To support H-MVIP links, each line interface block contains a time-slot counter.
The time-slot counter is incremented each time the holding register is updated.
When a frame pulse occurs, the time-slot counter is initialised to indicate that the
next bit is the most significant bit of the first time-slot.
To support non H-MVIP channelised links, each line interface block contains a
time-slot counter and a clock activity monitor. The time-slot counter is
incremented each time the holding register is updated. The clock activity monitor
is a counter that increments at the system clock (SYSCLK) rate and is cleared by
a rising edge of the receive clock (RCLK[n]). A framing bit (T1/J1) or a framing
byte (E1) is detected when the counter reaches a programmable threshold, in
which case, the bit and time-slot counters are initialised to indicate that the next
bit is the most significant bit of the first time-slot. For unchannelised links, the
time-slot counter and the clock activity monitor are held reset.
8.3.3 Priority Encoder
The priority encoder monitors the line interfaces for requests and synchronises
them to the SYSCLK timing domain. Requests are serviced on a fixed priority
scheme where highest to lowest priority is assigned from the line interface
attached to RD[0] to that attached to RD[31]. Thus, simultaneous requests from
RD[m] will be serviced ahead of RD[n], if m < n. When there are no pending
requests, the priority encoder generates an idle cycle. In addition, once every
fourth SYSCLK cycle, the priority encoder inserts a null cycle where no requests
are serviced. This cycle is used by the channel assigner downstream for host
microprocessor accesses to the provisioning RAMs.
8.3.4 Channel Assigner
The channel assigner block determines the channel number of the data byte
currently being processed. The block contains a 1024 word channel provision
RAM. The address of the RAM is constructed from concatenating the link
number and the time-slot number of the current data byte. The fields of each
RAM word include the channel number and a time-slot enable flag. The time-slot
enable flag labels the current time-slot as belonging to the channel indicted by
the channel number field.
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8.3.5 Loopback Controller
The loopback controller block implements the channel based diagnostic
loopback function. Every valid data byte belonging to a channel with diagnostic
loopback enabled from the Transmit HDLC Processor / Partial Packet Buffer
block (THDL256) is written into a 64 word FIFO. The loopback controller
monitors for an idle time-slot or a time-slot carrying a channel with diagnostic
loopback enabled. If either conditions hold, the current data byte is replaced by
data retrieved from the loopback data FIFO.
8.4
Receive HDLC Processor / Partial Packet Buffer
The Receive HDLC Processor / Partial Packet Buffer block (RHDL256)
processes up to 256 synchronous transmission HDLC data streams. Each
channel can be individually configured to perform flag sequence detection, bit
de-stuffing and CRC-CCITT or CRC-32 verification. The packet data is written
into the partial packet buffer. At the end of a frame, packet status including CRC
error, octet alignment error and maximum length violation are also loaded into
the partial packet buffer. Alternatively, a channel can be provisioned as
transparent, in which case, the HDLC data stream is passed to the partial packet
buffer processor verbatim.
There is a natural precedence in the alarms detectable on a receive packet.
Once a packet exceeds the programmable maximum packet length, no further
processing is performed on it. Thus, octet alignment detection, FCS verification
and abort recognition are squelched on packets with a maximum length violation.
An abort indication squelches octet alignment detection, minimum packet length
violations, and FCS verification. In addition, FCS verification is only performed
on packets that do not have octet alignment errors, in order to allow the
RHDL256 to perform CRC calculations on a byte-basis.
The partial packet buffer is an 32 Kbyte RAM that is divided into 16-byte blocks.
Each block has an associated pointer which points to another block. A logical
FIFO is created for each provisioned channel by programming the block pointers
to form a circular linked list. A channel FIFO can be assigned a minimum of 3
blocks (48 bytes) and a maximum of 2048 blocks (32 Kbytes). The depth of the
channel FIFOs are monitored in a round-robin fashion. Requests are made to
the Receive DMA Controller block (RMAC256) to transfer, to the PCI host
memory, data in channel FIFOs with depths exceeding their associated
threshold.
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8.4.1 HDLC Processor
The HDLC processor is a time-slice state machine which can process up to 256
independent channels. The state vector and provisioning information for each
channel is stored in a RAM. Whenever new channel data arrives, the
appropriate state vector is read from the RAM, processed and written back to the
RAM. The HDLC state-machine can be configured to perform flag delineation,
bit de-stuffing, CRC verification and length monitoring. The resulting HDLC data
and status information is passed to the partial packet buffer processor to be
stored in the appropriate channel FIFO buffer.
The configuration of the HDLC processor is accessed using indirect channel
read and write operations. When an indirect operation is performed, the
information is accessed from RAM during a null clock cycle generated by the
upstream Receive Channel Assigner block (RCAS256). Writing new provisioning
data to a channel resets the channel's entire state vector.
8.4.2 Partial Packet Buffer Processor
The partial packet buffer processor controls the 32 Kbyte partial packet RAM
which is divided into 16 byte blocks. A block pointer RAM is used to chain the
partial packet blocks into circular channel FIFO buffers. Thus, non-contiguous
sections of the RAM can be allocated in the partial packet buffer RAM to create a
channel FIFO. System software is responsible for the assignment of blocks to
individual channel FIFOs. Figure 4 shows an example of three blocks (blocks 1,
3, and 200) linked together to form a 48 byte channel FIFO.
The partial packet buffer processor is divided into three sections: writer, reader
and roamer. The writer is a time-sliced state machine which writes the HDLC
data and status information from the HDLC processor into a channel FIFO in the
packet buffer RAM. The reader transfers channel FIFO data from the packet
buffer RAM to the downstream Receive DMA Controller block (RMAC256). The
roamer is a time-sliced state machine which tracks channel FIFO buffer depths
and signals the reader to service a particular channel. If a buffer over-run
occurs, the writer ends the current packet from the HDLC processor in the
channel FIFO with an over-run flag and ignores the rest of the packet.
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Figure 4 – Partial Packet Buffer Structure
Partial Packet
Buffer RAM
Block
Pointer RAM
Block 0
16 bytes
Block 0
XX
Block 1
16 bytes
Block 1
0x03
Block 2
16 bytes
Block 2
XX
Block 3
16 bytes
Block 3
0xC8
Block 200
16 bytes
Block 200
0x01
Block 2047
16 bytes
Block 2047
XX
The FIFO algorithm of the partial packet buffer processor is based on a
programmable per-channel transfer size. Instead of tracking the number of full
blocks in a channel FIFO, the processor tracks the number of transactions.
Whenever the partial packet writer fills a transfer-sized number of blocks or
writes an end-of-packet flag to the channel FIFO, a transaction is created.
Whenever the partial packet reader transmits a transfer-size number of blocks or
an end-of-packet flag to the RMAC256 block, a transaction is deleted. Thus,
small packets less than the transfer size will be naturally transferred to the
RMAC256 block without having to precisely track the number of full blocks in the
channel FIFO.
The partial packet roamer performs the transaction accounting for all channel
FIFOs. The roamer increments the transaction count when the writer signals a
new transaction and sets a per-channel flag to indicate a non-zero transaction
count. The roamer searches the flags in a round-robin fashion to decide for
which channel FIFO to request transfer by the RMAC256 block. The roamer
informs the partial packet reader of the channel to process. The reader transfers
the data to the RMAC256 until the channel transfer size is reached or an end of
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packet is detected. The reader then informs the roamer that a transaction is
consumed. The roamer updates its transaction count and clears the non-zero
transaction count flag if required. The roamer then services the next channel
with its transaction flag set high.
The writer and reader determine empty and full FIFO conditions using flags.
Each block in the partial packet buffer has an associated flag. The writer sets
the flag after the block is written and the reader clears the flag after the block is
read. The flags are initialized (cleared) when the block pointers are written using
indirect block writes. The writer declares a channel FIFO overrun whenever the
writer tries to store data to a block with a set flag. In order to support optional
removal of the FCS from the packet data, the writer does not declare a block as
filled (set the block flag nor increment the transaction count) until the first double
word of the next block in channel FIFO is filled. If the end of a packet resides in
the first double word, the writer declares both blocks as full at the same time.
When the reader finishes processing a transaction, it examines the first double
word of the next block for the end-of-packet flag. If the first double word of the
next block contains only FCS bytes, the reader would, optionally, process next
transaction (end-of-packet) and consume the block, as it contains information not
transferred to the RMAC256 block.
8.5
Receive DMA Controller
The Receive DMA Controller block (RMAC256) is a DMA controller which stores
received packet data in host computer memory. The RMAC256 is not directly
connected to the host memory PCI bus. Memory accesses are serviced by a
downstream PCI controller block (GPIC). The RMAC256 and the host exchange
information using receive packet descriptors (RPDs). The descriptor contains
the size and location of buffers in host memory and the packet status information
associated with the data in each buffer. RPDs are transferred from the
RMAC256 to the host and vice versa using descriptor reference queues. The
RMAC256 maintains all the pointers for the operation of the queues. The
RMAC256 provides two receive packet descriptor reference (RPDR) free queues
to support small and large buffers. The RMAC256 acquires free buffers by
reading RPDRs from the free queues. After a packet is received, the RMAC256
places the associated RPDR onto a RPDR ready queue. To minimize host bus
accesses, the RMAC256 maintains a descriptor reference table to store current
DMA information. This table contains separate DMA information entries for up to
256 receive channels.
8.5.1 Data Structures
For packet data, the RMAC256 communicates with the host using Receive
Packet Descriptors (RPD), Receive Packet Descriptor References (RPDR), the
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Receive Packet Descriptor Reference Ready (RPDRR) queue and the Receive
Packet Descriptor Reference Small and Large Buffer Free (RPDRF) queues.
The RMAC256 copies packet data to data buffers in host memory. The RPD,
RPDR, RPDRR queue, and Small and Large RPDRF queues are data structures
which are used to transfer host memory data buffer information. All five data
structures are manipulated by both the RMAC256 and the host computer. The
RPD holds the data buffer size, data buffer address, and packet status
information. The RPDR is a pointer which is used to index into a table of RPDs.
The RPDRR queue and RPDRF queues allow the RMAC256 and the host to
pass RPDRs back and forth. These data structures are described in more detail
in the following sections.
Receive Packet Descriptor
The Receive Packet Descriptors (RPDs) pass buffer and packet information
between the RMAC256 and the host. Both the RMAC256 and the host read and
write information in the RPDs. The host writes RPD fields which describe the
size and address of data buffers in host memory. The RMAC256 writes RPD
fields which provide number of bytes used in each data buffer, RPD link
information, and the status of the received packet. RPDs are stored in host
memory in a Receive Packet Descriptor Table which is described in a later
section. The Receive Packet Descriptor structure is shown in Figure 5.
Figure 5 – Receive Packet Descriptor
Bit 31
0
Data Buf fer Start Address [31 :0]
Bytes In Buffer [15:0]
Reserved (6)
RCC[9:0]
Status [5:0]
Res (1)
Reserved (16)
Offset[1:0]
CE
Reserved (7)
Next R PD Pointer [14:0]
Receive Buff er Size [15 :0]
Table 6 – Receive Packet Descriptor Fields
Field
Data Buffer Start
Address[31:0]
Description
The Data Buffer Start Address[31:0] bits point to the data
buffer in host memory. This field is expected to be
configured by the Host during initialisation.
The Data Buffer Start Address field is valid in all RPDs.
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Field
CE
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Description
The Chain End (CE) bit indicates the end of a linked list of
RPDs. When CE is set to logic one, the current RPD is
the last RPD of a linked list of RPDs. When CE is set to
logic zero, the current RPD is not the last RPD of a linked
list.
The CE bit is valid for all RPDs written by the RMAC256
to the Receive Ready Queue. When a packet requires
only one RPD, the CE bit is set to logic one. The CE bit is
ignored for all RPDs read by the RMAC256 from the
Receive Free Queues, each of which is assumed to point
to only one buffer, i.e. not a chain.
Offset[1:0]
The Offset[1:0] bits indicate the byte offset of the data
packet from the start of the buffer. If this value is nonzero, there will be ‘dummy’ (i.e. undefined) bytes at the
start of the data buffer prior to the packet data proper.
For a linked list of RPDs, only the first RPD's Offset field
is valid. All other RPD Offset fields of the linked list are
set to 0.
Status [5:0]
The Status[5:0] bits indicate the status of the received
packet.
Status[0]
Status[1]
Status[2]
Status[3]
Status[4]
Status[5]
Rx buffer overrun
Packet exceeds max. allowed size
CRC error
Packet Length not an exact no. of bytes
HDLC abort detected
Unused (set to 0)
For a linked list of RPDs, only the last RPD's Status field
is valid. All other RPD Status fields of the linked list are
invalid and should be ignored. When a packet requires
only one RPD, the Status field is valid.
Bytes in Buffer
[15:0]
The Bytes in Buffer[15:0] bits indicate the number of bytes
actually used in the current RPD's data buffer to store
packet data. The count excludes the 'dummy' bytes
inserted as a result of a non-zero Offset field. A count
greater than 32767 bytes indicates a packet that is
shorter than the expected length of the FCS field.
The Bytes in Buffer field is invalid when Status[0] or
Status[4] is asserted .
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Field
Next RPD Pointer
[14:0]
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Description
The Next RPD Pointer[14:0] bits store a RPDR which
enables the RMAC256 to support linked lists of RPDs.
This field, which is only valid when CE is equal to logic
zero, contains the RPDR to the next RPD in a linked list.
The RMAC256 links RPDs when more than one buffer is
needed to store a packet.
The Next RPD Pointer is not valid for the last RPD in a
linked list (when CE=1). When a packet requires only one
RPD, the Next RPD Pointer field is not valid.
RCC[9:0]
The Receive Channel Code (RCC[9:0]) bits are used by
the RMAC256 to associate a RPD with a channel.
For a linked list of RPDs, all the RPDs’ RCC[9:0] fields
are valid. i.e. all contain the same channel value.
Receive Buffer Size The Receive Buffer Size[15:0] bits indicate the size in
[15:0]
bytes of the current RPD's data buffer. This field is
expected to be configured by the Host during initialisation.
The Receive Buffer Size must be a non-zero integer
multiple of sixteen and less than or equal to 32752.
The Receive Buffer Size field is valid in all RPDs.
The Receive Buffer Size and Data Buffer Start Address fields are written only by
the host. The RMAC256 reads these fields to determine where to store packet
data. All other fields are written only by the RMAC256.
Receive Packet Descriptor Table
The Receive Packet Descriptor Table resides in host memory and stores all the
RPDs. The RPD Table can contain a maximum of 32768 RPDs. The base of
the RPD table is user programmable using the Rx Packet Descriptor Table Base
(RPDTB) register. The table is indexed by a Receive Packet Descriptor
Reference (RPDR) which is a 15-bit pointer defining the offset of a RPD from the
table base. Thus, as shown in the following diagram, a RPD can be located by
adding the RPDR to the Rx Packet Descriptor Table Base register.
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Figure 6 – Receive Packet Descriptor Table
RPDTB[31:4] = Rx Packet Descriptor Table Base register
RPDR[14:0] = Receive Packet Descriptor Reference
RPD_ADDR[31:0] = Receive Packet Descriptor Address
Bit 31
Bit 0
RPDTB[31:4]
0000
+
RPDR[14:0]
0000
=
RPD_ADDR[31:0]
Bit 31
RPDTB
Bit 0
RPD 1
RPD_ADDR
Dword 0
Dword 1
Dword 2
Dword 3
Dword 0
RPD 2
Dword 3
Dword 0
RPD 32768
Dword 3
The Receive Packet Descriptor Table resides in host memory. The Rx Packet
Descriptor Table Base register resides in the RMAC256; this register is initialised
by the host. The RPDRs reside in host memory and are accessed using receive
packet queues which are described in the next section.
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Receive Packet Queues
Receive Packet Queues are used to transfer RPDRs between the host and the
RMAC256. There are three queues: a RPDR Large Buffer Free Queue
(RPDRLFQ), a RPDR Small Buffer Free Queue (RPDRSFQ) and a RPDR Ready
Queue (RPDRRQ). The free queues contain RPDRs referencing RPDs that
define free buffers. The ready queue contains RPDRs referencing RPDs that
define buffers ready for host processing. The RMAC256 pulls RPDRs from the
free queues when it needs free data buffers. The RMAC256 places an RPDR
onto the ready queue after it has filled the buffers with data from each complete
packet. The host removes RPDRs from the ready queue to process the data
buffers. The host places the RPDRs back onto the free queues after it finishes
reading the data from the buffers.
When starting to process a packet, the RMAC256 uses a small buffer RPD to
store the first buffer of packet data. If the packet data requires more than one
buffer, the RMAC256 uses large buffer RPDs to store the remainder of the
packet. The RMAC256 links together all the RPDs required to store the packet
and returns the RPDR associated with the first RPD onto the ready queue.
All receive packet queues reside in host memory and are defined by the Rx
Queue Base (RQB) register and index registers which reside in the RMAC256.
The Rx Queue Base is the base address for the receive packet queues. Each
packet queue has four index registers which define the start and end of the
queue and the read and write locations of the queue. Each index register is 16
bits in length and defines an offset from the Rx Queue Base. Thus, as shown in
the Figure 7, the host address of a RPDR is calculated by adding the index
register to the Rx Queue Base register. The host initializes the Rx Queue Base
register and all the index registers. When an entity (either the RMAC256 or the
host) removes elements from a queue, the entity updates the read pointer for
that queue. When an entity (either the RMAC256 or the host) places elements
onto a queue, the entity updates the write pointer for that queue.
The read index for each queue points to the last valid RPDR read while the write
index points to where the next RPDR can be written. The start index points to the
first valid location within the queue; an RPDR can be written to this location.
However, the end index points to a location that is beyond a queue; an RPDR
can not be written to this location. Note however, the start index of one queue
can be set to the end index of another queue. A queue is empty when the read
index is one less than the write index; a queue is also empty if the read index is
one less than the end index and the write index equals the start index. A queue is
full when the read index is equal to the write index. Figure 7 shows the RPDR
reference queues.
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Figure 7 – RPDRF and RPDRR Queues
Receive Packet Descriptor (RPD) Reference Queues
Base Address:
RQB[3 1:2] = Rx Q ueue Base register
Index Registers:
Large Buffer Free Q ueue:
Sm all Bu ffer Free Queue:
RPDRLFQS[15:0] = RPDR L arge Free Queue Start register
RPDRSFQS[15:0] = RPDR Sm all F ree Queue Start register
RPDRSFQW [15:0] = RPD R Sm all Free Queue W rite register
RPDRLFQW [15:0] = RPD R Large F ree Queue W rite regis ter
RPDRLFQ R[15:0 ] = R PDR Large Free Queu e Read register
RPDRLFQE [15:0] = RPD R Large F ree Qu eue End register
RPDRSFQ R[15:0] = R PDR Sm all Free Queue Read register
RPDRSFQE [15:0] = RPDR Sm all Free Queue End register
Ready Q ueue:
RPDRRQS[15:0] = RPDR R eady Q ueue Start register
RPDRRQ W [15:0] = RPDR Ready Q ueue W rite register
RPDRRQ R[15:0] = R PDR R eady Q ueue Read register
RPDRRQ E[15:0 ] = RPDR Ready Queue End register
Base Address
+ Index Register
------------------------Host Address
RQB[31:2]
+
Index[1 5:0 ]
00
00
AD[31:0]
Rx Packet Descriptor Reference Queue Mem ory Map
RPDRRQS
RPDRRQR
Bit 31
Bit 0
Status + R PDR
Status + R PDR
Status + R PDR
Host Mem ory
RPDRRQW
Status + R PDR
Status + R PDR
Status + R PDR
RPDRRQE
RQB
RPDRLF QS
RPDRLF QR
RPDR
RPD R eference Queues
RPDR
RPDR
RPDRLF QW
RPDRLFQE
RPDRSFQS
RPDRSFQR
RPDR
RPDR
RPDR
RPDR
RPDR
RPDR
Valid R PDR
RPDRSFQW
RPDR
RPDR
RPDRSFQE
RPDR
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Note that the maximum value to which an end pointer may be set is FFFF hex,
resulting in a maximum offset from the queue base address of (4*(FFFF-1)) =
3FFF8 hex. An end pointer must not be set to 0 hex in an attempt to include
offset 3FFFC hex in a queue.
As shown in Figure 7, the ready queue elements have a status field as well as an
RPDR field. The RMAC256 fills in the status field to mark whether a packet was
successfully received or not. The host reads the status field. The ready queue
element is shown in Table 7 below along with the definition of the status bits.
If the RMAC256 requires a buffer of a particular size (i.e. small or large) and no
RPDR is available in the corresponding free queue, a RPDR from the other free
queue is substituted. The host may, therefore, force the RMAC256 to store
received data in buffers of only one size by setting one of the free queues to zero
length, i.e. by setting the start and end index registers of one of the queues to
equal values. If the RMAC256 requires a buffer and neither free queue contains
RPDRs, an RPQ_ERRI interrupt is generated.
Table 7 – RPDRR Queue Element
Bit 16
Bit 0
STATUS[1:0]
RPDR[14:0]
Field
Description
STATUS[1:0]
The encoding for the status field is as follows:
00 –
01 –
10 –
11 –
RPDR[14:0]
Successful reception of packet.
Unsuccessful reception of packet.
Unprovisioned partial packet.
Partial packet returned due to RAWMAX
limit being reached.
The RPDR[14:0] field defines the offset of the first
RPD in a linked chain of RPDs, each pointing to a
buffer containing the received data.
As described previously, the RMAC256 links RPDs together if more than one
buffer is needed for a packet. The RMAC256 links additional buffer RPDs to the
end of the chain as required until the entire packet is copied to host memory
(provided that the host has not disabled use of both the small and large free
queues by setting one of them to length zero). After storing the packet data, the
RMAC256 places the STATUS+RPDR for the first RPD onto the ready queue.
Only the RPDR associated with the first RPD is placed onto the ready queue. All
other required RPDs are linked to the first RPD as shown in Figure 8.
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Although a STATUS+RPDR only totals to 17 bits, each queue entry is a dword,
i.e. 32 bits. When the RMAC256 block writes a STATUS+RPDR to the ready
queue, it sets the remaining 7 bits in the third byte to zero and the fourth byte is
unmodified.
Figure 8 – RPDRR Queue Operation
Rx Packet Descriptor Reference Ready Queue
RP DRRQ _START _ADDR
Bit 31
Bit 0
buffer
-packet M
RPDR RQ _RE AD_ADDR
RPD - 16 bytes
ST AT US + RPDR
ST AT US + RPDR
RPDRRQ_W RITE_ADDR
ST AT US + RPDR
buffer
RPD - 16 bytes
-packet N
RPD - 16 bytes
buffer
-start of
packet O
RPD - 16 bytes
buffer
-m iddle of
packet O
RPD - 16 bytes
buffer
-end of
packet O
RP DRRQ _EN D_ADDR
Receive Channel Descriptor Reference Table
On a per-channel basis, the RMAC256 caches information such as the current
DMA information in a Receive Channel Descriptor Reference (RCDR) Table.
The RMAC256 can process 256 channels and stores three dwords of
information per channel. This information is cached internally in order to
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decrease the number of host bus accesses required to process each data
packet. The structure of the RCDR table is shown in Figure 9.
Figure 9 – Receive Channel Descriptor Reference Table
Bit 31
RCC 0
Bit 0
Bytes Avail. in Buffer[14:0] RBC[1:0]
Buffer Size[14:0]
R es
V
RPD Pointer[14:0]
Start RPD Pointer[14:0]
DMA Current Address[31:0]
RCC 1
Bytes Avail. in Buffer[14:0] RBC[1:0]
Buffer Size[14:0]
R es
V
RPD Pointer[14:0]
Start RPD Pointer[14:0]
DMA Current Address[31:0]
RCC 671
Bytes Avail. in Buffer[14:0] RBC[1:0]
Buffer Size[14:0]
R es
V
RPD Pointer[14:0]
Start RPD Pointer[14:0]
DMA Current Address[31:0]
Table 8 – Receive Channel Descriptor Reference Table Fields
Field
Description
Bytes Available in
Buffer[15:0]
This field is used to keep track of the number of bytes
available in the current data buffer. The RMAC256
initialises the Bytes Available in Buffer to the Receive
Buffer Size minus the offset at the head of the buffer.
The field is decremented each time a byte is written into
the buffer.
RBC[1:0]
This field is used to keep track of the number of buffers
used when storing ‘raw’ (i.e. non packet delimited) data.
The RMAC256 initialises the RBC field to the value of
the RAWMAX[1:0] field in the RMAC Control Register.
The field is decremented each time a buffer is filled with
data. If the field reaches zero, the chain of RPDs is
placed on the ready queue and a new chain started.
RPD Pointer[14:0]
This field contains the pointer to the current RPD.
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Field
Description
Buffer Size[14:0]
This field contains the size in bytes of the buffer
currently being written to.
V
This bit (Valid) indicates whether a packet is currently
being received on the DMA channel. When the V bit is
set to 1, the other fields in the RCDR table entry for the
DMA channel contain valid information.
Start RPD
Pointer[14:0]
This field contains the pointer to the first RPD for the
packet being received.
DMA Current
Address[31:0]
The DMA Current Address [31:0] bits holds the host
address of the next dword in the current buffer. The
RMAC256 increments this field on each access to the
buffer.
8.5.2 DMA Transaction Controller
The DMA Transaction Controller coordinates the reception of data packets from
the Receive Packet Interface and their subsequent storage in host memory. A
packet may be received over a number of separate transactions, interleaved with
transactions belonging to other DMA channels. As well as sending the received
data to host memory, the DMA Transaction Controller initiates data transactions
of its own for the purposes of maintaining the data structures (queues,
descriptors, etc.) in host memory.
8.5.3 Write Data Pipeline/Mux
The Write Data Pipeline/Mux performs two functions. First, it pipelines receive
data between the RHDL256 block and the GPIC block, inserting enough delay to
enable the DMA Transaction Controller to generate appropriate control signals at
the GPIC interface. Second, it provides a multiplexor to the data out lines on the
GPIC interface, allowing the DMA Transaction Controller to output data relating
to the transactions the controller itself initiates.
8.5.4 Descriptor Information Cache
The Descriptor Information Cache provides the storage for the Receive Channel
Descriptor Reference (RCDR) Table described above (Figure 9).
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8.5.5 Free Queue Cache
The Free Queue Cache block implements the 6 element RPDR Small Buffer
Free Queue cache and the 6 element RPDR Large Buffer Free Queue cache.
These caches are used to store free small buffer and large buffer RPDRs.
Caching RPDRs reduces the number of host bus accesses that the RMAC256
makes.
Each cache is managed independently. The elements of the cache are
consumed one at a time as they are needed by the RMAC256. The RPDR small
buffer cache is reloaded when it is empty and the RMAC256 requires a new
small buffer RPDR. The large buffer RPDR cache is reloaded when it is empty
and the RMAC256 requires a new large buffer RPDR. When reloading either of
the caches, the appropriate cache controller will read up to six new elements.
The cache controller may read fewer than six elements if there are fewer than six
new elements available, or the read pointer index is within six elements of the
end of the free queue. If the read pointer is near the end of the free queue, the
cache controller reads only to the end of the queue and does not start reading
from the top of the queue until the next time a reload is required. To do so would
require two host memory transactions and would be of no benefit.
8.6
PCI Controller
The General-Purpose Peripheral Component Interconnect Controller block
(GPIC) provides a 32-bit Master and Target interface core which contains all the
required control functions for full Peripheral Component Interconnect (PCI) Bus
Revision 2.1 compliance. Communications between the PCI bus and other
FREEDM-32P256 blocks can be made through either an internal
asynchronous16-bit bus or through one of two synchronous FIFO interfaces.
One of the FIFO interfaces is dedicated to servicing the Receive DMA Controller
block (RMAC256) and the other to the Transmit DMA Controller block
(TMAC256).
The GPIC supports a 32-bit PCI bus operating at up to 66 MHz and bridges
between the timing domain of the DMA controllers (SYSCLK) and the timing
domain of the PCI bus (PCICLK). The GPIC is backwards compatible and will
operate at 33 MHz when connected to a 33 MHz PCI bus. By itself, the GPIC
does not generate any PCI bus accesses. All transactions on the bus are
initiated by another PCI bus master or by the core device. The GPIC transforms
each access to and from the PCI bus to the intended target or initiator in the core
device. Except for the configuration space registers and parity
generating/checking, the GPIC performs no operations on the data.
The GPIC is made up of four sections: master state machine, a target state
machine, internal microprocessor bus interface and error/bus controller. The
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target and master blocks operate independent of each other. The error/bus
control block monitors the control signals from the target and master blocks to
determine the state of the PCI I/O pads. This block also generates and/or
checks parity for all data going to or coming from the PCI bus. The internal
microprocessor bus interface block contains configuration and status registers
together with the production test logic for the GPIC block.
8.6.1 Master Machine
The GPIC master machine translates requests from the RMAC256 and
TMAC256 block interfaces into PCI bus transactions. The GPIC initiates four
types of PCI cycles: memory read (burst or single), memory read multiple,
memory read line and memory write (burst or single). The number of data
transfers in any cycle is controlled by the DMA controllers. The maximum burst
size is determined by the particular data path. A read cycle to the RMAC256 is
restricted to a maximum burst size of 8 dwords and a write cycle is limited to a
maximum of 64. The TMAC256 interface has a limit of 64 dwords on a read
cycle and 8 on a write cycle.
In response to a DMA controller requesting a cycle, the GPIC must arbitrate for
control of the PCI bus. In the event that the RMAC256 and TMAC256 request
service simultaneously, the GPIC66 processes the RMAC256 DMA operation
first.
When an external PCI bus arbitrator issues a Grant in response to the Request
from the GPIC, the master state machine monitors the PCI bus to insure that the
previous master has completed its transaction and has released the bus before
beginning the cycle. Once the GPIC has control of the bus, it will assert the
FRAME signal and drive the bus with the address and command. The value for
the address is provided by the selected DMA controller. After the initial data
transfer, the GPIC tracks the address for all remaining transfers in the burst
internally in case the GPIC is disconnected by the target and must retry the
transaction.
The target of the GPIC master burst cycle has the option of stopping or
disconnecting the burst at any point. In the event of a target disconnect the
GPIC will terminate the present cycle and release the PCI bus. If the GPIC is
asserting the REQUEST line at the time of the disconnect, it will remove the
REQUEST for two PCI clock cycles then reassert it. When the PCI bus arbitrator
returns the GRANT, the GPIC will restart the burst access at the next address
and continue until the burst is completed or repeat the sequence if the target
disconnects again.
During burst reads, the GPIC accepts the data without inserting any wait states.
Data is written directly into the read FIFO where the RMAC256 or TMAC256 can
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remove it at its own rate. During burst writes, the GPIC will output the data
without inserting any wait states, but may terminate the transaction early if the
local master fails to fill the write FIFO with data before the GPIC requires it. (If a
write transaction is terminated early due to data starvation, the GPIC will
automatically initiate a further transaction to write the remaining data when it
becomes available.)
Normally, the GPIC will begin requesting the PCI bus for a write transaction
shortly after data starts to be loaded into the write FIFO by the RMAC256 or
TMAC256. The RMAC256, however, is not required to supply a transaction
length when writing packet data and in addition, may insert pauses during the
transfer. In the case of packet data writes by the RMAC256, the GPIC will hold
off requesting the PCI bus until the write FIFO has filled up with a number of
dwords equal to a programmable threshold. If the FIFO empties without
reaching the end of the transition, the GPIC will terminate the current transaction
and restart a new transaction to transfer any remaining data when the RMAC256
signals an end of transaction. Beginning the PCI transaction before all the data
is in the write FIFO allows the GPIC to reduce the impact of the bus latency on
the core device.
Each master PCI cycle generated by the GPIC can be terminated in three ways:
Completion, Timeout or Master Abort. The normal mode of operation of the GPIC
is to terminate after transferring all the data from the master FIFO selected. As
noted above this may involve multiple PCI accesses because of the inability of
the target to accept the full burst or data starvation during writes. After the
completion of the burst transfer the GPIC will release the bus unless another
FIFO is requesting service, in which case if the GRANT is asserted the GPIC will
insert one idle cycle on the bus and then start a new transfer.
The maximum duration of the a master burst cycle is controlled by the value set
in the LATENCY TIMER register in the GPIC Configuration Register block. This
value is set by the host on boot and is loaded into a counter in the GPIC master
state at the start of each access. If the counter reaches zero and the GRANT
signal has been removed the GPIC will release the bus regardless of whether it
has completed the present burst cycle. This type of termination is referred to as
a Master Time-out. In the case of a Master Time-out the GPIC will remove the
REQUEST signal for two PCI clocks and then reassert it to complete the burst
cycle.
If no target responds to the address placed on the bus by the GPIC after 4 PCI
clocks the GPIC will terminate the cycle and flag the cycle in the PCI Command/
Status Configuration Register as a Master Abort. If the Stop on Error enable
(SOE_E) bit is set in the GPIC Command Register, the GPIC will not process any
more requests until the error condition is cleared. If the SOE_E is not set, the
GPIC will discard the REQUEST and indicate to the local master that the cycle is
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complete. This action will result in any write data being lost and any read data
being erroneous.
8.6.2 Master Local Bus Interface
The master local bus is a 32 bit data bus which connects the local master device
to the GPIC. The GPIC contains two local master interface blocks, with one
supporting the RMAC256 and the other the TMAC256. Each local master
interface has been optimised to support the traffic pattern generated by the
RMAC256 or the TMAC256 and are not interchangeable.
The data path between the GPIC and local master device provides a mechanism
to segregate the system timing domain of the core from the PCI bus. Transfers
on each of the RMAC256 and TMAC256 interfaces are timed to its own system
clock. The DMA controllers isolated from all aspects of the PCI bus protocol, and
instead “sees” a simple synchronous protocol. Read or write cycles on the local
master bus will initiate a request for service to the GPIC which will then transfer
the data via the PCI bus.
The GPIC maximises data throughput between the PCI bus and the local device
by paralleling local bus data transfers with PCI access latency. The GPIC allows
either DMA controller to write data independent of each other and independent of
PCI bus control. The GPIC temporarily buffers the data from each DMA
controller while it is arbitrating for control of the PCI bus. After completion of a
write transfer, the DMA controller is then released to perform other tasks. The
GPIC can buffer only a single transaction from each DMA controller.
Read accesses on the local bus are optimised by allowing the DMA controllers
access to the data from the PCI bus as soon as the first data becomes available.
After the initial synchronisation and PCI bus latency data is transferred at the
slower of PCI bus rate or the core logic SYSCLK rate. Once a read transaction
is started, the DMA controller is held waiting for the ready signal while the GPIC
is arbitrating for the PCI bus.
All data is passed between the GPIC and the DMA controllers in little Endian
format and, in the default mode of operation, the GPIC expects all data on the
PCI bus to also be in little Endian format. The GPIC provides a selection bit in
the internal Control register which allows the Endian format of the PCI bus data
to be changed. If enabled, the GPIC will swizzle all packet data on the PCI bus
(but not descriptor references and the contents of descriptors). The swizzling is
performed according to the “byte address invariance” rule, i.e. the only change to
the data is the mirror-imaging of byte lanes.
The interface for the RMAC256 provides for byte addressability of write
transactions whereas the interface for the TMAC256 provides for byte
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addressability of read transactions. Other transactions must be dword aligned.
For byte-addressable transactions, the data transferred between the local device
and the GPIC need not be dword aligned with the data as it is presented on the
PCI bus. The GPIC will perform any byte-realignment required. In order to
complete a transfer involving byte re-alignment, the GPIC may need to add an
extra burst cycle to the PCI transaction.
8.6.3 Target Machine
The GPIC target machine performs all the required functions of a stand alone
PCI target device. The target block performs three main functions. The first is
the target state machine which controls the protocol of PCI target accesses to
the GPIC. The second function is to provide all PCI Configuration registers.
Last, the target block provides a Target Interface to the CBI registers in the other
FREEDM-32P256 blocks.
The GPIC tracks the PCI bus and decodes all addresses and commands placed
on the bus to determine whether to respond to the access. The GPIC responds
to the following types of PCI bus commands only: Configuration read and write,
memory read and write, memory-read-multiple and memory-read-line which are
aliased to memory read and memory-write-and-invalidate which is aliased to
memory write. The GPIC will ignore any access that falls within the address
range but has any other command type.
After accepting a target access as a medium speed device, the FREEDM32P256 inserts one wait state for a configuration read/write and five wait states
for other command types before completing the transaction by asserting TRDYB.
Burst accesses to the GPIC are accepted provided they are of linear type. If a
master makes a memory access to the GPIC with the lower two address bits set
to any value but "00" (linear burst type) the GPIC ignores the cycle. Burst
accesses of any length are accepted, but the FREEDM-32P256 will disconnect if
the master inserts any wait states during the transaction. The FREEDM-32P256
will also disconnect on every read and write access to configuration space after
transferring one Dword of data.
Figure 10 illustrates the GPIC address space.
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Figure 10 – GPIC Address Map
PCI ADDRESS MAP
0B
CBI Registers
Base Address
CBI Registers
8KB
4GB
The GPIC responds with medium timing to master accesses. (i.e. DEVSELB is
asserted 2 PCICLK cycles after FRAMEB asserted). The GPIC inserts five wait
states on reads to the internal CBI register space (six wait states for the 2nd and
subsequent dwords of a burst read). The target machine will only terminate an
access with a Retry if the target is locked and another master tries to access the
GPIC. The GPIC will terminate any access to a non-burst area with a
Disconnect and always with data transferred. The target does not support
delayed transactions. The GPIC will perform a Target-Abort termination only in
the case of an address parity error in an address that the GPIC claims.
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8.6.4 CBI Bus Interface
The CBI bus interface provides access to the CBI address space of the
FREEDM-32P256 blocks. The CBI address space is set by the associated BAR
in the PCI Configuration registers.
Write transfers to the CBI space always write all 32 bits provided that at least
one byte enable is asserted. A write command with all byte enables negated will
be ignored. Read transfers always return the 32 bits regardless of the status of
the byte enables, as long as at least one byte enable is asserted. A read
command with all byte enables negated will be ignored.
8.6.5 Error / Bus Control
The Error/Bus Control block monitors signals from both the Target block and
Master Block to determine the direction of the PCI bus pads and to generate or
check parity. After reset, the GPIC sets all bi-directional PCI bus pads to inputs
and monitors the bus for accesses. The Error/Bus control unit remains in this
state unless either the Master requests the PCI bus or the Target responds to a
PCI Master Access. The Error/Bus control unit decodes the state of each state
machine to determine the direction of each PCI bus signal.
All PCI bus devices are required to check and generate even parity across
AD[31:0] and C/BEB[3:0] signals. The GPIC generates parity on Master address
and write data phases; the target generates parity on read data phases. The
GPIC is required to check parity on all PCI bus phases even if it is not
participating in the cycle. But, the GPIC will report parity errors only if the GPIC
is involved in the PCI cycle or if the GPIC detects an address parity error or data
parity is detected in a PCI special cycle. The GPIC updates the PCI
Configuration Status register for all detected error conditions.
8.7
Transmit DMA Controller
The Transmit DMA Controller block (TMAC256) is a DMA controller which
retrieves packet data from host computer memory for transmission. The minimum
packet data length is two bytes. The TMAC256 communicates with the host
computer bus through the master interface connected to PCI Controller block
(GPIC) which translates host bus specific signals from the host to the master
interface format. The TMAC256 uses the master interface whenever it wishes to
initiate a host bus read or write; in this case, the TMAC256 is the initiator and the
host memory is the target.
The TMAC256 and the host exchange information using transmit descriptors
(TDs). The descriptor contains the size and location of buffers in host memory
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and the packet status information associated with the data in each buffer. TDs
are transferred from the TMAC256 to the host and vice versa using descriptor
reference queues. The TMAC256 maintains all the pointers for the operation of
the queues. The TMAC256 acquires buffers with data ready for transmission by
reading TDRs from a TDR ready queue. After a packet has been transmitted,
the TMAC256 places the associated TDR onto a TDR free queue.
To minimise host bus accesses, the TMAC256 maintains a descriptor reference
table to store current DMA information. This table contains separate DMA
information entries for up to 256 transmit channels. The TMAC256 also
performs per-channel sorting of packets received in the TDR ready queue to
eliminate head-of-line blocking.
8.7.1 Data Structures
The TMAC256 communicates with the host using Transmit Descriptors (TD),
Transmit Descriptor References (TDR), the Transmit Data Reference Ready
(TDRR) queue and the Transmit Data Reference Free (TDRF) queue.
The TMAC256 reads packet data from data buffers in host memory. The TD,
TDR, TDRR queue, and TDRF queue are data structures which are used to
transfer host memory data buffer information. All four data structures are
manipulated by both the TMAC256 and the host computer. The TD holds the
data buffer size, data buffer address, and other packet information. The TDR is
a pointer which is used to index into a table of TDs. The TDRR queue and TDRF
queue allow the TMAC256 and the host to pass TDRs back and forth. These
data structures are described in more detail in the following sections.
Transmit Descriptor
The Transmit Descriptors (TDs) pass buffer and packet information between the
TMAC256 and the host. Both the TMAC256 and the host read and write
information in the TDs. TDs are stored in host memory in a Transmit Descriptor
Table. The Transmit Descriptor structure is shown in Figure 11.
Figure 11 – Transmit Descriptor
Bit 31
0
Data Buf fer Start Address [31:0]
Bytes In Buffer [15:0]
V
TM AC Next TD P ointer[14:0]
Reserved (16)
P AB T IOC CE Res (2)
M
TCC[9:0]
H ost Next TD P ointer[14 :0]
Transm it Buf fer Size[15:0]
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Table 9 – Transmit Descriptor Fields
Field
Description
Data Buffer Start
Address [31:0]
The Data Buffer Start Address[31:0] bits point to the
data buffer in host memory.
The Data Buffer Start Address field is valid in all TDs
Bytes In Buffer [15:0]
The Bytes In Buffer[15:0] field is used by the host to
indicate the total number of bytes to be transmitted in
the current TD. Zero length buffers are illegal.
P
The Priority bit is set by the host to indicate the
priority of the associated packet in a two level quality
of service scheme. Packets with its P bit set high are
queued in the high priority queue in the TMAC256.
Packets with the P bit set low are queued in the low
priority queue. Packets in the low priority queue will
not begin transmission until the high priority queue is
empty.
ABT
The Abort (ABT) bit is used by the host to abort the
transmission of a packet. When ABT is set to logic 1,
the packet will be aborted after all the data in the
buffer has been transmitted. If ABT is set to logic 1 in
the current TD, the M bit must be set low and the CE
bit must be set to high.
IOC
The Interrupt On Complete (IOC) bit is used by the
host to instruct the TMAC256 to interrupt the host
when the current TD's data buffer has been read.
When IOC is logic 1, the TMAC256 asserts the IOCI
interrupt when the data buffer has been read.
Additionally, the Free Queue FIFO will be flushed. If
IOC is logic zero, the TMAC256 will not generate an
interrupt and the Free Queue FIFO will operate
normally.
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Field
Description
CE
The Chain End (CE) bit is used by the host to indicate
the end of a linked list of TDs presented to the
TMAC256. The linked list can contain one or more
packets as delineated by the M bit (see above).
When CE is set to logic 1, the current TD is the last
TD of a linked list of TDs. When CE is set to logic 0,
the current TD is not the last TD of a linked list.
When the current TD is not the last of the linked list,
the Host Next TD Pointer[14:0] field is valid,
otherwise the field is not valid.
Note: When CE is set to logic 1, the only valid value
for M is logic 0.
Note: When presenting raw (i.e. unpacketised) data
for transmission, the host should code the M and CE
bits as for a single packet chain, i.e. M=1, CE=0 for
all TDs except the last in the chain and M=0, CE=1
for the last TD in the chain.
TCC[9:0]
The Transmit Channel Code (TCC[9:0]) bits are used
by the host to associate a channel with a TD pointed
to by a TDR.
All TCC[9:0] fields in a linked list of TDs must be set
to the same value.
V
The V bit is used to indicate that the TMAC Next TD
Pointer field is valid. When set to logic 1, the TMAC
Next TD Pointer[14:0] field is valid. When V is set to
logic 0, the TMAC Next TD Pointer[14:0] field is
invalid. The V bit is used by the host to reclaim data
buffers in the event that data presented to the
TMAC256 is returned to the host due to a channel
becoming unprovisioned. The V bit is expected to be
initialised to logic 0 by the host.
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Field
Description
TMAC Next TD Pointer
[14:0]
The TMAC Next TD Pointer[14:0] bits are used to
store TDRs which permits the TMAC256 to create
linked lists of TDs passed to it via the TDRR queue.
The TDs are linked with other TDs belonging to the
same channel and same priority level. In the case
that data presented to the TMAC256 is returned to
the host due to a channel becoming unprovisioned, a
TDR pointing to the start of the per-channel linked list
of TDs is placed on the TDRF queue. It is the
responsibility of the host to follow the TMAC256 and
host links in order to recover all the buffers.
M
The More (M) bit is used by the host to support
packets that require multiple TDs. If M is set to
logic 1, the current TD is just one of several TDs for
the current packet. If M is set to logic 0, this TD
either describes the entire packet (in the single TD
packet case) or describes the end of a packet (in the
multiple TD packet case).
Note: When M is set to logic 1, the only valid value
for CE is logic 0.
Host Next TD Pointer
[14:0]
The Host Next TD Pointer[14:0] bits are used to store
TDRs which permits the host to support linked lists of
TDs. As described above, linked lists of TDs are
terminated by setting the CE bit to logic 1. Linked
lists of TDs are used by the host to pass multiple TD
packets or multiple packets associated with the same
channel and priority level to the TMAC256.
Transmit Buffer Size
[15:0]
The Transmit Buffer Size[15:0] field is used to
indicate the size in bytes of the current TD's data
buffer. (N.B. The TMAC256 does not make use of
this field.)
Transmit Descriptor Table
The Transmit Descriptor Table, which resides in host memory, contains all of the
Transmit Descriptors referenced by the TMAC256. To access a TD, the
TMAC256 takes a TDR from a TDRR queue or from the TCDR table and adds
16 times its value (because each TD is 16 bytes in size) to the Transmit
Descriptor Table Base (TDTB) pointer to form the actual address of the TD in
host memory. Each TD must reside in the Transmit Descriptor Table. The
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Transmit Descriptor Table can contain a maximum of 32768 TDs. The base of
the Transmit Descriptor Table is user programmable using the TMAC Tx
Descriptor Table Base register. Thus, as shown below, each TD can be located
using a Transmit Descriptor Reference (TDR) combined with the TMAC Tx
Descriptor Table Base register.
Figure 12 – Transmit Descriptor Table
TDTB[31:4] = Tx Descriptor Table Base register
TDR[14:0] = Transmit Descriptor Reference
TD_ADDR[31:0] = Transmit Descriptor Address
Bit 31
Bit 0
TDTB[31:4]
0000
+
TDR[14:0]
0000
=
TD_ADDR[31:0]
Bit 31
TDTB
Bit 0
TD1
TD_ADDR
Dword 0
Dword 1
Dword 2
Dword 3
Dword 0
TD2
Dword 3
Dword 0
TD 32768
Dword 3
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Transmit Queues
Pointers to the transmit descriptors (TDs) containing packet(s) ready for
transmission are passed from the host to the TMAC256 using the Transmit
Descriptor Reference Ready (TDRR) queue, which resides in host memory.
Pointers to transmit descriptor structures whose buffers have been read by the
TMAC256 are passed from the TMAC256 to the host using the Transmit
Descriptor Reference Free (TDRF) queue, which also resides in host memory.
The TMAC256 contains a Free Queue cache which can store up to six TDRs. If
caching is enabled, free TDRs are written into the TDRF queue six at a time, to
reduce the number of host memory accesses. The Free Queue cache is flushed
to the TDRF queue if the Interrupt On Completion (IOC) bit is set in the TD,
which sends the corresponding TDR directly to the TDRF queue. The Free
Queue cache is also flushed to the TDRF queue if the FQFLUSH register bit is
set high. The FQFLUSH register bit is self clearing.
The queues, shown in Figure 13 are defined by a common base pointer residing
in the Transmit Queue Base register and eight offset pointers, four per queue.
For each queue, two pointers define the start and the end of the queue, and two
pointers keep track of the current read and write locations within the queue. The
read pointer for each queue points to the offset of the last valid TDR read, and
the write pointer points to the offset where next TDR can be written. The end of
a queue is not a valid location for a TDR to be read or written. A queue is empty
when the read pointer is one less than the write pointer or if the read pointer is
one less than the end pointer and the write pointer equals the start pointer. A
queue is full when the read pointer is equal to the write pointer. Each queue
element is 32 bits in size, but only the least significant 18 bits are valid. The 18
least significant bits consist of a 15-bit TDR and three status bits for the TD
pointed at by this TDR. The status bits are used by the TMAC256 to inform the
host of the success or failure of transmission (see Table 10). When the
TMAC256 writes TDRs to the TDRF queue, it sets bits [23:18] of the queue
element to 0 and leaves bits [31:24] unaltered. Once a TDR is placed on the
TDRF queue, the FREEDM-32P256 will make no further accesses to the TD nor
the associated buffer.
Note that the maximum value to which an end pointer may be set is FFFF hex,
resulting in a maximum offset from the queue base address of (4*(FFFF-1)) =
3FFF8 hex. An end pointer must not be set to 0 hex in an attempt to include
offset 3FFFC hex in a queue.
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Figure 13 – TDRR and TDRF Queues
Transmit Descriptor Referance Queues
Base Address:
TQB[31:2] = Tx Queue Base register
Index Registers:
Ready:
TDRRQS[15:0] =
TDRRQW[15:0] =
TDRRQR[15:0] =
TDRRQE[15:0] =
TDR Ready Queue Start register
TDR Ready Queue Write register
TDR Ready Queue Read register
TDR Ready Queue End register
Base Address
+ Index Register
------------------------PCI Address
Free:
TDRFQS[15:0] =
TDRFQW[15:0] =
TDRFQR[15:0] =
TDRFQE[15:0] =
TDR Free Queue Start register
TDR Free Queue Write register
TDR Free Queue Read register
TDR Free Queue End register
TQB[31:2]
+
00
Index[15:0] 00
AD[31:0]
Tx Descriptor Reference Queue Memory Map
TDRFQS
TDRFQR
Bit 31
Bit 0
Status + TDR
PCI Host Memory
Status + TDR
Status + TDR
Status + TDR
TDRFQW
Status + TDR
Status + TDR
TQB
TDR Reference Queues
TDRFQE
TDRRQS
TDRRQR
TDR
TDR
TDR
TDRRQW
TDRRQE
TDR
TDR
TDR
Valid TDR
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Table 10 – Transmit Descriptor Reference
Bit 17
Bit 0
STATUS[2:0]
TDR[14:0]
Field
Description
Status[2:0]
The TMAC256 fills in the Status field to indicate to the
host the results of processing the TD. The encoding is:
TDR[14:0]
Status[1:0]
Description
00
01
10
11
Last or only buffer of packet, buffer read.
Buffer of partial packet, buffer read.
Unprovisioned channel, buffer not read.
Malformed packet (e.g. Bytes In Buffer field
set to 0), buffer not read.
Status[2]
Description
0
1
No underflow detected.
Underflow detected.
The TDR[14:0] field contains the offset of the TD
returned.
If a TDR is returned to the host with the status field set to “10” (unprovisioned
channel), the TDR may point to a binary tree of TDs and buffers (as indicated by
the CE and V bits in the TDs). It is the responsibility of the host to traverse the
tree to reclaim all the buffers. If a TDR is returned to the host with the status
field set to any other value, the TDR will only point to one TD and buffer
regardless of the values of V and CE in that TD.
The underflow status bit (Status[2]) is normally attached to the TDR belonging to
a packet experiencing underflow. For long packets spanning multiple buffers,
underflow is reported only once at the first available TDR of that channel. All
subsequent TDRs of that packet will be returned normally without the underflow
status. In rare cases, due to internal buffering by the FREEDM-32P256, a
packet may experience underflow at the very end of a packet, just as the TDR is
being returned to the TDR free queue. The underflow status will then be
reported in the first TDR of the immediate next packet of that channel. Because
of the uncertainty with the reporting of underflows between the current verse the
subsequent packet, the underflow status should only be used to gather
performance statistics on channels and not for initiating packet specific
responses such as retransmission.
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Transmit Channel Descriptor Reference Table
The TMAC256 maintains a Transmit Channel Descriptor Reference (TCDR)
table in which is stored certain information relating to DMA activity on each
channel together with TD pointers which are used by the TMAC256 to sort
packet chains supplied by the host into per-channel linked lists (see below). The
caching of DMA-related information reduces the number of host bus accesses
required to process each data packet, while the sorting into per-channel linked
lists eliminates head of line blocking. Each channel is provided with two entries
in the TCDR table, one for high priority packets (Pri 1) and one for low priority
packets (Pri 0). The structure of the TCDR table is shown in Figure 14 below.
Figure 14 – Transmit Channel Descriptor Reference Table
Bit 0
Bit 33
TCC 0, Pri 0
Reserved (12)
PiP
Last TD Pointer [14:0]
Reserved (12)
TCC 1, Pri 0
PiP
Current TD Pointer [14:0]
Res
Host TD Pointer [14:0]
V
Next TD Pointer [14:0]
D
Current TD Pointer [14:0]
Res
Host TD Pointer [14:0]
NA
Abrt IOC
M CE A
V
Next TD Pointer [14:0]
D
Current TD Pointer [14:0]
Res
Host TD Pointer [14:0]
DMA Current Address[31:0]
Res
U
M CE A
Bytes to Tx [15:0]
Res
Res
Abrt IOC
Last TD Pointer [14:0]
Reserved (12)
TCC 671, Pri 1
D
DMA Current Address[31:0]
Res
U
NA
Bytes to Tx [15:0]
Res
Res
M CE A
DMA Current Address[31:0]
Res
U
Abrt IOC
Bytes to Tx [15:0]
Res
Res
NA
PiP
Last TD Pointer [14:0]
V
Next TD Pointer [14:0]
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Table 11 – Transmit Channel Descriptor Reference Table Fields
Field
Description
NA
Indicates that a ‘null abort’ is to be sent to the
downstream block when it next requests data on this
channel. The NA bit is set if a mal-formed TD is
encountered while searching down a host chain.
ABRT
A copy of the ABRT bit in the TD currently being read.
IOC
A copy of the IOC bit in the TD currently being read.
M
A copy of the M bit in the TD currently being read.
CE
A copy of the CE bit in the TD currently being read.
A
Indicates if this channel is active (i.e. provisioned). If
the channel is active, the A bit is set to logic 1. If the
channel is inactive, the A bit is set to logic 0.
D
Indicates whether the linked list of packets for this
channel is empty or not. If the D bit is set to logic 1,
the list is not empty and the current TD pointer field is
valid (i.e., it points to a valid TD). If the D bit is set to
logic 0, the list is empty and the current TD pointer field
is invalid.
Current TD Pointer
[14:0]
Offset to the TD currently being read. (See Figure 15)
Bytes To Tx[15:0]
The Bytes to Tx[15:0] bits are used to indicate the total
number of bytes that remain to be read in the current
buffer. Each access to the data buffer decrements this
value. A value of zero in this field indicates the buffer
has been completely read.
Host TD Pointer [14:0] A copy of the Host Next TD Pointer field of the TD
currently being read, i.e. a pointer to the next TD in the
chain currently being read. (See Figure 15)
DMA Current
Address[31:0]
The DMA Current Address [31:0] bits hold the address
of the next dword in the current buffer. This field is
incremented on each access to the buffer.
U
Indicates that an underflow has occurred on this
channel. This bit is set in response to an underflow
indication for the downstream THDL256 block and is
cleared when a TDR is written to the TDR Free Queue
(or to the free queue cache).
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Field
Description
PiP
The Packet Transfer in Progress bit indicates that a
packet is currently being transmitted on this channel at
this priority level.
Last TD Pointer [14:0]
Offset to the head of the last host-linked chain of TDs
to be read. (See Figure 15)
V
Indicates if the linked list of packets for this channel
contains more than one host-linked chain (See Figure
15). If the V bit is set to logic 1, the list contains more
than one chain and the next and last TD pointer fields
are valid. If the V bit is set to logic 0, the list is either
empty or contains only one host-linked chain and the
next and last TD pointer fields are invalid.
Next TD Pointer [14:0] Offset to the head of the next host-linked chain of TDs
to be read. (See Figure 15)
Transmit Descriptor Linking
As described above, the TCDR table contains pointers which the TMAC256 uses
to construct linked lists of data packets to be transmitted. After the host places a
new TDR in the TDR Ready queue, the TMAC256 retrieves the TDR and links it
to the TD pointed at by the Last TD Pointer field. The TMAC256 may create up
to 1,344 linked lists, viz. a high-priority list and a low-priority list for each DMA
channel. Whenever a new data packet is requested by the downstream block,
the TMAC256 picks a packet from the high-priority linked list unless it is empty, in
which case, a packet from the low-priority linked list is used.
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Figure 15 – TD Linking
TD
TD
P1
Curr. Next Last Host
TDR TDR TDR TDR
V=1
M=1
CE=0
TCDR Table
TD
P4
P3
V=1
M=1
CE=0
TMAC Link
V=0
M=0
CE=1
Data
Data
Host Link
TMAC Link
Host Link
TD
TD
P3
P1
M=1
CE=0
M=0
CE=1
Data
Data
Host Link
TD
P1
M=0
CE=0
Data
Host Link
TD
P2
M=0
CE=1
Data
The host links the TDs vertically while the TMAC256 links TDs horizontally.
Figure 15 shows the TDs for packets P1 and P2 linked by the host before the
TDR is placed on the TDRR queue, as are the TDs for packet P3 and P4.
Packet P3 is linked to packet P1 by the TMAC256, as is packet P4 linked to
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packet P3. The TMAC256 indicates valid horizontal links by setting the V bit to
logic 1.
8.7.2 Task Priorities
The TMAC256 must perform a number of tasks concurrently in order to maintain
a steady flow of data through the system. The main tasks of the TMAC256 are
managing the Ready Queue (i.e. removing chains of data packets from the
queue and attaching them to the appropriate per-channel linked list) and
servicing requests for data from the Transmit Packet Interface. The priority of
service for each of the tasks is fixed by the TMAC256 as follows:
·
Top priority is given to servicing ‘expedited’ read requests from the Transmit
HDLC Processor / Partial Packet Buffer block (THDL256).
·
Second priority is given to removing chains of data packets from the TDRR
queue and attaching them to the appropriate per-channel linked list.
·
Third priority is given to servicing non-expedited read requests from the
THDL256.
8.7.3 DMA Transaction Controller
The DMA Transaction Controller coordinates the processing of requests from the
THDL256 with the reading of data stored in host memory. The reading of a data
packet may require a number of separate host memory transactions, interleaved
with transactions of other DMA channels. As well as reading data from the Host
Master Interface, the DMA Transaction Controller initiates read and write
transactions to the PCI Controller block (GPIC) for the purposes of maintaining
the data structures (queues, descriptors, etc.) in host memory.
8.7.4 Read Data Pipeline
The Read Data Pipeline inserts delay in the data stream between the GPIC
interface and the THDL256 interface to enable the DMA Transaction Controller to
generate appropriate control signals at the Transmit Packet Interface.
8.7.5 Descriptor Information Cache
The Descriptor Information Cache provides the storage for the Transmit Channel
Descriptor Reference (TCDR) Table.
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8.7.6 Free Queue Cache
The Free Queue Cache block implements the 6 element TDR Free Queue
cache. Caching TDRs reduces the number of host bus accesses that the
TMAC256 makes.
TDRs are written to the cache one at a time as they are released by the
TMAC256. The cache is then flushed to host memory when it becomes full,
when a TD with the IOC bit set high is released, when the FQFLUSH register bit
is set high or when a TD is released as the result of unprovisioning a channel.
The cache controller may also flush the cache when it contains fewer than six
elements or if the pointer index is within six elements of the end of the free
queue. When the write pointer is near the end of the free queue, the cache
controller writes only to the end of the queue and does not start writing from the
top of the queue until the next time a flush is required. To do so would require
two host memory transactions and would be of no benefit.
8.8
Transmit HDLC Controller / Partial Packet Buffer
The Transmit HDLC Controller / Partial Packet Buffer block (THDL256) contains
a partial packet buffer for PCI latency control and a transmit HDLC controller.
Packet data retrieved from the PCI host memory by the Transmit DMA Controller
block (TMAC256) is stored in channel specific FIFOs residing in the partial
packet buffer. When the amount of data in a FIFO reaches a programmable
threshold, the HDLC controller is enabled to initiate transmission. The HDLC
controller performs flag generation, bit stuffing and, optionally, frame check
sequence (FCS) insertion. The FCS is software selectable to be CRC-CCITT or
CRC-32. The minimum packet size, excluding FCS, is two bytes. A single byte
payload is illegal. The HDLC controller delivers data to the Transmit Channel
Assigner block (TCAS256) on demand. A packet in progress is aborted if an
under-run occurs. The THDL256 is programmable to operate in transparent
mode where packet data retrieved from the PCI host is transmitted verbatim.
8.8.1 Transmit HDLC Processor
The HDLC processor is a time-slice state machine which can process up to 256
independent channels. The state vector and provisioning information for each
channel is stored in a RAM. Whenever the TCAS256 requests data, the
appropriate state vector is read from the RAM, processed and finally written back
to the RAM. The HDLC state-machine can be configured to perform flag
insertion, bit stuffing and CRC generation. The HDLC processor requests data
from the partial packet processor whenever a request for channel data arrives.
However, the HDLC processor does not start transmitting a packet until the entire
packet is stored in the channel FIFO or until the FIFO free space is less than the
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software programmable limit. If a channel FIFO under-runs, the HDLC processor
aborts the packet.
The configuration of the HDLC processor is accessed using indirect channel
read and write operations. When an indirect operation is performed, the
information is accessed from RAM during a null clock cycle inserted by the
TCAS256 block. Writing new provisioning data to a channel resets the channel’s
entire state vector.
8.8.2 Transmit Partial Packet Buffer Processor
The partial packet buffer processor controls the 32 Kbyte partial packet RAM
which is divided into 16 byte blocks. A block pointer RAM is used to chain the
partial packet blocks into circular channel FIFO buffers. Thus, non-contiguous
sections of RAM can be allocated in the partial packet buffer RAM to create a
channel FIFO. Figure 16 shows an example of three blocks (blocks 1, 3, and
200) linked together to form a 48 byte channel FIFO. The three pointer values
would be written sequentially using indirect block write accesses. When a
channel is provisioned with this FIFO, the state machine can be initialised to
point to any one of the three blocks.
The partial packet buffer processor is divided into three sections: reader, writer
and roamer. The roamer is a time-sliced state machine which tracks each
channel's FIFO buffer free space and signals the writer to service a particular
channel. The writer requests data from the TMAC256 block and transfers packet
data from the TMAC256 to the associated channel FIFO. The reader is a timesliced state machine which transfers the HDLC information from a channel FIFO
to the HDLC processor when the HDLC processor requests it. If a buffer underrun occurs for a channel, the reader informs the HDLC processor and purges the
rest of the packet.
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Figure 16 – Partial Packet Buffer Structure
Partial Packet
Buffer RAM
Block
Pointer RAM
Block 0
16 bytes
Block 0
XX
Block 1
16 bytes
Block 1
0x03
Block 2
16 bytes
Block 2
XX
Block 3
16 bytes
Block 3
0xC8
Block 200
16 bytes
Block 200
0x01
Block 2047
16 bytes
Block 2047
XX
The writer and reader determine empty and full FIFO conditions using flags.
Each block in the partial packet buffer has an associated flag. The writer sets
the flag after the block is written and the reader clears the flag after the block is
read. The flags are initialized (cleared) when the block pointers are written using
indirect block writes. The reader declares a channel FIFO under-run whenever it
tries to read data from a block without a set flag.
The FIFO algorithm of the partial packet buffer processor is based on perchannel software programmable transfer size and free space trigger level.
Instead of tracking the number of full blocks in a channel FIFO, the processor
tracks the number of empty blocks, called free space, as well as the number of
end of packets stored in the FIFO. Recording the number of empty blocks
instead of the number of full blocks reduces the amount of information the
roamer must store in its state RAM.
The partial packet roamer records the FIFO free space and end-of-packet count
for all channel FIFOs. When the reader signals that a block has been read, the
roamer increments the FIFO free space and sets a per-channel request flag if
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the free space is greater than the limit set by XFER[3:0]. The roamer also
decrements the end-of-packet count when the reader signals that it has passed
an end of a packet to the HDLC processor. If the HDLC is transmitting a packet
and the FIFO free space is greater than the starving trigger level and there are
no complete packets within the FIFO (end-of-packet count equal to zero), a perchannel starving flag is set. The roamer searches the starving flags in a roundrobin fashion to decide which channel FIFO should make expedited data
requests to the TMAC256 block. If no starving flags are set, the roamer
searches the request flags in a round-robin fashion to decide which channel
FIFO should make regular data requests to the TMAC256 block. The roamer
informs the partial packet writer of the channel FIFO to process, the FIFO free
space and the type of request it should make. The writer sends a request for
data to the TMAC256 block, writes the response data to the channel FIFO, and
sets the block full flags. The writer reports back to the roamer the number of
blocks and end-of-packets transferred. The maximum amount of data
transferred during one request is limited by a software programmable limit
(XFER[3:0]).
The configuration of the HDLC processor is accessed using indirect channel
read and write operations as well as indirect block read and write operations.
When an indirect operation is performed, the information is accessed from RAM
during a null clock cycle identified by the TCAS256 block. Writing new
provisioning data to a channel resets the entire state vector.
8.9
Transmit Channel Assigner
The Transmit Channel Assigner block (TCAS256) processes up to 256 channels.
Data for all channels is sourced from a single byte-serial stream from the
Transmit HDLC Controller / Partial Packet Buffer block (THDL256). The
TCAS256 demultiplexes the data and assigns each byte to any one of 32 links.
Each link may be configured to support 2.048 or 8.192 H-MVIP traffic, to support
T1/J1/E1 channelised traffic or to support unchannelised traffic. When
configured to support H-MVIP traffic, each group of 8 links share a clock and
frame pulse, otherwise each link is independent and has its own associated
clock. For each high-speed link (TD[2:0]), the TCAS provides a six byte FIFO.
For the remaining links (TD[31:3]), the TCAS provides a single byte holding
register. The TCAS256 also performs parallel to serial conversion to form a bitserial stream. In the event where multiple links are in need of data, TCAS256
requests data from upstream blocks on a fixed priority basis with link TD[0]
having the highest priority and link TD[31] the lowest.
From the point of view of the TCAS256, links configured for H-MVIP traffic
behave identically to links configured for T1/J1/E1 channelised or unchannelised
traffic in the back end, only differing on the link side as described herein. First,
the number of time-slots in each frame is programmable to be 32 or 128 and has
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an associated data clock frequency that is double the data rate. This provides
more bandwidth per link for applications requiring higher data densities on a
single link. Data at each time-slot may be independently assigned to be sourced
from a different channel. Second, H-MVIP links reference the start of each
frame with a frame pulse, thereby avoiding having to gap the link clock during the
framing bits/bytes of each frame. The frame pulse is provided by an H-MVIP bus
master and ensures that all agents sharing the H-MVIP bus remain
synchronized. When configured for operation in 2.048 Mbps H-MVIP mode, the
frame pulse is sampled using the same clock which samples the data. When
configured for operation in 8.192 Mbps H-MVIP mode, the frame pulse is
sampled using a separate frame pulse clock provided by an H-MVIP bus master.
The frame pulse clock has a synchronous timing relationship to the data clock.
Third, not all links are independent. When configured for operation in 2.048
Mbps H-MVIP mode, each group of 8 links share a clock and a frame pulse.
Links 0 through 7, 8 through 15, 16 through 23 and 24 through 31 each share a
clock and a frame pulse. Not all 8 links within each group need to be configured
for operation in 2.048 Mbps H-MVIP mode. However, any link within each logical
group of 8 which is configured for 2.048 Mbps H-MVIP operation will share the
same clock and frame pulse. When configured for operation in 8.192 Mbps HMVIP mode, links 4m (0£m£7) share a frame pulse, a data clock and a frame
pulse clock. Again, not all eight 4m (0£m£7) links need to be configured for
operation in 8.192 Mbps H-MVIP mode, however, any link which is configured for
8.192 Mbps H-MVIP operation will share the same frame pulse, data clock and
frame pulse clock. If link 4m is configured for 8.192 Mbps H-MVIP operation,
then data transferred on that link is “spread” over links 4m, 4m+1 4m+2 and
4m+3 from a channel assigner point of view. Accordingly, when link 4m is
configured for operation in 8.192 Mbps H-MVIP mode, links 4m+1, 4m+2 and
4m+3 must also be configured for operation in 8.192 Mbps H-MVIP mode. In the
back end, the TCAS256 extracts and processes the time-slots identically to
channelised T1/J1/E1 traffic.
Links containing a T1/J1 or an E1 stream may be channelised. Data at each
time-slot may be independently assigned to be sourced from a different channel.
The link clock is only active during time-slots 1 to 24 of a T1/J1 stream and is
inactive during the frame bit. Similarly, the clock is only active during time-slots 1
to 31 of an E1 stream and is inactive during the FAS and NFAS framing bytes.
The most significant bit of time-slot 1 of a channelised link is identified by noting
the absence of the clock and its re-activation. With knowledge of the transmit
link and time-slot identity, the TCAS256 performs a table look-up to identify the
channel from which a data byte is to be sourced.
Links may also be unchannelised. Then, all data bytes on that link belong to one
channel. The TCAS256 performs a table look-up to identify the channel to which
a data byte belongs using only the outgoing link identity, as no time-slots are
associated with unchannelised links. Link clocks are no longer limited to T1/J1
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or E1 rates and may range up to a maximum clock rate of 51.84 MHz for
TCLK[2:0] and 10 MHz for TCLK[31:3]. The link clock is only active during bit
times containing data to be transmitted and inactive during bits that are to be
ignored by the downstream devices, such as framing and overhead bits. For the
case of two unchannelised links, the maximum link rate is 51.84 MHz. For the
case of more numerous unchannelised links or a mixture of channelised,
unchannelised and H-MVIP links, the total instantaneous link rate over all the
links is limited to 64 MHz.
8.9.1 Line Interface Translator (LIT)
The LIT block translates the information between the 32 physical links and the
Line Interface block. The LIT block performs three functions: data translation,
clock translation and frame pulse generation.
When link 4m (0£m£7) is configured for operation in 8.192 Mbps H-MVIP mode,
the LIT block translates the data arriving from the Line Interface block on links
4m, 4m+1, 4m+2 and 4m+3 onto the 128 time-slot link 4m. The LIT block
translates data arriving from the Line Interface block on link 4m, 4m+1, 4m+2
and 4m+3 onto time-slots 0 through 31, 32 through 63, 64 through 95 and 96
through 127 respectively. When link 4m is configured for operation in 8.192
Mbps H-MVIP mode, outputs TD[4m+3:4m+1] are driven with constant ones.
However, links 4m+1, 4m+2 and 4m+3 must be programmed in the TCAS256
Link Configuration register for 8.192 Mbps H-MVIP operation. When links are
configured for operation in 2.048 Mbps H-MVIP mode, channelised T1/J1/E1
mode or unchannelised mode, the LIT block does not perform any translation on
the link data.
When a link is configured for operation in H-MVIP mode, the LIT block divides
the appropriate clock (TMVCK[n] for 2.048 Mbps H-MVIP and TMV8DC for 8.192
Mbps H-MVIP) by two and provides this divided down clock to the Line Interface
block. When a link is configured for operation in channelised T1/J1/E1 or
unchannelised mode, the LIT block does not perform any translation on the link
clock.
When a link is configured for operation in H-MVIP mode, the LIT block samples
the appropriate frame pulse (TFPB[n] for 2.048 Mbps H-MVIP and TFP8B for
8.192 Mbps H-MVIP) and presents the sampled frame pulse to the Line Interface
block. When a link is configured for operation in channelised T1/J1/E1 or
unchannelised mode, the gapped clock is passed to the LIT block unmodified.
8.9.2 Line Interface
There are 32 identical line interface blocks in the TCAS256. Each line interface
block contains 2 sub-blocks; one supporting channelised T1/J1/E1 streams and
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the other H-MVIP streams. Based on configuration, only one of the sub-blocks
are active at one time; the other is held reset. Each sub-block contains a bit
counter, an 8-bit shift register and a holding register. Each sub-block performs
parallel to serial conversion. Whenever the shift register is updated, a request
for service is sent to the priority encoder block. When acknowledged by the
priority encoder, the line interface would respond by writing the data into the
holding register in the active sub-block.
To support H-MVIP links, each line interface block contains a time-slot counter.
The time-slot counter is incremented each time the holding register is updated.
When a frame pulse occurs, the time-slot counter is cleared to indicate that the
next byte belongs to the first time-slot.
To support non H-MVIP channelised links, each line interface block contains a
time-slot counter and a clock activity monitor. The time-slot counter is
incremented each time the shift register is updated. The clock activity monitor is
a counter that increments at the system clock (SYSCLK) rate and is cleared by a
rising edge of the transmit clock (TCLK[n]). A framing bit (T1/J1) or a framing
byte (E1) is detected when the counter reaches a programmable threshold, at
which point, the bit and time-slot counters are initialised to indicate that the next
bit sampled is the most significant bit of the first time-slot. For unchannelised
links, the time-slot counter and the clock activity monitor are held reset.
8.9.3 Priority Encoder
The priority encoder monitors the line interfaces for requests and synchronises
them to the SYSCLK timing domain. Requests are serviced on a fixed priority
scheme where highest to lowest priority is assigned from line interface TD[0] to
line interface TD[31]. Thus, simultaneous requests from line interface TD[m] will
be serviced ahead of line interface TD[n], if m < n. The priority encoder selects
the request from the link with the highest priority for service. When there are no
pending requests, the priority encoder generates an idle cycle. In addition, once
every fourth SYSCLK cycle, the priority encoder inserts a null cycle where no
requests are serviced. This cycle is used by the channel assigner downstream
for CBI accesses to the channel provision RAM.
8.9.4 Channel Assigner
The channel assigner block determines the channel number of the request
currently being processed. The block contains a 1024 word channel provision
RAM. The address of the RAM is constructed from concatenating the link
number and the time-slot number of the highest priority requester. The fields of
each RAM word include the channel number and a time-slot enable flag. The
time-slot enable flag labels the current time-slot as belonging to the channel
indicted by the channel number field. For time-slots that are enabled, the
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channel assigner issues a request to the THDL256 block which responds with
packet data within one byte period of the transmit stream.
8.10 Performance Monitor
The Performance Monitor block (PMON) contains four counters. The first two
accumulate receive partial packet buffer FIFO overrun events and transmit partial
packet buffer FIFO underflow events, respectively. The remaining two counters
are software programmable to accumulate a variety of events, such as receive
packet count, FCS error counts, etc. All counters saturate upon reaching
maximum value. The accumulation logic consists of a counter and holding
register pair. The counter is incremented when the associated event is detected.
Writing to the FREEDM-32P256 Master Clock / BERT Activity Monitor and
Accumulation Trigger register transfer the count to the corresponding holding
register and clear the counter. The contents of the holding register is accessible
via the PCI interface.
8.11 JTAG Test Access Port Interface
The JTAG Test Access Port block provides JTAG support for boundary scan.
The standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST
instructions are supported. The FREEDM-32P256 identification code is
073820CD hexadecimal.
8.12 PCI Host Interface
The FREEDM-32P256 supports two different normal mode register types as
defined below:
1. PCI Host Accessible registers (PA) - these registers can be accessed through
the PCI Host interface.
2. PCI Configuration registers (PC) - these register can only be accessed
through the PCI Host interface during a PCI configuration cycle.
The PCI registers are addressable on dword boundaries only. The PCI offset
shown in the table below must be combined with a base address to form the PCI
Interface address. The base address can be found in the FREEDM-32P256
Memory Base Address register in the PCI Configuration memory space.
Table 12 – Normal Mode PCI Host Accessible Register Memory Map
PCI Offset
Register
0x000
FREEDM-32P256 Master Reset
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PCI Offset
Register
0x004
FREEDM-32P256 Master Interrupt Enable
0x008
FREEDM-32P256 Master Interrupt Status
0x00C
FREEDM-32P256 Master Clock / Frame Pulse / BERT Activity
Monitor and Accumulation Trigger
0x010
FREEDM-32P256 Master Link Activity Monitor
0x014
FREEDM-32P256 Master Line Loopback #1
0x018
FREEDM-32P256 Master Line Loopback #2
0x01C
FREEDM-32P256 Reserved
0x020
FREEDM-32P256 Master BERT Control
0x024
FREEDM-32P256 Master Performance Monitor Control
0x028 - 0x07C
Reserved
0x080
GPIC Control
0x084 - 0x0FC
GPIC Reserved
0x100
RCAS Indirect Channel and Time-slot Select
0x104
RCAS Indirect Channel Data
0x108
RCAS Framing Bit Threshold
0x10C
RCAS Channel Disable
0x110 - 0x17C
RCAS Reserved
0x180 – 0x1FC
RCAS Link #0 through #31 Configuration
0x200
RHDL Indirect Channel Select
0x204
RHDL Indirect Channel Data Register #1
0x208
RHDL Indirect Channel Data Register #2
0x20C
RHDL Reserved
0x210
RHDL Indirect Block Select
0x214
RHDL Indirect Block Data Register
0x218 - 0x21C
RHDL Reserved
0x220
RHDL Configuration
0x224
RHDL Maximum Packet Length
0x228 - 0x23C
RHDL Reserved
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PCI Offset
Register
0x240 - 0x27C
Reserved
0x280
RMAC Control
0x284
RMAC Indirect Channel Provisioning
0x288
RMAC Packet Descriptor Table Base LSW
0x28C
RMAC Packet Descriptor Table Base MSW
0x290
RMAC Queue Base LSW
0x294
RMAC Queue Base MSW
0x298
RMAC Packet Descriptor Reference Large Buffer Free Queue
Start
0x29C
RMAC Packet Descriptor Reference Large Buffer Free Queue
Write
0x2A0
RMAC Packet Descriptor Reference Large Buffer Free Queue
Read
0x2A4
RMAC Packet Descriptor Reference Large Buffer Free Queue
End
0x2A8
RMAC Packet Descriptor Reference Small Buffer Free Queue
Start
0x2AC
RMAC Packet Descriptor Reference Small Buffer Free Queue
Write
0x2B0
RMAC Packet Descriptor Reference Small Buffer Free Queue
Read
0x2B4
RMAC Packet Descriptor Reference Small Buffer Free Queue
End
0x2B8
RMAC Packet Descriptor Reference Ready Queue Start
0x2BC
RMAC Packet Descriptor Reference Ready Queue Write
0x2C0
RMAC Packet Descriptor Reference Ready Queue Read
0x2C4
RMAC Packet Descriptor Reference Ready Queue End
0x2C8 - 0x2FC
RMAC Reserved
0x300
TMAC Control
0x304
TMAC Indirect Channel Provisioning
0x308
TMAC Descriptor Table Base LSW
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PCI Offset
Register
0x30C
TMAC Descriptor Table Base MSW
0x310
TMAC Queue Base LSW
0x314
TMAC Queue Base MSW
0x318
TMAC Descriptor Reference Free Queue Start
0x31C
TMAC Descriptor Reference Free Queue Write
0x320
TMAC Descriptor Reference Free Queue Read
0x324
TMAC Descriptor Reference Free Queue End
0x328
TMAC Descriptor Reference Ready Queue Start
0x32C
TMAC Descriptor Reference Ready Queue Write
0x330
TMAC Descriptor Reference Ready Queue Read
0x334
TMAC Descriptor Reference Ready Queue End
0x338 - 0x37C
TMAC Reserved
0x380
THDL Indirect Channel Select
0x384
THDL Indirect Channel Data #1
0x388
THDL Indirect Channel Data #2
0x38C
THDL Indirect Channel Data #3
0x390 - 0x39C
THDL Reserved
0x3A0
THDL Indirect Block Select
0x3A4
THDL Indirect Block Data
0x3A8 - 0x3AC
THDL Reserved
0x3B0
THDL Configuration
0x3B4 - 0x3BC
THDL Reserved
0x3C0 - 0x3FC
Reserved
0x400
TCAS Indirect Channel and Time-slot Select
0x404
TCAS Indirect Channel Data
0x408
TCAS Framing Bit Threshold
0x40C
TCAS Idle Time-slot Fill Data
0x410
TCAS Channel Disable
0x414 - 0x47C
TCAS Reserved
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PCI Offset
Register
0x480 - 0x4FC
TCAS Link #0 through #31 Configuration
0x500
PMON Status
0x504
PMON Receive FIFO Overflow Count
0x508
PMON Transmit FIFO Underflow Count
0x50C
PMON Configurable Count #1
0x510
PMON Configurable Count #2
0x514 - 0x51C
PMON Reserved
0x520 - 0x7FC
Reserved
The following PCI configuration registers are implemented by the PCI Interface.
These registers can only be accessed when the PCI Interface is a target and a
configuration cycle is in progress as indicated using the IDSEL input.
Table 13 – PCI Configuration Register Memory Map
PCI Offset
Register
0x00
Vendor Identification/Device Identification
0x04
Command/Status
0x08
Revision Identifier/Class Code
0x0C
Cache Line Size/Latency Timer/Header Type/BIST
0x10
CBI Memory Base Address Register
0x14 - 0x24
Unused Base Address Register
0x28 - 0x38
Reserved
0x3C
Interrupt Line/Interrupt Pin/MIN_GNT/MAX_LAT
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NORMAL MODE REGISTER DESCRIPTION
Normal mode registers are used to configure and monitor the operation of the
FREEDM-32P256.
Notes on Normal Mode Register Bits:
1. Writing values into unused register bits has no effect. However, to ensure
software compatibility with future, feature-enhanced versions of the product,
unused register bits must be written with logic zero. Reading back unused
bits can produce either a logic one or a logic zero; hence, unused register bits
should be masked off by software when read.
2. Except where noted, all configuration bits that can be written into can also be
read back. This allows the processor controlling the FREEDM-32P256 to
determine the programming state of the block.
3. Writable normal mode register bits are cleared to logic zero upon reset unless
otherwise noted.
4. Writing into read-only normal mode register bit locations does not affect
FREEDM-32P256 operation unless otherwise noted.
5. Certain register bits are reserved. These bits are associated with megacell
functions that are unused in this application. To ensure that the FREEDM32P256 operates as intended, reserved register bits must only be written with
their default values. Similarly, writing to reserved registers should be
avoided.
9.1
PCI Host Accessible Registers
PCI host accessible registers can be accessed by the PCI host. For each
register description below, the hexadecimal register number indicates the PCI
offset from the base address in the FREEDM-32P256 CBI Register Base
Address Register when accesses are made using the PCI Host Port.
Note
These registers are not byte addressable. Writing to any one of these registers
modifies all the bits in the register. Byte selection using byte enable signals
(CBEB[3:0]) are not implemented. However, when all four byte enables are
negated, no access is made to the register.
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Register 0x000 : FREEDM-32P256 Master Reset
Bit
Type
Bit 31
to
Bit 16
Bit 15
Bit 14
to
Bit 0
R/W
Function
Default
Unused
XXXXH
Reset
0
Unused
XXXXH
This register provides software reset capability.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
RESET:
The RESET bit allows the FREEDM-32P256 to be reset under software
control. If the RESET bit is a logic one, the entire FREEDM-32P256 except
the PCI Interface is held in reset. This bit is not self-clearing. Therefore, a
logic zero must be written to bring the FREEDM-32P256 out of reset. Holding
the FREEDM-32P256 in a reset state places it into a low power, stand-by
mode. A hardware reset clears the RESET bit, thus negating the software
reset.
Note
Unlike the hardware reset input (RSTB), RESET does not force the FREEDM32P256's PCI pins tristate. Transmit link data pins (TD[31:0]) are forced high. In
addition, all registers except the GPIC PCI Configuration registers, are reset to
their default values.
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Register 0x004 : FREEDM-32P256 Master Interrupt Enable
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
TFUDRE
0
Bit 14
R/W
IOCE
0
Bit 13
R/W
TDFQEE
0
Bit 12
R/W
TDQRDYE
0
Bit 11
R/W
TDQFE
0
Bit 10
R/W
RPDRQEE
0
Bit 9
R/W
RPDFQEE
0
Bit 8
R/W
RPQRDYE
0
Bit 7
R/W
RPQLFE
0
Bit 6
R/W
RPQSFE
0
Bit 5
R/W
RFOVRE
0
Bit 4
R/W
RPFEE
0
Bit 3
R/W
RABRTE
0
Bit 2
R/W
RFCSEE
0
Bit 1
R/W
PERRE
0
Bit 0
R/W
SERRE
0
This register provides interrupt enables for various events detected or initiated by
the FREEDM-32P256.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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SERRE:
The system error interrupt enable bit (SERRE) enables PCI system error
interrupts to the PCI host. When SERRE is set high, any address parity error,
data parity error on Special Cycle commands, reception of a master abort or
detection of a target abort will cause an interrupt to be generated on the
PCIINTB output. Interrupts are masked when SERRE is set low. However,
the SERRI bit remains valid when interrupts are disabled and may be polled
to detect PCI system error events.
PERRE:
The parity error interrupt enable bit (PERRE) enables PCI parity error
interrupts to the PCI host. When PERRE is set high, data parity errors
detected by the FREEDM-32P256 or parity errors reported by a target will
cause an interrupt to be generated on the PCIINTB output. Interrupts are
masked when PERRE is set low. However, the PERRI bit remains valid when
interrupts are disabled and may be polled to detect PCI parity error events.
RFCSEE:
The receive frame check sequence error interrupt enable bit (RFCSEE)
enables receive FCS error interrupts to the PCI host. When RFCSEE is set
high, a mismatch between the received FCS code and the computed CRC
residue will cause an interrupt to be generated on the PCIINTB output.
Interrupts are masked when RFCSEE is set low. However, the RFCSEI bit
remains valid when interrupts are disabled and may be polled to detect
receive FCS error events.
RABRTE:
The receive abort interrupt enable bit (RABRTE) enables receive HDLC abort
interrupts to the PCI host. When RABRTE is set high, receipt of an abort
code (at least 7 contiguous 1's) will cause an interrupt to be generated on the
PCIINTB output. Interrupts are masked when RABRTE is set low. However,
the RABRTI bit remains valid when interrupts are disabled and may be polled
to detect receive abort events.
RPFEE:
The receive packet format error interrupt enable bit (RPFEE) enables receive
packet format error interrupts to the PCI host. When RPFEE is set high,
receipt of a packet that is longer than the maximum specified in the RHDL
Maximum Packet Length register, of a packet that is shorter than 32 bits
(CRC-CCITT) or 48 bits (CRC-32), or of a packet that is not octet aligned will
cause an interrupt to be generated on the PCIINTB output. Interrupts are
masked when RPFEE is set low. However, the RPFEI bit remains valid when
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interrupts are disabled and may be polled to detect receive packet format
error events.
RFOVRE:
The receive FIFO overrun error interrupt enable bit (RFOVRE) enables
receive FIFO overrun error interrupts to the PCI host. When RFOVRE is set
high, attempts to write data into the logical FIFO of a channel when it is
already full will cause an interrupt to be generated on the PCIINTB output.
Interrupts are masked when RFOVRE is set low. However, the RFOVRI bit
remains valid when interrupts are disabled and may be polled to detect
receive FIFO overrun events.
RPQSFE:
The receive packet descriptor small buffer free queue cache read interrupt
enable bit (RPQSFE) enables receive packet descriptor small free queue
cache read interrupts to the PCI host. When RPQSFE is set high, reading a
programmable number of RPDR blocks from the RPDR Small Buffer Free
Queue will cause an interrupt to be generated on the PCIINTB output.
Interrupts are masked when RPQSFE is set low. However, the RPQSFI bit
remains valid when interrupts are disabled and may be polled to detect
RPDR small buffer free queue cache read events.
RPQLFE:
The receive packet descriptor large buffer free queue cache read interrupt
enable bit (RPQLFE) enables receive packet descriptor large free queue
cache read interrupts to the PCI host. When RPQLFE is set high, reading a
programmable number of RPDR blocks from the RPDR Large Buffer Free
Queue will cause an interrupt to be generated on the PCIINTB output.
Interrupts are masked when RPQLFE is set low. However, the RPQLFI bit
remains valid when interrupts are disabled and may be polled to detect
RPDR large buffer free queue cache read events.
RPQRDYE:
The receive packet descriptor ready queue write interrupt enable bit
(RPQRDYE) enables receive packet descriptor ready queue write interrupts
to the PCI host. When RPQRDYE is set high, writing a programmable
number of RPDRs to the RPDR Ready Queue will cause an interrupt to be
generated on the PCIINTB output. Interrupts are masked when RPQRDYE is
set low. However, the RPQRDYI bit remains valid when interrupts are
disabled and may be polled to detect RPDR ready queue write events.
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RPDFQEE:
The receive packet descriptor free queue error interrupt enable bit
(RPDFQEE) enables receive packet descriptor free queue error interrupts to
the PCI host. When RPDFQEE is set high, attempts to retrieve an RPDR
when both the large buffer and small buffer free queues are empty will cause
an interrupt to be generated on the PCIINTB output. Interrupts are masked
when RPDFQEE is set low. However, the RPDFQEI bit remains valid when
interrupts are disabled and may be polled to detect RPDR free queue empty
error events.
RPDRQEE:
The receive packet descriptor ready queue error interrupt enable bit
(RPDRQEE) enables receive packet descriptor ready queue error interrupts
to the PCI host. When RPDRQEE is set high, attempts to write an RPDR
when ready queue is ready full will cause an interrupt to be generated on the
PCIINTB output. Interrupts are masked when RPDRQEE is set low.
However, the RPDRQEI bit remains valid when interrupts are disabled and
may be polled to detect RPDR ready queue full error events.
TDQFE:
The transmit packet descriptor free queue write interrupt enable bit (TDQFE)
enables transmit packet descriptor free queue write interrupts to the PCI host.
When TDQFE is set high, writing a programmable number of TDRs to the
TDR Free Queue will cause an interrupt to be generated on the PCIINTB
output. Interrupts are masked when TDQFE is set low. However, the TDQFI
bit remains valid when interrupts are disabled and may be polled to detect
TDR free queue write events.
TDQRDYE:
The transmit descriptor ready queue cache read interrupt enable bit
(TDQRDYE) enables transmit descriptor ready queue cache read interrupts
to the PCI host. When TDQRDYE is set high, reading a programmable
number of TDRs from the TDR Ready Queue will cause an interrupt to be
generated on the PCIINTB output. Interrupts are masked when TDQRDYE is
set low. However, the TDQRDYI bit remains valid when interrupts are
disabled and may be polled to detect TDR ready queue cache read events.
TDFQEE:
The transmit descriptor free queue error interrupt enable bit (TDFQEE)
enables transmit descriptor free queue error interrupts to the PCI host. When
TDFQEE is set high, attempting to write to the transmit free queue while the
queue is full will cause an interrupt to be generated on the PCIINTB output.
Interrupts are masked when TDFQEE is set low. However, the TDFQEI bit
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remains valid when interrupts are disabled and may be polled to detect TD
free queue error events.
IOCE:
The transmit interrupt on complete enable bit (IOCE) enables transmission
complete interrupts to the PCI host. When IOCE is set high, complete
transmission of a packet with the IOC bit in the TD set high will cause an
interrupt to be generated on the PCIINTB output. Interrupts are masked
when IOCE is set low. However, the IOCI bit remains valid when interrupts
are disabled and may be polled to detect transmission of IOC tagged
packets.
TFUDRE:
The transmit FIFO underflow error interrupt enable bit (TFUDRE) enables
transmit FIFO underflow error interrupts to the PCI host. When TFUDRE is
set high, attempts to read data from the logical FIFO when it is already empty
will cause an interrupt to be generated on the PCIINTB output. Interrupts are
masked when TFUDRE is set low. However, the TFUDRI bit remains valid
when interrupts are disabled and may be polled to detect transmit FIFO
underflow events.
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Register 0x008 : FREEDM-32P256 Master Interrupt Status
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R
TFUDRI
X
Bit 14
R
IOCI
X
Bit 13
R
TDFQEI
X
Bit 12
R
TDQRDYI
X
Bit 11
R
TDQFI
X
Bit 10
R
RPDRQEI
X
Bit 9
R
RPDFQEI
X
Bit 8
R
RPQRDYI
X
Bit 7
R
RPQLFI
X
Bit 6
R
RPQSFI
X
Bit 5
R
RFOVRI
X
Bit 4
R
RPFEI
X
Bit 3
R
RABRTI
X
Bit 2
R
RFCSEI
X
Bit 1
R
PERRI
X
Bit 0
R
SERRI
X
This register reports the interrupt status for various events detected or initiated
by the FREEDM-32P256. Reading this registers acknowledges and clears the
interrupts.
Note
This register is not byte addressable. Reading this register clears all the interrupt
bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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SERRI:
The system error interrupt status bit (SERRI) reports PCI system error
interrupts to the PCI host. SERRI is set high upon detection of any address
parity error, data parity error on Special Cycle commands, reception of a
master abort or detection of a target abort event. The SERRI bit remains
valid when interrupts are disabled and may be polled to detect PCI system
error events.
PERRI:
The parity error interrupt status bit (PERRI) reports PCI parity error interrupts
to the PCI host. PERRI is set high when data parity errors are detected by
the FREEDM-32P256 while acting as a master, and when parity errors are
reported to the FREEDM-32P256 by a target via the PERRB input. The
PERRI bit remains valid when interrupts are disabled and may be polled to
detect PCI parity error events.
RFCSEI:
The receive frame check sequence error interrupt status bit (RFCSEI) reports
receive FCS error interrupts to the PCI host. RFCSEI is set high, when a
mismatch between the received FCS code and the computed CRC residue is
detected. RFCSEI remains valid when interrupts are disabled and may be
polled to detect receive FCS error events.
RABRTI:
The receive abort interrupt status bit (RABRTI) reports receive HDLC abort
interrupts to the PCI host. RABRTI is set high upon receipt of an abort code
(at least 7 contiguous 1's). RABRTI remains valid when interrupts are
disabled and may be polled to detect receive abort events.
RPFEI:
The receive packet format error interrupt status bit (RPFEI) reports receive
packet format error interrupts to the PCI host. RPFEI is set high upon receipt
of a packet that is longer than the maximum programmed length, of a packet
that is shorter than 32 bits (CRC-CCITT) or 48 bits (CRC-32), or of a packet
that is not octet aligned. RPFEI remains valid when interrupts are disabled
and may be polled to detect receive packet format error events.
RFOVRI:
The receive FIFO overrun error interrupt status bit (RFOVRI) reports receive
FIFO overrun error interrupts to the PCI host. RFOVRI is set high on
attempts to write data into the logical FIFO of a channel when it is already full.
RFOVRI remains valid when interrupts are disabled and may be polled to
detect receive FIFO overrun events.
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RPQSFI:
The receive packet descriptor small buffer free queue cache read interrupt
status bit (RPQSFI) reports receive packet descriptor small free queue cache
read interrupts to the PCI host. RPQSFI is set high when the programmable
number of RPDR blocks is read from the RPDR Small Buffer Free Queue.
RPQSFI remains valid when interrupts are disabled and may be polled to
detect RPDR small buffer free queue cache read events.
RPQLFI:
The receive packet descriptor large buffer free queue cache read interrupt
status bit (RPQLFI) reports receive packet descriptor large free queue cache
read interrupts to the PCI host. RPQLFI is set high when the programmable
number of RPDR blocks is read from the RPDR Large Buffer Free Queue.
RPQLFI remains valid when interrupts are disabled and may be polled to
detect RPDR large buffer free queue cache read events.
RPQRDYI:
The receive packet descriptor ready queue write interrupt status bit
(RPQRDYI) reports receive packet descriptor ready queue write interrupts to
the PCI host. RPQRDYI is set high when the programmable number of
RPDRs is written to the RPDR Ready Queue. RPQRDYI remains valid when
interrupts are disabled and may be polled to detect RPDR ready queue write
events.
RPDFQEI:
The receive packet descriptor free queue error interrupt status bit (RPDFQEI)
reports receive packet descriptor free queue error interrupts to the PCI host.
RPDFQEI is set high upon attempts to retrieve an RPDR when both the large
buffer and small buffer free queues are empty. RPDFQEI remains valid when
interrupts are disabled and may be polled to detect RPDR free queue empty
error events.
RPDRQEI:
The receive packet descriptor ready queue error interrupt status bit
(RPDRQEI) reports receive packet descriptor ready queue error interrupts to
the PCI host. RPDRQEI is set high upon attempts to write an RPDR when
ready queue is ready full. RPDRQEI remains valid when interrupts are
disabled and may be polled to detect RPDR ready queue full error events.
TDQFI:
The transmit packet descriptor free queue write interrupt status bit (TDQFI)
reports transmit packet descriptor free queue write interrupts to the PCI host.
TDQFI is set high when the programmable number of TDRs is written to the
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TDR Free Queue. TDQFI remains valid when interrupts are disabled and
may be polled to detect TDR free queue write events.
TDQRDYI:
The transmit descriptor ready queue cache read interrupt status bit
(TDQRDYI) reports transmit descriptor ready queue cache read interrupts to
the PCI host. TDQRDYI is set high when the programmable number of TDRs
is read from the TDR Ready Queue. TDQRDYI remains valid when interrupts
are disabled and may be polled to detect TDR ready queue cache read
events.
TDFQEI:
The transmit descriptor free queue error interrupt status bit (TDFQEI) reports
transmit descriptor free queue error interrupts to the PCI host. TDFQEI is set
high when an attempt to write to the transmit free queue fail due to the queue
being already full. TDFQEI bit remains valid when interrupts are disabled and
may be polled to detect TD free queue error events.
IOCI:
The transmit interrupt on complete status bit (IOCI) reports transmission
complete interrupts to the PCI host. IOCI is set high, when a packet with the
IOC bit in the TD set high is completely transmitted. IOCI remains valid when
interrupts are disabled and may be polled to detect transmission of IOC
tagged packets.
TFUDRI:
The transmit FIFO underflow error interrupt status bit (TFUDRI) reports
transmit FIFO underflow error interrupts to the PCI host. TFUDRI is set high
upon attempts to read data from the logical FIFO when it is already empty.
TFUDRI remains valid when interrupts are disabled and may be polled to
detect transmit FIFO underflow events.
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Register 0x00C : FREEDM-32P256 Master Clock / Frame Pulse / BERT
Activity Monitor and Accumulation Trigger
Bit
Type
Bit 31
to
Bit 12
Function
Default
Unused
XXXXXH
Bit 11
R
TFPA[3]
X
Bit 10
R
TFPA[2]
X
Bit 9
R
TFPA[1]
X
Bit 8
R
TFPA[0]
X
Bit 7
R
RFPA[3]
X
Bit 6
R
RFPA[2]
X
Bit 5
R
RFPA[1]
X
Bit 4
R
RFPA[0]
X
Bit 3
R
TFP8A
X
Bit 2
R
RFP8A
X
Bit 1
R
TBDA
X
Bit 0
R
SYSCLKA
X
This register provides activity monitoring on FREEDM-32P256 system clock,
H-MVIP frame pulse and BERT port inputs. When a monitored input makes a
transition, the corresponding register bit is set high. The bit will remain high until
this register is read, at which point, all the bits in this register are cleared. A lack
of transitions is indicated by the corresponding register bit reading low. This
register should be read periodically to detect for stuck at conditions.
Writing to this register delimits the accumulation intervals in the PMON
accumulation registers. Counts accumulated in those registers are transferred to
holding registers where they can be read. The counters themselves are then
cleared to begin accumulating events for a new accumulation interval. The bits
in this register are not affected by write accesses.
Note
This register is not byte addressable. Reading this register clears all the activity
bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
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implemented. However, when all four byte enables are negated, no access is
made to this register.
SYSCLKA:
The system clock active bit (SYSCLKA) monitors for low to high transitions on
the SYSCLK input. SYSCLKA is set high on a rising edge of SYSCLK, and is
set low when this register is read.
TBDA:
The transmit BERT data active bit (TBDA) monitors for low to high transitions
on the TBD input. TBDA is set high on a rising edge of TDB, and is set low
when this register is read.
RFP8A:
The receive 8.192 Mbps H-MVIP frame pulse activity bit (RFP8A) monitors for
low to high transitions on the RFP8B input. RFP8A is set high when RFP8B
has been sampled low and sampled high by falling edges of the RMV8FPC,
and is set low when this register is read.
TFP8A:
The transmit 8.192 Mbps H-MVIP frame pulse activity bit (TFP8A) monitors
for low to high transitions on the TFP8B input. TFP8A is set high when
TFP8B has been sampled low and sampled high by falling edges of the
TMV8FPC, and is set low when this register is read.
RFPA[3:0]:
The receive frame pulse activity bits (RFPA[3:0]) monitor for low to high
transitions on the RFPB[3:0] inputs. RFPA[n] is set high when RFPB[n] has
been sampled low and sampled high by falling edges of the corresponding
RMVCK[n], and is set low when this register is read.
TFPA[3:0]:
The transmit frame pulse activity bits (TFPA[3:0]) monitor for low to high
transitions on the TFPB[3:0] inputs. TFPA[n] is set high when TFPB[n] has
been sampled low and sampled high by falling edges of the corresponding
TMVCK[n], and is set low when this register is read.
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Register 0x010 : FREEDM-32P256 Master Link Activity Monitor
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R
TLGA[7]
X
Bit 14
R
TLGA[6]
X
Bit 13
R
TLGA[5]
X
Bit 12
R
TLGA[4]
X
Bit 11
R
TLGA[3]
X
Bit 10
R
TLGA[2]
X
Bit 9
R
TLGA[1]
X
Bit 8
R
TLGA[0]
X
Bit 7
R
RLGA[7]
X
Bit 6
R
RLGA[6]
X
Bit 5
R
RLGA[5]
X
Bit 4
R
RLGA[4]
X
Bit 3
R
RLGA[3]
X
Bit 2
R
RLGA[2]
X
Bit 1
R
RLGA[1]
X
Bit 0
R
RLGA[0]
X
This register provides activity monitoring on FREEDM-32P256 receive and
transmit link inputs. When a monitored input makes a low to high transition, the
corresponding register bit is set high. The bit will remain high until this register is
read, at which point, all the bits in this register are cleared. A lack of transitions
is indicated by the corresponding register bit reading low. This register should be
read periodically to detect for stuck at conditions.
Note
This register is not byte addressable. Reading this register clears all the activity
bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
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implemented. However, when all four byte enables are negated, no access is
made to this register.
RLGA[0]:
The receive link group #0 active bit (RLGA[0]) monitors for transitions on the
RD[3:0] and RCLK[3:0]/RMVCK[0]/RMV8DC inputs. RLGA[0] is set high
when either:
1. Each of RD[3:0] has been sampled low and sampled high by rising
edges of the corresponding RCLK[3:0] inputs, or
2. Each of RD[3:0] has been sampled low and sampled high by rising
edges of the RMVCK[0] input, or
3. RD[0] has been sampled low and sampled high by rising edges of the
RMV8DC input.
RLGA[0] is set low when this register is read.
RLGA[1]:
The receive link group #1 active bit (RLGA[1]) monitors for transitions on the
RD[7:4] and RCLK[7:4]/RMVCK[0]/RMV8DC inputs. RLGA[1] is set high
when either:
1. Each of RD[7:4] has been sampled low and sampled high by rising
edges of the corresponding RCLK[7:4] inputs, or
2. Each of RD[7:4] has been sampled low and sampled high by rising
edges of the RMVCK[0] input, or
3. RD[4] has been sampled low and sampled high by rising edges of the
RMV8DC input.
RLGA[1] is set low when this register is read.
RLGA[2]:
The receive link group #2 active bit (RLGA[2]) monitors for transitions on the
RD[11:8] and RCLK[11:8]/RMVCK[1]/RMV8DC inputs. RLGA[2] is set high
when either:
1. Each of RD[11:8] has been sampled low and sampled high by rising
edges of the corresponding RCLK[11:8] inputs, or
2. Each of RD[11:8] has been sampled low and sampled high by rising
edges of the RMVCK[1] input, or
3. RD[8] has been sampled low and sampled high by rising edges of the
RMV8DC input.
RLGA[2] is set low when this register is read.
RLGA[3]:
The receive link group #3 active bit (RLGA[3]) monitors for transitions on the
RD[15:12] and RCLK[15:12]/RMVCK[1]/RMV8DC inputs. RLGA[3] is set high
when either:
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1. Each of RD[15:12] has been sampled low and sampled high by rising
edges of the corresponding RCLK[15:12] inputs, or
2. Each of RD[15:12] has been sampled low and sampled high by rising
edges of the RMVCK[1] input, or
3. RD[12] has been sampled low and sampled high by rising edges of the
RMV8DC input.
RLGA[3] is set low when this register is read.
RLGA[4]:
The receive link group #4 active bit (RLGA[4]) monitors for transitions on the
RD[19:16] and RCLK[19:16]/RMVCK[2]/RMV8DC inputs. RLGA[4] is set high
when either:
1. Each of RD[19:16] has been sampled low and sampled high by rising
edges of the corresponding RCLK[19:16] inputs, or
2. Each of RD[19:16] has been sampled low and sampled high by rising
edges of the RMVCK[2] input, or
3. RD[16] has been sampled low and sampled high by rising edges of the
RMV8DC input.
RLGA[4] is set low when this register is read.
RLGA[5]:
The receive link group #5 active bit (RLGA[5]) monitors for transitions on the
RD[23:20] and RCLK[23:20]/RMVCK[2]/RMV8DC inputs. RLGA[5] is set high
when either:
1. Each of RD[23:20] has been sampled low and sampled high by rising
edges of the corresponding RCLK[23:20] inputs, or
2. Each of RD[23:20] has been sampled low and sampled high by rising
edges of the RMVCK[2] input, or
3. RD[20] has been sampled low and sampled high by rising edges of the
RMV8DC input.
RLGA[5] is set low when this register is read.
RLGA[6]:
The receive link group #6 active bit (RLGA[6]) monitors for transitions on the
RD[27:24] and RCLK[27:24]/RMVCK[3]/RMV8DC inputs. RLGA[6] is set high
when either:
1. Each of RD[27:24] has been sampled low and sampled high by rising
edges of the corresponding RCLK[27:24] inputs, or
2. Each of RD[27:24] has been sampled low and sampled high by rising
edges of the RMVCK[3] input, or
3. RD[24] has been sampled low and sampled high by rising edges of the
RMV8DC input.
RLGA[6] is set low when this register is read.
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RLGA[7]:
The receive link group #7 active bit (RLGA[7]) monitors for transitions on the
RD[31:28] and RCLK[31:28]/RMVCK[3]/RMV8DC inputs. RLGA[7] is set high
when either:
1. Each of RD[31:28] has been sampled low and sampled high by rising
edges of the corresponding RCLK[31:28] inputs, or
2. Each of RD[31:28] has been sampled low and sampled high by rising
edges of the RMVCK[3] input, or
3. RD[28] has been sampled low and sampled high by rising edges of the
RMV8DC input.
RLGA[7] is set low when this register is read.
TLGA[0]:
The transmit link group #0 active bit (TLGA[0]) monitors for low to high
transitions on the TCLK[3:0] & TMVCK[0] inputs. TLGA[0] is set high when
either:
1. Rising edges have been observed on all four TCLK[3:0] inputs, or
2. A rising edge has been observed on the TMVCK[0] input.
TLGA[0] is set low when this register is read.
TLGA[1]:
The transmit link group #1 active bit (TLGA[1]) monitors for low to high
transitions on the TCLK[7:4] & TMVCK[1] inputs. TLGA[1] is set high when
either:
1. Rising edges have been observed on all four TCLK[7:4] inputs, or
2. A rising edge has been observed on the TMVCK[1] input.
TLGA[1] is set low when this register is read.
TLGA[2]:
The transmit link group #2 active bit (TLGA[2]) monitors for low to high
transitions on the TCLK[11:8] & TMVCK[2] inputs. TLGA[2] is set high when
either:
1. Rising edges have been observed on all four TCLK[11:8] inputs, or
2. A rising edge has been observed on the TMVCK[2] input.
TLGA[2] is set low when this register is read.
TLGA[3]:
The transmit link group #3 active bit (TLGA[3]) monitors for low to high
transitions on the TCLK[15:12] & TMVCK[3] inputs. TLGA[3] is set high when
either:
1. Rising edges have been observed on all four TCLK[15:12] inputs, or
2. A rising edge has been observed on the TMVCK[3] input.
TLGA[3] is set low when this register is read.
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TLGA[4]:
The transmit link group #4 active bit (TLGA[4]) monitors for low to high
transitions on the TCLK[19:16] inputs. TLGA[4] is set high when rising edges
have been observed on all four TCLK[19:16] inputs, and is set low when this
register is read.
TLGA[5]:
The transmit link group #5 active bit (TLGA[5]) monitors for low to high
transitions on the TCLK[23:20] inputs. TLGA[5] is set high when rising edges
have been observed on all four TCLK[23:20] inputs, and is set low when this
register is read.
TLGA[6]:
The transmit link group #6 active bit (TLGA[6]) monitors for low to high
transitions on the TCLK[27:24] inputs. TLGA[6] is set high when rising edges
have been observed on all four TCLK[27:24] inputs, and is set low when this
register is read.
TLGA[7]:
The transmit link group #7 active bit (TLGA[7]) monitors for low to high
transitions on the TCLK[31:28] & TMV8DC inputs. TLGA[7] is set high when
either:
1. Rising edges have been observed on all four TCLK[31:28] inputs, or
2. A rising edge has been observed on the TMV8DC input.
TLGA[7] is set low when this register is read.
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Register 0x014 : FREEDM-32P256 Master Line Loopback #1
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
LLBEN[15]
0
Bit 14
R/W
LLBEN[14]
0
Bit 13
R/W
LLBEN[13]
0
Bit 12
R/W
LLBEN[12]
0
Bit 11
R/W
LLBEN[11]
0
Bit 10
R/W
LLBEN[10]
0
Bit 9
R/W
LLBEN[9]
0
Bit 8
R/W
LLBEN[8]
0
Bit 7
R/W
LLBEN[7]
0
Bit 6
R/W
LLBEN[6]
0
Bit 5
R/W
LLBEN[5]
0
Bit 4
R/W
LLBEN[4]
0
Bit 3
R/W
LLBEN[3]
0
Bit 2
R/W
LLBEN[2]
0
Bit 1
R/W
LLBEN[1]
0
Bit 0
R/W
LLBEN[0]
0
This register controls line loopback for links #0 to #15.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
LLBEN[15:0]:
The line loopback enable bits (LLBEN[15:0]) controls line loopback for
links #15 to #0. When links #0 through #15 are configured for channelised
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T1/J1/E1 or unchannelised traffic and LLBEN[n] is set high, the data on RD[n]
is passed verbatim to TD[n] which is then updated on the falling edge of
RCLK[n]. TCLK[n] is ignored. When LLBEN[n] is set low, TD[n] is processed
normally. Line loopback is not supported for H-MVIP traffic.
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Register 0x018 : FREEDM-32P256 Master Line Loopback #2
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
LLBEN[31]
0
Bit 14
R/W
LLBEN[30]
0
Bit 13
R/W
LLBEN[29]
0
Bit 12
R/W
LLBEN[28]
0
Bit 11
R/W
LLBEN[27]
0
Bit 10
R/W
LLBEN[26]
0
Bit 9
R/W
LLBEN[25]
0
Bit 8
R/W
LLBEN[24]
0
Bit 7
R/W
LLBEN[23]
0
Bit 6
R/W
LLBEN[22]
0
Bit 5
R/W
LLBEN[21]
0
Bit 4
R/W
LLBEN[20]
0
Bit 3
R/W
LLBEN[19]
0
Bit 2
R/W
LLBEN[18]
0
Bit 1
R/W
LLBEN[17]
0
Bit 0
R/W
LLBEN[16]
0
This register controls line loopback for links #16 to #31.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
LLBEN[31:16]:
The line loopback enable bits (LLBEN[31:16]) controls line loopback for
links #31 to #16. When links #16 through #31 are configured for channelised
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T1/J1/E1 or unchannelised traffic and LLBEN[n] is set high, the data on RD[n]
is passed verbatim to TD[n] which is then updated on the falling edge of
RCLK[n]. TCLK[n] is ignored. When LLBEN[n] is set low, TD[n] is processed
normally. Line loopback is not supported for H-MVIP traffic.
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Register 0x01C : FREEDM-32P256 Reserved
Bit
Type
Bit 15
to
Bit 1
Bit 0
R/W
Function
Default
Unused
XXXXH
Reserved
0
Note
This register is not byte addressable. Reading this register clears all the activity
bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
Reserved:
The reserved bit must be set low for correct operation of the FREEDM32P256 device.
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Register 0x020 : FREEDM-32P256 Master BERT Control
Bit
Type
Function
Default
Unused
XXXXH
TBEN
0
Bit 14
Unused
X
Bit 13
Unused
X
Bit 31
to
Bit 16
Bit 15
R/W
Bit 12
R/W
TBSEL[4]
0
Bit 11
R/W
TBSEL[3]
0
Bit 10
R/W
TBSEL[2]
0
Bit 9
R/W
TBSEL[1]
0
Bit 8
R/W
TBSEL[0]
0
Bit 7
R/W
RBEN
0
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
R/W
RBSEL[4]
0
Bit 3
R/W
RBSEL[3]
0
Bit 2
R/W
RBSEL[2]
0
Bit 1
R/W
RBSEL[1]
0
Bit 0
R/W
RBSEL[0]
0
This register controls the bit error rate testing of the receive and transmit links.
Bit error rate testing is not supported for links configured for H-MVIP traffic.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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RBSEL[4:0]:
The receive bit error rates testing link select bits (RBSEL[4:0]) controls the
source of data on the RBD and RBCLK outputs when receive bit error rate
testing is enabled (RBEN set high). RBSEL[4:0] is a binary number that
selects a receive link configured for non H-MVIP traffic (RD[31:0]/RCLK[31:0])
to be the source of data for RBD and RBCLK outputs. RBSEL[4:0] is ignored
when RBEN is set low. RBSEL[4:0] cannot select a link configured for HMVIP traffic.
RBEN:
The receive bit error rates testing link enable bit (RBEN) controls the receive
bit error rate testing port. When RBEN is set high, RBSEL[4:0] is a binary
number that selects a receive link configured for non H-MVIP traffic
(RD[31:0]/RCLK[31:0]) to be the source of data for RBD and RBCLK outputs.
When RBEN is set low, RBD and RBCLK are held tristated.
TBSEL[4:0]:
The transmit bit error rates testing link select bits (TBSEL[4:0]) controls the
over-writing of transmit data on TD[31:0] by data on TBD when transmit bit
error rate testing is enabled (TBEN set high) and the selected link is not in
line loopback (LLBEN[n] set low). TBSEL[4:0] is a binary number that selects
a transmit link configured for non H-MVIP traffic (TD[31:0]/TCLK[31:0]) to
carry the data on TBD. The TBCLK output is a buffered version of the
selected one of TCLK[31:0]. TBSEL[4:0] is ignored when TBEN is set low.
TBSEL[4:0] cannot select a link configured for H-MVIP traffic.
TBEN:
The transmit bit error rates testing link enable bit (TBEN) controls the transmit
bit error rate testing port. When TBEN is set high and the associated link in
not in line loopback (LLBEN set low), TBSEL[4:0] is a binary number that
selects a transmit link data configured for non H-MVIP traffic (TD[31:0]) to
carry the data on TBD and selects a transmit link clock (TCLK[31:0]) as the
source of TBCLK. When TBEN is set low, all transmit links are processed
normally and TBCLK is held tristated.
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Register 0x024 : FREEDM-32P256 Master Performance Monitor Control
Bit
Type
Bit 31
to
Bit 15
Function
Default
Unused
XXXXXH
Bit 14
R/W
TP2EN
0
Bit 13
R/W
TABRT2EN
0
Bit 12
R/W
RP2EN
0
Bit 11
R/W
RLENE2EN
0
Bit 10
R/W
RABRT2EN
0
Bit 9
R/W
RFCSE2EN
0
Bit 8
R/W
RSPE2EN
0
Unused
X
Bit 7
Bit 6
R/W
TP1EN
0
Bit 5
R/W
TABRT1EN
0
Bit 4
R/W
RP1EN
0
Bit 3
R/W
RLENE1EN
0
Bit 2
R/W
RABRT1EN
0
Bit 1
R/W
RFCSE1EN
0
Bit 0
R/W
RSPE1EN
0
This register configures the events that are accumulated in the two configurable
performance monitor counters in the PMON block.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
RSPE1EN:
The receive small packet error accumulate enable bit (RSPE1EN) enables
counting of minimum packet size violation events. When RSPE1EN is set
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high, receipt of a packet that is shorter than 32 bits (CRC-CCITT, Unspecified
CRC or no CRC) or 48 bits (CRC-32) will cause the PMON Configurable
Accumulator #1 register to increment. Small packet errors are ignored when
RSPE1EN is set low.
RFCSE1EN:
The receive frame check sequence error accumulate enable bit (RFCSE1EN)
enables counting of receive FCS error events. When RFCSE1EN is set high,
a mismatch between the received FCS code and the computed CRC residue
will cause the PMON Configurable Accumulator #1 register to increment.
Receive frame check sequence errors are ignored when RFCSE1EN is set
low.
RABRT1EN:
The receive abort accumulate enable bit (RABRT1EN) enables counting of
receive HDLC abort events. When RABRT1EN is set high, receipt of an
abort code (at least 7 contiguous 1's) will cause the PMON Configurable
Accumulator #1 register to increment. Receive aborts are ignored when
RABRT1EN is set low.
RLENE1EN:
The receive packet length error accumulate enable bit (RLENE1EN) enables
counting of receive packet length error events. When RLENE1EN is set high,
receipt of a packet that is longer than the programmable maximum or of a
packet that in not octet aligned will cause the PMON Configurable
Accumulator #1 register to increment. (Receipt of a packet that is both too
long and not octet aligned results in only one increment.) Receive packet
length errors are ignored when RLENE1EN is set low.
RP1EN:
The receive packet enable bit (RP1EN) enables counting of receive error-free
packets. When RP1EN is set high, receipt of an error-free packet will cause
the PMON Configurable Accumulator #1 register to increment. Receive errorfree packets are ignored when RP1EN is set low.
TABRT1EN:
The transmit abort accumulate enable bit (TABRT1EN) enables counting of
transmit HDLC abort events. When TABRT1EN is set high, insertion of an
abort in the outgoing stream will cause the PMON Configurable Accumulator
#1 register to increment. Transmit aborts are ignored when TABRT1EN is set
low.
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TP1EN:
The transmit packet enable bit (TP1EN) enables counting of transmit
error-free packets. When TP1EN is set high, transmission of an error-free
packet will cause the PMON Configurable Accumulator #1 register to
increment. Transmit error-free packets are ignored when TP1EN is set low.
RSPE2EN:
The receive small packet error accumulate enable bit (RSPE2EN) enables
counting of minimum packet size violation events. When RSPE2EN is set
high, receipt of a packet that is shorter than 32 bits (CRC-CCITT, Unspecified
CRC or no CRC) or 48 bits (CRC-32) will cause the PMON Configurable
Accumulator #2 register to increment. Small packet errors are ignored when
RSPE2EN is set low.
RFCSE2EN:
The receive frame check sequence error accumulate enable bit (RFCSE2EN)
enables counting of receive FCS error events. When RFCSE2EN is set high,
a mismatch between the received FCS code and the computed CRC residue
will cause the PMON Configurable Accumulator #2 register to increment.
Receive frame check sequence errors are ignored when RFCSE2EN is set
low.
RABRT2EN:
The receive abort accumulate enable bit (RABRT2EN) enables counting of
receive HDLC abort events. When RABRT2EN is set high, receipt of an
abort code (at least 7 contiguous 2's) will cause the PMON Configurable
Accumulator #2 register to increment. Receive aborts are ignored when
RABRT2EN is set low.
RLENE2EN:
The receive packet length error accumulate enable bit (RLENE2EN) enables
counting of receive packet length error events. When RLENE2EN is set high,
receipt of a packet that is longer than the programmable maximum or of a
packet that in not octet aligned will cause the PMON Configurable
Accumulator #2 register to increment. (Receipt of a packet that is both too
long and not octet aligned results in only one increment.) Receive packet
length errors are ignored when RLENE2EN is set low.
RP2EN:
The receive packet enable bit (RP2EN) enables counting of receive error-free
packets. When RP2EN is set high, receipt of an error-free packet will cause
the PMON Configurable Accumulator #2 register to increment. Receive errorfree packets are ignored when RP2EN is set low.
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TABRT2EN:
The transmit abort accumulate enable bit (TABRT2EN) enables counting of
transmit HDLC abort events. When TABRT2EN is set high, insertion of an
abort in the outgoing stream will cause the PMON Configurable Accumulator
#2 register to increment. Transmit aborts are ignored when TABRT2EN is set
low.
TP2EN:
The transmit packet enable bit (TP2EN) enables counting of transmit
error-free packets. When TP2EN is set high, transmission of an error-free
packet will cause the PMON Configurable Accumulator #2 register to
increment. Transmit error-free packets are ignored when TP2EN is set low.
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Register 0x080 : GPIC Control
Bit
Type
Bit 31
to
Bit 14
Function
Default
Unused
XXXXXH
Bit 13
R/W
RPWTH[5]
0
Bit 12
R/W
RPWTH[4]
0
Bit 11
R/W
RPWTH[3]
0
Bit 10
R/W
RPWTH[2]
0
Bit 9
R/W
RPWTH[1]
0
Bit 8
R/W
RPWTH[0]
0
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
R/W
PONS_E
0
Bit 2
R/W
SOE_E
0
Bit 1
R/W
LENDIAN
1
Bit 0
R/W
Reserved
0
This register configures the operation of the GPIC.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
Reserved:
The Reserved bit must be set low for correct operation of the FREEDM32P256.
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LENDIAN:
The Little Endian mode bit (LENDIAN) selects between Big Endian or Little
Endian format when reading packet data from and writing packet data to PCI
host memory. When LENDIAN is set low, Big Endian format is selected.
When LENDIAN is set high, Little Endian format is selected. Descriptor
references and the contents of descriptors are always transferred in Little
Endian Format. Please refer below for each format's byte ordering.
Table 14 – Big Endian Format
00
DWORD Address
04
n-4
Bit 31
24
23
16
15
8
7
Bit 0
BYTE 0
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
BYTE 7
•
•
•
•
•
•
•
•
•
•
•
•
BYTE n-4
BYTE n-3
BYTE n-2
BYTE n-1
Table 15 – Little Endian Format
00
DWORD Address
04
n-4
Bit 31
24
23
16
15
8
7
Bit 0
BYTE 3
BYTE 2
BYTE 1
BYTE 0
BYTE 7
BYTE 6
BYTE 5
BYTE 4
•
•
•
•
•
•
•
•
•
•
•
•
BYTE n-1
BYTE n-2
BYTE n-3
BYTE n-4
SOE_E:
The stop on error enable (SOE_E) bit determines the action the PCI
controller will take when a system or parity error occurs. When set high the
PCI controller will disconnect the PCI REQB signal from the PCI bus. This
prevents the GPIC from the becoming a master device on the PCI bus in
event of one of the following bits in the PCI Configuration Command/Status
register being set: DPR, RTABT, MABT and SERR. When the SOE_E bit is
set low the PCI controller will continue to allow master transactions on the
PCI bus. Setting this bit low after an error has occurred or clearing the
appropriate bit the PCI Configuration Command/Status register will reactivate
the PCI REQB signal and allow the GPIC to resume servicing the local
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masters. In the event of a system or parity error it is recommended that the
core device be reset unless the cause of the fault can be determined.
PONS_E:
The Report PERR on SERR enable (PONS_E) bit controls the source of
system errors. When set high all parity errors will be signaled to the host via
the SERRB output signal.
RPWTH[5:0]:
The Receive Packet Write Threshold bits (RPWTH[5:0]) controls the amount
of data in the write FIFO before the GPIC begins arbitrating for the bus. The
GPIC will begin requesting access to the PCI bus when the number of dwords
of packet data loaded by the RMAC256 reaches the threshold specified by
RPWTH[5:0].
If the FREEDM-32P256 is being operated with PCICLK at a higher frequency
than SYSCLK, RPWTH must be set to a value that ensures that the write
FIFO does not underflow due to data being read out of the FIFO faster than
data is written into the FIFO. It is recommended that RPWTH be set to a
value not less than
[4 ´ (XFER + 1)]éê1 - SYSCLKfreq. ùú - éêrg ´ SYSCLKfreq. ùú
ë
PCICLKfreq. û
ë
PCICLKfreq. û
where rg is the minimum number of clock cycles in which GNTB can be
received after REQB has been asserted.
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Register 0x100 : RCAS Indirect Link and Time-slot Select
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R
BUSY
X
Bit 14
R/W
RWB
0
Unused
X
Bit 13
Bit 12
R/W
Reserved
0
Bit 11
R/W
Reserved
0
Bit 10
R/W
LINK[4]
0
Bit 9
R/W
LINK[3]
0
Bit 8
R/W
LINK[2]
0
Bit 7
R/W
LINK[1]
0
Bit 6
R/W
LINK[0]
0
Unused
X
Bit 5
Bit 4
R/W
TSLOT[4]
0
Bit 3
R/W
TSLOT[3]
0
Bit 2
R/W
TSLOT[2]
0
Bit 1
R/W
TSLOT[1]
0
Bit 0
R/W
TSLOT[0]
0
This register provides the receive link and time-slot number used to access the
channel provision RAM. Writing to this register triggers an indirect register
access.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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TSLOT[4:0]:
The indirect time-slot number bits (TSLOT[4:0]) indicate the time-slot to be
configured or interrogated in the indirect access. For a channelised T1/J1
link, time-slots 1 to 24 are valid. For a channelised E1 link, time-slots 1 to 31
are valid. For an H-MVIP link, time-slots 0 to 31 are valid. For unchannelised
links, only time-slot 0 is valid.
LINK[4:0]:
The indirect link number bits (LINK[4:0]) select amongst the 32 receive links
to be configured or interrogated in the indirect access.
Reserved:
The reserved bits must be set low for correct operation of the FREEDM32P256 device.
RWB:
The indirect access control bit (RWB) selects between a configure (write) or
interrogate (read) access to the channel provision RAM. The address to the
channel provision RAM is constructed by concatenating the TSLOT[4:0] and
LINK[4:0] bits. Writing a logic zero to RWB triggers an indirect write
operation. Data to be written is taken from the PROV, the CDLBEN and the
CHAN[7:0] bits of the RCAS Indirect Channel Data register. Writing a logic
one to RWB triggers an indirect read operation. Addressing of the RAM is the
same as in an indirect write operation. The data read can be found in the
PROV, the CDLBEN and the CHAN[7:0] bits of the RCAS Indirect Channel
Data register.
BUSY:
The indirect access status bit (BUSY) reports the progress of an indirect
access. BUSY is set high when this register is written to trigger an indirect
access, and will stay high until the access is complete. At which point, BUSY
will be set low. This register should be polled to determine when data from an
indirect read operation is available in the RCAS Indirect Channel Data
register or to determine when a new indirect write operation may commence.
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Register 0x104 : RCAS Indirect Channel Data
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
CDLBEN
0
Bit 14
R/W
PROV
0
Unused
XH
Bit 13
to
Bit 10
Bit 9
R/W
Reserved
0
Bit 8
R/W
Reserved
0
Bit 7
R/W
CHAN[7]
0
Bit 6
R/W
CHAN[6]
0
Bit 5
R/W
CHAN[5]
0
Bit 4
R/W
CHAN[4]
0
Bit 3
R/W
CHAN[3]
0
Bit 2
R/W
CHAN[2]
0
Bit 1
R/W
CHAN[1]
0
Bit 0
R/W
CHAN[0]
0
This register contains the data read from the channel provision RAM after an
indirect read operation or the data to be inserted into the channel provision RAM
in an indirect write operation.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
CHAN[7:0]:
The indirect data bits (CHAN[7:0]) report the channel number read from the
channel provision RAM after an indirect read operation has completed.
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Channel number to be written to the channel provision RAM in an indirect
write operation must be set up in this register before triggering the write.
CHAN[7:0] reflects the value written until the completion of a subsequent
indirect read operation.
PROV:
The indirect provision enable bit (PROV) reports the channel provision enable
flag read from the channel provision RAM after an indirect read operation has
completed. The provision enable flag to be written to the channel provision
RAM, in an indirect write operation, must be set up in this register before
triggering the write. When PROV is set high, the current receive data byte is
processed as part of the channel as indicated by CHAN[7:0]. When PROV is
set low, the current time-slot does not belong to any channel and the receive
data byte ignored. PROV reflects the value written until the completion of a
subsequent indirect read operation.
CDLBEN:
The indirect channel based diagnostic loopback enable bit (CDLBEN) reports
the loopback enable flag read from channel provision RAM after an indirect
read operation has complete. The loopback enable flag to be written to the
channel provision RAM, in an indirect write operation, must be set up in this
register before triggering the write. When CDLBEN is set high, the current
receive data byte is to be over-written by data retrieved from the loopback
FIFO of the channel as indicated by CHAN[7:0]. When CDLBEN is set low,
the current receive data byte is processed normally. CDLBEN reflects the
value written until the completion of a subsequent indirect read operation.
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Register 0x108 : RCAS Framing Bit Threshold
Bit
Type
Bit 31
to
Bit 7
Function
Default
Unused
XXXXXXXH
Bit 6
R/W
FTHRES[6]
0
Bit 5
R/W
FTHRES[5]
1
Bit 4
R/W
FTHRES[4]
0
Bit 3
R/W
FTHRES[3]
0
Bit 2
R/W
FTHRES[2]
1
Bit 1
R/W
FTHRES[1]
0
Bit 0
R/W
FTHRES[0]
1
This register contains the threshold used by the clock activity monitor to detect
for framing bits/bytes.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
FTHRES[6:0]:
The framing bit threshold bits (FTHRES[6:0]) contains the threshold used by
the clock activity monitor to detect for the presence of framing bits. A counter
in the clock activity monitor of each receive link increments on each rising
edge of SYSCLK and is cleared, when the BSYNC bit of that link is set low,
by each rising edge of the corresponding RCLK[n]. When the BSYNC bit of
that link is set high, the counter is cleared at every fourth rising edge of the
corresponding RCLK[n]. When the counter exceeds the threshold given by
FTHRES[6:0], a framing bit/byte has been detected.
FTHRES[6:0] should be set as a function of the SYSCLK period and the
expected gapping width of RCLK[n] during data bits and during framing
bits/bytes. Legal range of FTHRESH[6:0] is 'b0000001 to 'b1111110.
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Note: For operation with T1/J1 links and SYSCLK = 45 MHz, FTHRESH[6:0]
should be set to ‘b0100101’. The default value of this register reflects this
mode of operation.
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Register 0x10C : RCAS Channel Disable
Bit
Type
Bit 31
to
Bit 16
Bit 15
R/W
Bit 14
to
Bit 10
Function
Default
Unused
XXXXH
CHDIS
0
Unused
XXH
Bit 9
R/W
Reserved
0
Bit 8
R/W
Reserved
0
Bit 7
R/W
DCHAN[7]
0
Bit 6
R/W
DCHAN[6]
0
Bit 5
R/W
DCHAN[5]
0
Bit 4
R/W
DCHAN[4]
0
Bit 3
R/W
DCHAN[3]
0
Bit 2
R/W
DCHAN[2]
0
Bit 1
R/W
DCHAN[1]
0
Bit 0
R/W
DCHAN[0]
0
This register controls the disabling of one specific channel to allow orderly
provisioning of time-slots associated with that channel.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
DCHAN[7:0]:
The disable channel number bits (DCHAN[7:0]) selects the channel to be
disabled. When CHDIS is set high, the channel specified by DCHAN[7:0] is
disabled. Data in time-slots associated with the specified channel is ignored.
When CHDIS is set low, the channel specified by DCHAN[7:0] operates
normally.
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CHDIS:
The channel disable bit (CHDIS) controls the disabling of the channels
specified by DCHAN[7:0]. When CHDIS is set high, the channel selected by
DCHAN[7:0] is disabled. Data in time-slots associated with the specified
channel is ignored. When CHDIS is set low, the channel specified by
DCHAN[7:0] operates normally.
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Register 0x180 – 0x188 : RCAS Links #0 to #2 Configuration
Bit
Type
Bit 31
to
Bit 5
Bit 4
R/W
Bit 3
Function
Default
Unused
XXXXXXXH
BSYNC
0
Unused
X
Bit 2
R/W
MODE[2]
0
Bit 1
R/W
MODE[1]
0
Bit 0
R/W
MODE[0]
0
This register configures operational modes of receive links #0 to #2.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
MODE[2:0]:
The mode select bits (MODE[2:0]) configures the corresponding receive link.
Table 16 details this procedure. When link 4m (0£m£7) is configured for
operation in 8.192 Mbps H-MVIP mode (MODE[2:0]=”111”), data cannot be
received on links 4m+1, 4m+2 and 4m+3. However, links 4m+1, 4m+2 and
4m+3 must be configured for 8.192 Mbps H-MVIP mode for correct operation
of the RCAS256. From a channel assignment point of view in the RCAS256
(Registers 0x100, 0x104), time-slots 0 through 31 of the H-MVIP link are
treated as time-slots 0 through 31 of link 4m, time-slots 32 through 63 of the
H-MVIP link are treated as time-slots 0 through 31 of link 4m+1, time-slots 64
through 95 of the H-MVIP link are treated as time-slots 0 through 31 of link
4m+2 and time-slots 96 through 127 of the H-MVIP link are treated as timeslots 0 through 31 of link 4m+3.
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Table 16 - Receive Links #0 to #2 Configuration
MODE[2:0]
000
001
010
011
100
101
110
111
Link Configuration
Unchannelised
Channelised T1/J1 (24 time slots labeled 1-24)
Channelised E1 (31 time slots labeled 1-31)
2 Mbps H-MVIP (32 time slots labeled 0-31)
Reserved
Reserved
Reserved
8 Mbps H-MVIP (128 time slots mapped to timeslots 0 through 31 of links 4m, 4m+1, 4m+2 and
4m+3)
BSYNC:
The byte synchronization enable bit (BSYNC) controls the interpretation of
gaps in RCLK[n] when link #n is in unchannelised mode (MODE[2:0]=”000”).
When BSYNC is set high, the data bit on RD[n] clocked in by the first rising
edge of RCLK[n] after an extended quiescent period is considered to be the
most significant bit of a data byte. When BSYNC is set low, gaps in RCLK[n]
carry no special significance. BSYNC is ignored when MODE[2:0]¹”000”.
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Register 0x18C – 0x1FC : RCAS Links #3 to #31 Configuration
Bit
Type
Bit 31
to
Bit 3
Function
Default
Unused
XXXXXXXXH
Bit 2
R/W
MODE[2]
0
Bit 1
R/W
MODE[1]
0
Bit 0
R/W
MODE[0]
0
This register configures operational modes of receive links #3 to #31.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
MODE[2:0]:
The mode select bits (MODE[2:0]) configures the corresponding receive link.
Table 17 details this procedure. When link 4m (0£m£7) is configured for
operation in 8.192 Mbps H-MVIP mode (MODE[2:0]=”111”), data cannot be
received on links 4m+1, 4m+2 and 4m+3. However, links 4m+1, 4m+2 and
4m+3 must be configured for 8.192 Mbps H-MVIP mode for correct operation
of the RCAS256. From a channel assignment point of view in the RCAS256
(Registers 0x100, 0x104), time-slots 0 through 31 of the H-MVIP link are
treated as time-slots 0 through 31 of link 4m, time-slots 32 through 63 of the
H-MVIP link are treated as time-slots 0 through 31 of link 4m+1, time-slots 64
through 95 of the H-MVIP link are treated as time-slots 0 through 31 of link
4m+2 and time-slots 96 through 127 of the H-MVIP link are treated as timeslots 0 through 31 of link 4m+3.
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Table 17 - Receive Links #3 to #31 Configuration
MODE[2:0]
000
001
010
011
100
101
110
111
Link Configuration
Unchannelised
Channelised T1/J1 (24 time slots labeled 1-24)
Channelised E1 (31 time slots labeled 1-31)
2 Mbps H-MVIP (32 time slots labeled 0-31)
Reserved
Reserved
Reserved
8 Mbps H-MVIP (128 time slots mapped to timeslots 0 through 31 of links 4m, 4m+1, 4m+2 and
4m+3)
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Register 0x200 : RHDL Indirect Channel Select
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R
BUSY
X
Bit 14
R/W
CRWB
0
Unused
XH
Bit 13
to
Bit 10
Bit 9
R/W
Reserved
0
Bit 8
R/W
Reserved
0
Bit 7
R/W
CHAN[7]
0
Bit 6
R/W
CHAN[6]
0
Bit 5
R/W
CHAN[5]
0
Bit 4
R/W
CHAN[4]
0
Bit 3
R/W
CHAN[3]
0
Bit 2
R/W
CHAN[2]
0
Bit 1
R/W
CHAN[1]
0
Bit 0
R/W
CHAN[0]
0
This register provides the channel number used to access the receive channel
provision RAM. Writing to this register triggers an indirect channel register
access.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
CHAN[7:0]:
The indirect channel number bits (CHAN[7:0]) indicate the receive channel to
be configured or interrogated in the indirect access.
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CRWB:
The channel indirect access control bit (CRWB) selects between a configure
(write) or interrogate (read) access to the receive channel provision RAM.
Writing a logic zero to CRWB triggers an indirect write operation. Data to be
written is taken from the Indirect Channel Data registers. Writing a logic one
to CRWB triggers an indirect read operation. The data read can be found in
the Indirect Channel Data registers.
BUSY:
The indirect access status bit (BUSY) reports the progress of an indirect
access. BUSY is set high when this register is written to trigger an indirect
access, and will stay high until the access is complete. At which point, BUSY
will be set low. This register should be polled to determine when data from an
indirect read operation is available in the RHDL Indirect Channel Data #1 and
#2 registers or to determine when a new indirect write operation may
commence.
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Register 0x204 : RHDL Indirect Channel Data Register #1
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
PROV
0
Bit 14
R/W
STRIP
0
Bit 13
R/W
DELIN
0
Bit 12
R
TAVAIL
X
Bit 11
W
Reserved
X
Bit 10
W
FPTR[10]
X
Bit 9
W
FPTR[9]
X
Bit 8
W
FPTR[8]
X
Bit 7
W
FPTR[7]
X
Bit 6
W
FPTR[6]
X
Bit 5
W
FPTR[5]
X
Bit 4
W
FPTR[4]
X
Bit 3
W
FPTR[3]
X
Bit 2
W
FPTR[2]
X
Bit 1
W
FPTR[1]
X
Bit 0
W
FPTR[0]
X
This register contains data read from the channel provision RAM after an indirect
read operation or data to be inserted into the channel provision RAM in an
indirect write operation.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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FPTR[10:0]:
The indirect FIFO block pointer (FPTR[10:0]) identifies one of the blocks of
the circular linked list in the partial packet buffer used in the logical FIFO of
the current channel. The FIFO pointer to be written to the channel provision
RAM, in an indirect write operation, must be set up in this register before
triggering the write. The FIFO pointer value can be any one of the blocks
provisioned to form the circular buffer.
Reserved:
The reserved bit must be set low for correct operation of the FREEDM32P256 device.
TAVAIL:
The indirect transaction available bit (TAVAIL) reports the fill level of the
partial packet buffer used in the logical FIFO of the current channel. TAVAIL
is set high when the FIFO of the current channel contains sufficient data, as
controlled by XFER[3:0], to request a DMA transfer to the host memory.
TAVAIL is set low when the amount of receive data is too small to require a
transfer to host memory. TAVAIL is updated by an indirect channel read
operation.
DELIN:
The indirect delineate enable bit (DELIN) configures the HDLC processor to
perform flag sequence delineation and bit de-stuffing on the incoming data
stream. The delineate enable bit to be written to the channel provision RAM,
in an indirect channel write operation, must be set up in this register before
triggering the write. When DELIN is set high, flag sequence delineation and
bit de-stuffing is performed on the incoming data stream. When DELIN is set
low, the HDLC processor does not perform any processing (flag sequence
delineation, bit de-stuffing nor CRC verification) on the incoming stream.
DELIN reflects the value written until the completion of a subsequent indirect
channel read operation.
STRIP:
The indirect frame check sequence discard bit (STRIP) configures the HDLC
processor to remove the CRC from the incoming frame when writing the data
to the channel FIFO. The FCS discard bit to be written to the channel
provision RAM, in an indirect channel write operation, must be set up in this
register before triggering the write. When STRIP is set high and CRC[1:0] is
not equal to "00", the received CRC value is not written to the FIFO. When
STRIP is set low, the received CRC value is written to the FIFO. The bytes in
buffer field of the RPD correctly reflect the presence/absence of CRC bytes in
the buffer. The value of STRIP is ignored when DELIN is low. STRIP reflects
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the value written until the completion of a subsequent indirect channel read
operation.
PROV:
The indirect provision enable bit (PROV) reports the channel provision enable
flag read from the channel provision RAM after an indirect channel read
operation has completed. The provision enable flag to be written to the
channel provision RAM, in an indirect write operation, must be set up in this
register before triggering the write. When PROV is set high, the HDLC
processor will process data on the channel specified by CHAN[7:0]. When
PROV is set low, the HDLC processor will ignore data on the channel
specified by CHAN[7:0]. PROV reflects the value written until the completion
of a subsequent indirect channel read operation.
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Register 0x208 : RHDL Indirect Channel Data Register #2
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
7BIT
0
Bit 14
R/W
PRIORITY
0
Bit 13
R/W
INVERT
0
Unused
X
Bit 12
Bit 11
R/W
CRC[1]
0
Bit 10
R/W
CRC[0]
0
Bit 9
R/W
OFFSET[1]
0
Bit 8
R/W
OFFSET[0]
0
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
R/W
XFER[3]
0
Bit 2
R/W
XFER[2]
0
Bit 1
R/W
XFER[1]
0
Bit 0
R/W
XFER[0]
0
This register contains data read from the channel provision RAM after an indirect
read operation or data to be inserted into the channel provision RAM in an
indirect write operation.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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XFER[3:0]:
The indirect channel transfer size (XFER[3:0]) configures the amount of data
transferred in each transaction. The channel transfer size to be written to the
channel provision RAM, in an indirect write operation, must be set up in this
register before triggering the write. When the channel FIFO depth reaches
the depth specified by XFER[3:0] or when an end-of-packet exists in the
FIFO, a request will be made to the RMAC256 to initiate a PCI write access
to transfer the data to the PCI host. Channel transfer size is measured in 16
byte blocks. The amount of data transferred and the depth threshold are
specified by given setting is:
XFER[3:0] + 1 blocks = 16 * (XFER[3:0] + 1) bytes
XFER[3:0] should be set such that the number of blocks transferred is at
least two fewer than the total allocated to the associated channel. XFER[3:0]
reflects the value written until the completion of a subsequent indirect channel
read operation.
OFFSET[1:0]:
The packet byte offset (OFFSET[1:0]) configures the partial packet processor
to insert invalid bytes at the beginning of a packet stored in the channel FIFO.
The value of OFFSET[1:0] to be written to the channel provision RAM, in an
indirect channel write operation, must be set up in this register before
triggering the write. The number of bytes inserted before the beginning of a
HDLC packet is defined by the binary value of OFFSET[1:0]. OFFSET[1:0]
reflects the value written until the completion of a subsequent indirect channel
read operation.
CRC[1:0]:
The CRC algorithm bits (CRC[1:0]) configures the HDLC processor to
perform CRC verification on the incoming data stream. The value of
CRC[1:0] to be written to the channel provision RAM, in an indirect channel
write operation, must be set up in this register before triggering the write.
CRC[1:0] is ignored when DELIN is low. CRC[1:0] reflects the value written
until the completion of a subsequent indirect channel read operation.
Table 18 – CRC[1:0] Settings
CRC[1]
CRC[0]
Operation
0
0
No Verification
0
1
CRC-CCITT
1
0
CRC-32
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CRC[1]
CRC[0]
Operation
1
1
Reserved
INVERT:
The HDLC data inversion bit (INVERT) configures the HDLC processor to
logically invert the incoming HDLC stream from the RCAS256 before
processing it. The value of INVERT to be written to the channel provision
RAM, in an indirect channel write operation, must be set up in this register
before triggering the write. When INVERT is set to one, the HDLC stream is
logically inverted before processing. When INVERT is set to zero, the HDLC
stream is not inverted before processing. INVERT reflects the value written
until the completion of a subsequent indirect channel read operation.
PRIORITY:
The channel FIFO priority bit (PRIORITY) informs the partial packet
processor that the channel has precedence over other channels when being
serviced by the RMAC256 block for transfer to the PCI host. The value of
PRIORITY to be written to the channel provision RAM, in an indirect channel
write operation, must be set up in this register before triggering the write.
Channel FIFOs with PRIORITY set to one are serviced by the RMAC256
before channel FIFOs with PRIORITY set to zero. Channels with an HDLC
data rate to FIFO size ratio that is significantly higher than other channels
should have PRIORITY set to one. PRIORITY reflects the value written until
the completion of a subsequent indirect channel read operation.
7BIT:
The 7BIT enable bit (7BIT) configures the HDLC processor to ignore the least
significant bit of each octet in the corresponding link RD[n]. The value of
7BIT to be written to the channel provision RAM, in an indirect channel write
operation, must be set up in this register before triggering the write. When
7BIT is set high, the least significant bit (last bit of each octet received), is
ignored. When 7BIT is set low, the entire receive data stream is processed.
7BIT reflects the value written until the completion of a subsequent indirect
channel read operation.
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Register 0x210 : RHDL Indirect Block Select
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R
BUSY
X
Bit 14
R/W
BRWB
X
Bit 13
Unused
X
Bit 12
Unused
X
Bit 11
Unused
X
Bit 10
R/W
BLOCK[10]
X
Bit 9
R/W
BLOCK[9]
X
Bit 8
R/W
BLOCK[8]
X
Bit 7
R/W
BLOCK[7]
X
Bit 6
R/W
BLOCK[6]
X
Bit 5
R/W
BLOCK[5]
X
Bit 4
R/W
BLOCK[4]
X
Bit 3
R/W
BLOCK[3]
X
Bit 2
R/W
BLOCK[2]
X
Bit 1
R/W
BLOCK[1]
X
Bit 0
R/W
BLOCK[0]
X
This register provides the block number used to access the block pointer RAM.
Writing to this register triggers an indirect block register access.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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BLOCK[10:0]:
The indirect block number (BLOCK[10:0]) indicate the block to be configured
or interrogated in the indirect access.
Reserved:
The reserved bit must be set low for correct operation of the FREEDM32P256 device.
BRWB:
The block indirect access control bit (BRWB) selects between a configure
(write) or interrogate (read) access to the block pointer RAM. Writing a logic
zero to BRWB triggers an indirect block write operation. Data to be written is
taken from the Indirect Block Data register. Writing a logic one to BRWB
triggers an indirect block read operation. The data read can be found in the
Indirect Block Data register.
BUSY:
The indirect access status bit (BUSY) reports the progress of an indirect
access. BUSY is set high when this register is written to trigger an indirect
access, and will stay high until the access is complete. At which point, BUSY
will be set low. This register should be polled to determine when data from an
indirect read operation is available in the RHDL Indirect Block Data register or
to determine when a new indirect write operation may commence.
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Register 0x214 : RHDL Indirect Block Data
Bit
Type
Bit 31
to
Bit 12
Function
Default
Unused
XXXXXH
Bit 11
R/W
Reserved
X
Bit 10
R/W
BPTR[10]
0
Bit 9
R/W
BPTR[9]
0
Bit 8
R/W
BPTR[8]
0
Bit 7
R/W
BPTR[7]
0
Bit 6
R/W
BPTR[6]
0
Bit 5
R/W
BPTR[5]
0
Bit 4
R/W
BPTR[4]
0
Bit 3
R/W
BPTR[3]
0
Bit 2
R/W
BPTR[2]
0
Bit 1
R/W
BPTR[1]
0
Bit 0
R/W
BPTR[0]
0
This register contains data read from the block pointer RAM after an indirect
block read operation or data to be inserted into the block pointer RAM in an
indirect block write operation.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
BPTR[10:0]:
The indirect block pointer (BPTR[10:0]) configures the block pointer of the
block specified by the Indirect Block Select register. The block pointer to be
written to the block pointer RAM, in an indirect write operation, must be set up
in this register before triggering the write. The block pointer value is the block
number of the next block in the linked list. A circular list of blocks must be
formed in order to use the block list as a receive channel FIFO buffer.
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BPTR[10:0] reflects the value written until the completion of a subsequent
indirect block read operation. When provisioning a channel FIFO, all block
pointers must be re-written to properly initialize the FIFO.
Reserved:
The reserved bit must be set low for correct operation of the FREEDM32P256 device.
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Register 0x220 : RHDL Configuration
Bit
Type
Bit 31
to
Bit 10
Function
Default
Unused
XXXXXXH
Bit 9
R/W
LENCHK
0
Bit 8
R/W
TSTD
0
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
Unused
X
Bit 0
Unused
X
This register configures all provisioned receive channels.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
TSTD:
The telecom standard bit (TSTD) controls the bit ordering of the HDLC data
transferred to the PCI host. When TSTD is set low, the least significant bit of
the each byte on the PCI bus (AD[0], AD[8], AD[16] and AD[24]) is the first
HDLC bit received and the most significant bit of each byte (AD[7], AD[15],
AD[23] and AD[31]) is the last HDLC bit received (datacom standard). When
TSTD is set high, AD[0], AD[8], AD[16] and AD[24] are the last HDLC bit
received and AD[7], AD[15], AD[23] and AD[31] are the first HDLC bit
received (telecom standard).
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LENCHK:
The packet length error check bit (LENCHK) controls the checking of receive
packets that are longer than the maximum programmed length. When
LENCHK is set high, receive packets are aborted and the remainder of the
frame discarded when the packet exceeds the maximum packet length given
by MAX[15:0]. When LENCHK is set low, receive packets are not checked
for maximum size and MAX[15:0] must be set to 'hFFFF.
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Register 0x224 : RHDL Maximum Packet Length
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
MAX[15]
1
Bit 14
R/W
MAX[14]
1
Bit 13
R/W
MAX[13]
1
Bit 12
R/W
MAX[12]
1
Bit 11
R/W
MAX[11]
1
Bit 10
R/W
MAX[10]
1
Bit 9
R/W
MAX[9]
1
Bit 8
R/W
MAX[8]
1
Bit 7
R/W
MAX[7]
1
Bit 6
R/W
MAX[6]
1
Bit 5
R/W
MAX[5]
1
Bit 4
R/W
MAX[4]
1
Bit 3
R/W
MAX[3]
1
Bit 2
R/W
MAX[2]
1
Bit 1
R/W
MAX[1]
1
Bit 0
R/W
MAX[0]
1
This register configures the maximum legal HDLC packet byte length.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
MAX[15:0]:
The maximum HDLC packet length (MAX[15:0]) configures the FREEDM32P256 to reject HDLC packets longer than a maximum size when LENCHK
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is set high. Receive packets with total length, including address, control,
information and FCS fields, greater than MAX[15:0] bytes are aborted. When
LENCHK is set low, aborts are not generated regardless of packet length and
MAX[15:0] must be set to 'hFFFF.
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Register 0x280 : RMAC Control
Bit
Type
Bit 31
to
Bit 13
Function
Default
Unused
XXXXXH
Bit 12
R/W
Reserved
0
Bit 11
R/W
RPQ_SFN[1]
0
Bit 10
R/W
RPQ_SFN[0]
0
Bit 9
R/W
RPQ_LFN[1]
0
Bit 8
R/W
RPQ_LFN[0]
0
Bit 7
R/W
RPQ_RDYN[2]
0
Bit 6
R/W
RPQ_RDYN[1]
0
Bit 5
R/W
RPQ_RDYN[0]
0
Bit 4
R/W
RAWMAX[1]
1
Bit 3
R/W
RAWMAX[0]
1
Bit 2
R/W
SCACHE
1
Bit 1
R/W
LCACHE
1
Bit 0
R/W
ENABLE
0
This register configures the RMAC256 block.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
ENABLE:
The ENABLE bit determines whether or not the RMAC256 accepts data from
the RHDL256 block and sends it to host memory. When set to 1, these tasks
are enabled. When set to 0, they are disabled.
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LCACHE:
The large buffer cache enable bit (LCACHE) enables caching of Large Buffer
RPDRs. When LCACHE is set high, RPDRs are fetched from the RPDR
Large Buffer Free Queue in groups of up to six. When LCACHE is set low,
RPDRs are fetched one at a time.
SCACHE:
The small buffer cache enable bit (SCACHE) enables caching of Small Buffer
RPDRs. When SCACHE is set high, RPDRs are fetched from the RPDR
Small Buffer Free Queue in groups of up to six. When SCACHE is set low,
RPDRs are fetched one at a time.
RAWMAX[1:0]:
The RAWMAX[1:0] field determines how ‘raw’ (i.e. non packet delimited) data
is written to host memory. Raw data is written to buffers in host memory in
the same manner as packet delimited data. Whenever RAWMAX[1:0] + 1
buffers have been filled, the resulting buffer chain is placed in the ready
queue.
RPQ_RDYN[2:0]:
The RPQ_RDYN[2:0] field sets the number of receive packet descriptor
references (RPDRs) that must be placed onto the RPDR ready queue before
the RPDR ready interrupt (RPQRDYI) is asserted, as follows:
Table 19 – RPQ_RDYN[2:0] settings
RPQ_RDYN[2:0]
No of RPDRs
000
1
001
4
010
6
011
8
100
16
101
32
110
Reserved
111
Reserved
If the value of RPQ_RDYN[2:0] is altered, the new value does not become
effective until after the RPQRDYI interrupt is next generated.
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RPQ_LFN[1:0]:
The RPQ_LFN[1:0] field sets the number of times that a block of RPDRs are
read from the Large Buffer Free Queue to the RMAC256s internal cache
before the RPDR Large Buffer Free Queue interrupt (RPQLFI) is asserted, as
follows:
Table 20 – RPQ_LFN[1:0] Settings
RPQ_LFN[1:0]
No of Reads
00
1
01
4
10
8
11
Reserved
If the value of RPQ_LFN[1:0] is altered, the new value does not become
effective until after the RPQLFI interrupt is next generated.
RPQ_SFN[1:0]:
The RPQ_SFN[1:0] field sets the number of times that a block of RPDRs are
read from the Small Buffer Free Queue to the RMAC256s internal cache
before the RPDR Small Buffer Free Queue interrupt (RPQSFI) is asserted, as
follows:
Table 21 – RPQ_SFN[1:0] Settings
RPQ_SFN[1:0]
No of Reads
00
1
01
4
10
8
11
Reserved
If the value of RPQ_SFN[1:0] is altered, the new value does not become
effective until after the RPQSFI interrupt is next generated.
Reserved:
The reserved bit must be set low for correct operation of the FREEDM32P256 device.
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Register 0x284 : RMAC Indirect Channel Provisioning
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R
BUSY
X
Bit 14
R/W
RWB
0
Unused
XH
Bit 13
to
Bit 11
Bit 10
R/W
PROV
0
Bit 9
R/W
Reserved
0
Bit 8
R/W
Reserved
0
Bit 7
R/W
CHAN[7]
0
Bit 6
R/W
CHAN[6]
0
Bit 5
R/W
CHAN[5]
0
Bit 4
R/W
CHAN[4]
0
Bit 3
R/W
CHAN[3]
0
Bit 2
R/W
CHAN[2]
0
Bit 1
R/W
CHAN[1]
0
Bit 0
R/W
CHAN[0]
0
The Channel Provisioning Register is used to temporarily unprovision channels,
and also to query the provision status of channels. Channel is permanently
provisioned and can only be unprovisioned transiently. When a channel is
unprovisioned, a partially received packet, if any, will be flushed and marked as
unprovisioned in the RPDRR queue status field. The channel then returns to
being provisioned automatically.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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CHAN[7:0]:
The indirect data bits (CHAN[7:0]) report the channel number read from the
RMAC256 internal memory after an indirect read operation has completed.
Channel number to be written to the RMAC256 internal memory in an indirect
write operation must be set up in this register before triggering the write.
CHAN[7:0] reflects the value written until the completion of a subsequent
indirect read operation.
PROV:
The indirect provision enable bit (PROV) reports the channel provision enable
flag read from the RMAC256 internal memory after an indirect read operation
has completed. The provision enable flag to be written to the RMAC256
internal memory, in an indirect write operation, must be set up in this register
before triggering the write. When PROV is set high, the channel indicated by
CHAN[7:0] is provisioned. When PROV is set low, the channel indicated by
CHAN[7:0] is unprovisioned temporarily. Any partially received packets are
flushed and the status in the RPDRR queue is marked unprovisioned. The
channel then returns to being provisioned and PROV will report a logic high
after the next indirect read operation. PROV reflects the value written until
the completion of a subsequent indirect read operation.
RWB:
The Read/Write Bar (RWB) bit selects between a provisioning/unprovisioning
operation (write) or a query operation (read). Writing a logic 0 to RWB
triggers the provisioning or unprovisioning of a channel as specified by
CHAN[7:0] and PROV. Writing a logic 1 to RWB triggers a query of the
channel specified by CHAN[7:0].
BUSY:
The indirect access status bit (BUSY) reports the progress of an indirect
access. BUSY is set high when this register is written to trigger an indirect
access, and will stay high until the access is complete. At which point, BUSY
will be set low. This register should be polled to determine when data from an
indirect read operation is available or to determine when a new indirect write
operation may commence.
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Register 0x288 : RMAC Packet Descriptor Table Base LSW
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
RPDTB[15]
0
Bit 14
R/W
RPDTB[14]
0
Bit 13
R/W
RPDTB[13]
0
Bit 12
R/W
RPDTB[12]
0
Bit 11
R/W
RPDTB[11]
0
Bit 10
R/W
RPDTB[10]
0
Bit 9
R/W
RPDTB[9]
0
Bit 8
R/W
RPDTB[8]
0
Bit 7
R/W
RPDTB[7]
0
Bit 6
R/W
RPDTB[6]
0
Bit 5
R/W
RPDTB[5]
0
Bit 4
R/W
RPDTB[4]
0
Bit 3
R/W
RPDTB[3]
0
Bit 2
R/W
RPDTB[2]
0
Bit 1
R/W
RPDTB[1]
0
Bit 0
R/W
RPDTB[0]
0
This register provides the less significant word of the Receive Descriptor Table
Base address. The contents of this register is held in a holding register until a
write access to the companion RMAC Receive Descriptor Table Base MSW
register.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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Register 0x28C : RMAC Packet Descriptor Table Base MSW
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
RPDTB[31]
0
Bit 14
R/W
RPDTB[30]
0
Bit 13
R/W
RPDTB[29]
0
Bit 12
R/W
RPDTB[28]
0
Bit 11
R/W
RPDTB[27]
0
Bit 10
R/W
RPDTB[26]
0
Bit 9
R/W
RPDTB[25]
0
Bit 8
R/W
RPDTB[24]
0
Bit 7
R/W
RPDTB[23]
0
Bit 6
R/W
RPDTB[22]
0
Bit 5
R/W
RPDTB[21]
0
Bit 4
R/W
RPDTB[20]
0
Bit 3
R/W
RPDTB[19]
0
Bit 2
R/W
RPDTB[18]
0
Bit 1
R/W
RPDTB[17]
0
Bit 0
R/W
RPDTB[16]
0
This register provides the more significant word of the Receive Descriptor Table
Base address. The contents of the companion RMAC Receive Descriptor Table
Base LSW register is held in a holding register until a write access to this
register, at which point, the base address of the receive packet descriptor table is
updated.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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RPDTB[31:0]:
The receive packet descriptor table base bits (RPDTB[31:0]) provides the
base address of the Receive Packet Descriptor Table in PCI host memory.
This register is initialised by the host. To calculate the physical address of a
RPD, the 15 bit RPD offset must be added to bits 31 to 4 of the Receive
Packet Descriptor Table Base (RPDTB[31:4]).
The table must be on a 16 byte boundary and thus the least significant four
bits must be written to logic zero.
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Register 0x290 : RMAC Queue Base LSW
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
RQB[15]
0
Bit 14
R/W
RQB[14]
0
Bit 13
R/W
RQB[13]
0
Bit 12
R/W
RQB[12]
0
Bit 11
R/W
RQB[11]
0
Bit 10
R/W
RQB[10]
0
Bit 9
R/W
RQB[9]
0
Bit 8
R/W
RQB[8]
0
Bit 7
R/W
RQB[7]
0
Bit 6
R/W
RQB[6]
0
Bit 5
R/W
RQB[5]
0
Bit 4
R/W
RQB[4]
0
Bit 3
R/W
RQB[3]
0
Bit 2
R/W
RQB[2]
0
Bit 1
R/W
RQB[1]
0
Bit 0
R/W
RQB[0]
0
This register provides the less significant word of the Receive Queue Base
address. The contents of this register is held in a holding register until a write
access to the companion RMAC Receive Queue Base MSW register.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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Register 0x294 : RMAC Queue Base MSW
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
RQB[31]
0
Bit 14
R/W
RQB[30]
0
Bit 13
R/W
RQB[29]
0
Bit 12
R/W
RQB[28]
0
Bit 11
R/W
RQB[27]
0
Bit 10
R/W
RQB[26]
0
Bit 9
R/W
RQB[25]
0
Bit 8
R/W
RQB[24]
0
Bit 7
R/W
RQB[23]
0
Bit 6
R/W
RQB[22]
0
Bit 5
R/W
RQB[21]
0
Bit 4
R/W
RQB[20]
0
Bit 3
R/W
RQB[19]
0
Bit 2
R/W
RQB[18]
0
Bit 1
R/W
RQB[17]
0
Bit 0
R/W
RQB[16]
0
This register provides the more significant word of the Receive Queue Base
address. The contents of the companion RMAC Receive Queue Base LSW
register is held in a holding register until a write access to this register, at which
point, the base address of the receive queue is updated.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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RQB[31:0]:
The receive queue base bits (RQB[31:0]) provides the base address of the
Large Buffer RPDR Free, Small Buffer RPDR Free and RPDR Ready queues
in PCI host memory. This register is initialised by the host. To calculate the
physical address of a particular receive queue element, the RQB bits are
added with the appropriate queue start, end, read or write index registers to
form the physical address.
The base address must be dword aligned and thus the least significant two
bits must be written to logic zero.
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Register 0x298 : RMAC Packet Descriptor Reference Large Buffer Free
Queue Start
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
RPDRLFQS[15]
0
Bit 14
R/W
RPDRLFQS[14]
0
Bit 13
R/W
RPDRLFQS[13]
0
Bit 12
R/W
RPDRLFQS[12]
0
Bit 11
R/W
RPDRLFQS[11]
0
Bit 10
R/W
RPDRLFQS[10]
0
Bit 9
R/W
RPDRLFQS[9]
0
Bit 8
R/W
RPDRLFQS[8]
0
Bit 7
R/W
RPDRLFQS[7]
0
Bit 6
R/W
RPDRLFQS[6]
0
Bit 5
R/W
RPDRLFQS[5]
0
Bit 4
R/W
RPDRLFQS[4]
0
Bit 3
R/W
RPDRLFQS[3]
0
Bit 2
R/W
RPDRLFQS[2]
0
Bit 1
R/W
RPDRLFQS[1]
0
Bit 0
R/W
RPDRLFQS[0]
0
This register provides the Packet Descriptor Reference Large Buffer Free Queue
start address.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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RPDRLFQS[15:0]:
The receive packet descriptor reference (RPDR) large buffer free queue start
bits (RPDRLFQS[15:0]) define bits 17 to 2 of the Receive Packet Descriptor
Reference Large Buffer Free Queue start address. This register is initialised
by the host. The physical start address of the RPDRLF queue is the sum of
RPDRLFQS[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC
Receive Queue Base register.
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Register 0x29C : RMAC Packet Descriptor Reference Large Buffer Free
Queue Write
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
RPDRLFQW[15]
0
Bit 14
R/W
RPDRLFQW[14]
0
Bit 13
R/W
RPDRLFQW[13]
0
Bit 12
R/W
RPDRLFQW[12]
0
Bit 11
R/W
RPDRLFQW[11]
0
Bit 10
R/W
RPDRLFQW[10]
0
Bit 9
R/W
RPDRLFQW[9]
0
Bit 8
R/W
RPDRLFQW[8]
0
Bit 7
R/W
RPDRLFQW[7]
0
Bit 6
R/W
RPDRLFQW[6]
0
Bit 5
R/W
RPDRLFQW[5]
0
Bit 4
R/W
RPDRLFQW[4]
0
Bit 3
R/W
RPDRLFQW[3]
0
Bit 2
R/W
RPDRLFQW[2]
0
Bit 1
R/W
RPDRLFQW[1]
0
Bit 0
R/W
RPDRLFQW[0]
0
This register provides the Packet Descriptor Reference Large Buffer Free Queue
write address.
Notes
1. This register is not byte addressable. Writing to this register modifies all the
bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are
not implemented. However, when all four byte enables are negated, no
access is made to this register.
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2. If consecutive write accesses to this register are performed, they must be
spaced at least 4 SYSCLK periods apart.
RPDRLFQW[15:0]:
The receive packet descriptor reference (RPDR) large buffer free queue write
bits (RPDRLFQW[15:0]) define bits 17 to 2 of the Receive Packet Descriptor
Reference Large Buffer Free Queue write pointer. This register is initialised
by the host. The physical write address in the RPDRLF queue is the sum of
RPDRLFQW[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC
Receive Queue Base register.
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Register 0x2A0 : RMAC Packet Descriptor Reference Large Buffer Free
Queue Read
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
RPDRLFQR[15]
0
Bit 14
R/W
RPDRLFQR[14]
0
Bit 13
R/W
RPDRLFQR[13]
0
Bit 12
R/W
RPDRLFQR[12]
0
Bit 11
R/W
RPDRLFQR[11]
0
Bit 10
R/W
RPDRLFQR[10]
0
Bit 9
R/W
RPDRLFQR[9]
0
Bit 8
R/W
RPDRLFQR[8]
0
Bit 7
R/W
RPDRLFQR[7]
0
Bit 6
R/W
RPDRLFQR[6]
0
Bit 5
R/W
RPDRLFQR[5]
0
Bit 4
R/W
RPDRLFQR[4]
0
Bit 3
R/W
RPDRLFQR[3]
0
Bit 2
R/W
RPDRLFQR[2]
0
Bit 1
R/W
RPDRLFQR[1]
0
Bit 0
R/W
RPDRLFQR[0]
0
This register provides the Packet Descriptor Reference Large Buffer Free Queue
read address.
Notes
1. This register is not byte addressable. Writing to this register modifies all the
bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are
not implemented. However, when all four byte enables are negated, no
access is made to this register.
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2. If consecutive write accesses to this register are performed, they must be
spaced at least 4 SYSCLK periods apart.
RPDRLFQR[15:0]:
The receive packet descriptor reference (RPDR) large buffer free queue read
bits (RPDRLFQR[15:0]) define bits 17 to 2 of the Receive Packet Descriptor
Reference Large Buffer Free Queue read pointer. This register is initialised
by the host. The physical read address in the RPDRLF queue is the sum of
RPDRLFQR[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC
Receive Queue Base register.
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Register 0x2A4 : RMAC Packet Descriptor Reference Large Buffer Free
Queue End
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
RPDRLFQE[15]
0
Bit 14
R/W
RPDRLFQE[14]
0
Bit 13
R/W
RPDRLFQE[13]
0
Bit 12
R/W
RPDRLFQE[12]
0
Bit 11
R/W
RPDRLFQE[11]
0
Bit 10
R/W
RPDRLFQE[10]
0
Bit 9
R/W
RPDRLFQE[9]
0
Bit 8
R/W
RPDRLFQE[8]
0
Bit 7
R/W
RPDRLFQE[7]
0
Bit 6
R/W
RPDRLFQE[6]
0
Bit 5
R/W
RPDRLFQE[5]
0
Bit 4
R/W
RPDRLFQE[4]
0
Bit 3
R/W
RPDRLFQE[3]
0
Bit 2
R/W
RPDRLFQE[2]
0
Bit 1
R/W
RPDRLFQE[1]
0
Bit 0
R/W
RPDRLFQE[0]
0
This register provides the Packet Descriptor Reference Large Buffer Free Queue
end address.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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RPDRLFQE[15:0]:
The receive packet descriptor reference (RPDR) large buffer free queue end
bits (RPDRLFQE[15:0]) define bits 17 to 2 of the Receive Packet Descriptor
Reference Large Buffer Free Queue end address. This register is initialised
by the host. The physical end address in the RPDRLF queue is the sum of
RPDRLFQE[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC
Receive Queue Base register.
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Register 0x2A8 : RMAC Packet Descriptor Reference Small Buffer Free
Queue Start
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
RPDRSFQS[15]
0
Bit 14
R/W
RPDRSFQS[14]
0
Bit 13
R/W
RPDRSFQS[13]
0
Bit 12
R/W
RPDRSFQS[12]
0
Bit 11
R/W
RPDRSFQS[11]
0
Bit 10
R/W
RPDRSFQS[10]
0
Bit 9
R/W
RPDRSFQS[9]
0
Bit 8
R/W
RPDRSFQS[8]
0
Bit 7
R/W
RPDRSFQS[7]
0
Bit 6
R/W
RPDRSFQS[6]
0
Bit 5
R/W
RPDRSFQS[5]
0
Bit 4
R/W
RPDRSFQS[4]
0
Bit 3
R/W
RPDRSFQS[3]
0
Bit 2
R/W
RPDRSFQS[2]
0
Bit 1
R/W
RPDRSFQS[1]
0
Bit 0
R/W
RPDRSFQS[0]
0
This register provides the Packet Descriptor Reference Small Buffer Free Queue
start address.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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RPDRSFQS[15:0]:
The receive packet descriptor reference (RPDR) small buffer free queue start
bits (RPDRSFQS[15:0]) define bits 17 to 2 of the Receive Packet Descriptor
Reference Small Buffer Free Queue start address. This register is initialised
by the host. The physical start address of the RPDRSF queue is the sum of
RPDRSFQS[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC
Receive Queue Base register.
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Register 0x2AC : RMAC Packet Descriptor Reference Small Buffer Free
Queue Write
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
RPDRSFQW[15]
0
Bit 14
R/W
RPDRSFQW[14]
0
Bit 13
R/W
RPDRSFQW[13]
0
Bit 12
R/W
RPDRSFQW[12]
0
Bit 11
R/W
RPDRSFQW[11]
0
Bit 10
R/W
RPDRSFQW[10]
0
Bit 9
R/W
RPDRSFQW[9]
0
Bit 8
R/W
RPDRSFQW[8]
0
Bit 7
R/W
RPDRSFQW[7]
0
Bit 6
R/W
RPDRSFQW[6]
0
Bit 5
R/W
RPDRSFQW[5]
0
Bit 4
R/W
RPDRSFQW[4]
0
Bit 3
R/W
RPDRSFQW[3]
0
Bit 2
R/W
RPDRSFQW[2]
0
Bit 1
R/W
RPDRSFQW[1]
0
Bit 0
R/W
RPDRSFQW[0]
0
This register provides the Packet Descriptor Reference Small Buffer Free Queue
write address.
Notes
1. This register is not byte addressable. Writing to this register modifies all the
bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are
not implemented. However, when all four byte enables are negated, no
access is made to this register.
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2. If consecutive write accesses to this register are performed, they must be
spaced at least 4 SYSCLK periods apart.
RPDRSFQW[15:0]:
The receive packet descriptor reference (RPDR) small buffer free queue write
bits (RPDRSFQW[15:0]) define bits 17 to 2 of the Receive Packet Descriptor
Reference Small Buffer Free Queue write pointer. This register is initialised
by the host. The physical write address in the RPDRSF queue is the sum of
RPDRSFQW[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC
Receive Queue Base register.
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Register 0x2B0 : RMAC Packet Descriptor Reference Small Buffer Free
Queue Read
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
RPDRSFQR[15]
0
Bit 14
R/W
RPDRSFQR[14]
0
Bit 13
R/W
RPDRSFQR[13]
0
Bit 12
R/W
RPDRSFQR[12]
0
Bit 11
R/W
RPDRSFQR[11]
0
Bit 10
R/W
RPDRSFQR[10]
0
Bit 9
R/W
RPDRSFQR[9]
0
Bit 8
R/W
RPDRSFQR[8]
0
Bit 7
R/W
RPDRSFQR[7]
0
Bit 6
R/W
RPDRSFQR[6]
0
Bit 5
R/W
RPDRSFQR[5]
0
Bit 4
R/W
RPDRSFQR[4]
0
Bit 3
R/W
RPDRSFQR[3]
0
Bit 2
R/W
RPDRSFQR[2]
0
Bit 1
R/W
RPDRSFQR[1]
0
Bit 0
R/W
RPDRSFQR[0]
0
This register provides the Packet Descriptor Reference Small Buffer Free Queue
read address.
Notes
1. This register is not byte addressable. Writing to this register modifies all the
bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are
not implemented. However, when all four byte enables are negated, no
access is made to this register.
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2. If consecutive write accesses to this register are performed, they must be
spaced at least 4 SYSCLK periods apart.
RPDRSFQR[15:0]:
The receive packet descriptor reference (RPDR) small buffer free queue read
bits (RPDRSFQR[15:0]) define bits 17 to 2 of the Receive Packet Descriptor
Reference Small Buffer Free Queue read pointer. This register is initialised
by the host. The physical read address in the RPDRSF queue is the sum of
RPDRSFQR[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC
Receive Queue Base register.
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Register 0x2B4 : RMAC Packet Descriptor Reference Small Buffer Free
Queue End
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
RPDRSFQE[15]
0
Bit 14
R/W
RPDRSFQE[14]
0
Bit 13
R/W
RPDRSFQE[13]
0
Bit 12
R/W
RPDRSFQE[12]
0
Bit 11
R/W
RPDRSFQE[11]
0
Bit 10
R/W
RPDRSFQE[10]
0
Bit 9
R/W
RPDRSFQE[9]
0
Bit 8
R/W
RPDRSFQE[8]
0
Bit 7
R/W
RPDRSFQE[7]
0
Bit 6
R/W
RPDRSFQE[6]
0
Bit 5
R/W
RPDRSFQE[5]
0
Bit 4
R/W
RPDRSFQE[4]
0
Bit 3
R/W
RPDRSFQE[3]
0
Bit 2
R/W
RPDRSFQE[2]
0
Bit 1
R/W
RPDRSFQE[1]
0
Bit 0
R/W
RPDRSFQE[0]
0
This register provides the Packet Descriptor Reference Small Buffer Free Queue
end address.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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RPDRSFQE[15:0]:
The receive packet descriptor reference (RPDR) small buffer free queue end
bits (RPDRSFQE[15:0]) define bits 17 to 2 of the Receive Packet Descriptor
Reference Small Buffer Free Queue end address. This register is initialised
by the host. The physical end address in the RPDRSF queue is the sum of
RPDRSFQE[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC
Receive Queue Base register.
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Register 0x2B8 : RMAC Packet Descriptor Reference Ready Queue Start
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
RPDRRQS[15]
0
Bit 14
R/W
RPDRRQS[14]
0
Bit 13
R/W
RPDRRQS[13]
0
Bit 12
R/W
RPDRRQS[12]
0
Bit 11
R/W
RPDRRQS[11]
0
Bit 10
R/W
RPDRRQS[10]
0
Bit 9
R/W
RPDRRQS[9]
0
Bit 8
R/W
RPDRRQS[8]
0
Bit 7
R/W
RPDRRQS[7]
0
Bit 6
R/W
RPDRRQS[6]
0
Bit 5
R/W
RPDRRQS[5]
0
Bit 4
R/W
RPDRRQS[4]
0
Bit 3
R/W
RPDRRQS[3]
0
Bit 2
R/W
RPDRRQS[2]
0
Bit 1
R/W
RPDRRQS[1]
0
Bit 0
R/W
RPDRRQS[0]
0
This register provides the Packet Descriptor Reference Ready Queue start
address.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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RPDRRQS[15:0]:
The receive packet descriptor reference (RPDR) ready queue start bits
(RPDRRQS[15:0]) define bits 17 to 2 of the Receive Packet Descriptor
Reference Ready Queue start address. This register is initialised by the
host. The physical start address of the RPDRR queue is the sum of
RPDRRQS[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC
Receive Queue Base register.
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Register 0x2BC : RMAC Packet Descriptor Reference Ready Queue Write
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
RPDRRQW[15]
0
Bit 14
R/W
RPDRRQW[14]
0
Bit 13
R/W
RPDRRQW[13]
0
Bit 12
R/W
RPDRRQW[12]
0
Bit 11
R/W
RPDRRQW[11]
0
Bit 10
R/W
RPDRRQW[10]
0
Bit 9
R/W
RPDRRQW[9]
0
Bit 8
R/W
RPDRRQW[8]
0
Bit 7
R/W
RPDRRQW[7]
0
Bit 6
R/W
RPDRRQW[6]
0
Bit 5
R/W
RPDRRQW[5]
0
Bit 4
R/W
RPDRRQW[4]
0
Bit 3
R/W
RPDRRQW[3]
0
Bit 2
R/W
RPDRRQW[2]
0
Bit 1
R/W
RPDRRQW[1]
0
Bit 0
R/W
RPDRRQW[0]
0
This register provides the Packet Descriptor Reference Ready Queue write
address.
Notes
1. This register is not byte addressable. Writing to this register modifies all the
bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are
not implemented. However, when all four byte enables are negated, no
access is made to this register.
2. If consecutive write accesses to this register are performed, they must be
spaced at least 4 SYSCLK periods apart.
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RPDRRQW[15:0]:
The receive packet descriptor reference (RPDR) ready queue write bits
(RPDRRQW[15:0]) define bits 17 to 2 of the Receive Packet Descriptor
Reference Ready Queue write pointer. This register is initialised by the host.
The physical write address in the RPDRR queue is the sum of
RPDRRQW[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC
Receive Queue Base register.
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Register 0x2C0 : RMAC Packet Descriptor Reference Ready Queue Read
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
RPDRRQR[15]
0
Bit 14
R/W
RPDRRQR[14]
0
Bit 13
R/W
RPDRRQR[13]
0
Bit 12
R/W
RPDRRQR[12]
0
Bit 11
R/W
RPDRRQR[11]
0
Bit 10
R/W
RPDRRQR[10]
0
Bit 9
R/W
RPDRRQR[9]
0
Bit 8
R/W
RPDRRQR[8]
0
Bit 7
R/W
RPDRRQR[7]
0
Bit 6
R/W
RPDRRQR[6]
0
Bit 5
R/W
RPDRRQR[5]
0
Bit 4
R/W
RPDRRQR[4]
0
Bit 3
R/W
RPDRRQR[3]
0
Bit 2
R/W
RPDRRQR[2]
0
Bit 1
R/W
RPDRRQR[1]
0
Bit 0
R/W
RPDRRQR[0]
0
This register provides the Packet Descriptor Reference Ready Queue read
address.
Notes
1. This register is not byte addressable. Writing to this register modifies all the
bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are
not implemented. However, when all four byte enables are negated, no
access is made to this register.
2. If consecutive write accesses to this register are performed, they must be
spaced at least 4 SYSCLK periods apart.
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RPDRRQR[15:0]:
The receive packet descriptor reference (RPDR) ready queue read bits
(RPDRRQR[15:0]) define bits 17 to 2 of the Receive Packet Descriptor
Reference Ready Queue read pointer. This register is initialised by the host.
The physical read address in the RPDRR queue is the sum of
RPDRRQR[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC
Receive Queue Base register.
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Register 0x2C4 : RMAC Packet Descriptor Reference Ready Queue End
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
RPDRRQE[15]
0
Bit 14
R/W
RPDRRQE[14]
0
Bit 13
R/W
RPDRRQE[13]
0
Bit 12
R/W
RPDRRQE[12]
0
Bit 11
R/W
RPDRRQE[11]
0
Bit 10
R/W
RPDRRQE[10]
0
Bit 9
R/W
RPDRRQE[9]
0
Bit 8
R/W
RPDRRQE[8]
0
Bit 7
R/W
RPDRRQE[7]
0
Bit 6
R/W
RPDRRQE[6]
0
Bit 5
R/W
RPDRRQE[5]
0
Bit 4
R/W
RPDRRQE[4]
0
Bit 3
R/W
RPDRRQE[3]
0
Bit 2
R/W
RPDRRQE[2]
0
Bit 1
R/W
RPDRRQE[1]
0
Bit 0
R/W
RPDRRQE[0]
0
This register provides the Packet Descriptor Reference Ready Queue end
address.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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RPDRRQE[15:0]:
The receive packet descriptor reference (RPDR) ready queue end bits
(RPDRRQE[15:0]) define bits 17 to 2 of the Receive Packet Descriptor
Reference Ready Queue end address. This register is initialised by the host.
The physical end address in the RPDRR queue is the sum of
RPDRRQE[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC
Receive Queue Base register.
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Register 0x300 : TMAC Control
Bit
Type
Bit 31
to
Bit 8
Function
Default
Unused
XXXXXXH
Bit 7
R/W
FQFLUSH
0
Bit 6
R/W
TDQ_FRN[1]
0
Bit 5
R/W
TDQ_FRN[0]
0
Bit 4
R/W
TDQ_RDYN[2]
0
Bit 3
R/W
TDQ_RDYN[1]
0
Bit 2
R/W
TDQ_RDYN[0]
0
Bit 1
R/W
CACHE
1
Bit 0
R/W
ENABLE
0
This register provides control of the TMAC256 block.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
ENABLE:
The transmit DMA controller enable bit (ENABLE) enables the TMAC256 to
accept TDRs from the TDR Ready Queue and reads packet data from host
memory. When ENABLE is set high, the TMAC256 is enabled. When
ENABLE is set low, the TDR Ready Queue is ignored. Once all linked lists of
TDs built up by the TMAC256 have been exhausted, no more data will be
transmitted on the TD[31:0] links.
CACHE:
The transmit descriptor reference cache enable bit (CACHE) controls the
frequency at which TDRs are written to the TDR Free Queue. When CACHE
is set high, freed TDRs are cached and then written up to six at a time.
When CACHE is set low, freed TDRs are written one at a time.
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TDQ_RDYN[2:0]:
The TDQ_RDYN[2:0] field sets the number of transmit descriptor references
(TDRs) that must be read from the TDR Ready Queue before the TDR Ready
interrupt (TDQRDYI) is asserted, as follows:
Table 22 – TDQ_RDYN[2:0] Settings
TDQ_RDYN[2:0]
No of TDRs
000
1
001
4
010
6
011
8
100
16
101
32
110
Reserved
111
Reserved
TDQ_FRN[1:0]:
The TDQ_FRN[1:0] field sets the number of times that a block of TDRs are
written to the TDR Free Queue from the TMAC256s internal cache before the
TDR Free Queue Interrupt (TDQFI) is asserted, as follows:
Table 23 – TDQ_FRN[1:0] Settings
TDQ_FRN[1:0]
No of Reads
00
1
01
4
10
8
11
Reserved
FQFLUSH:
The Free Queue Flush bit (FQFLUSH) may be used to initiate a dump of the
free queue cache retained locally within the TMAC256 to the free queue
located in PCI host memory. When the FQFLUSH bit is set high, the
TMAC256 dumps the contents of the free queue cache to the free queue in
PCI host memory. The FQFLUSH bit is self clearing and will reset to zero
when the flush is complete. Setting the FQFLUSH bit to zero has no affect.
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Register 0x304 : TMAC Indirect Channel Provisioning
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R
BUSY
X
Bit 14
R/W
RWB
0
Bit 13
R/W
PROV
0
Unused
XH
Bit 12
to
Bit 10
Bit 9
R/W
Reserved
0
Bit 8
R/W
Reserved
0
Bit 7
R/W
CHAN[7]
0
Bit 6
R/W
CHAN[6]
0
Bit 5
R/W
CHAN[5]
0
Bit 4
R/W
CHAN[4]
0
Bit 3
R/W
CHAN[3]
0
Bit 2
R/W
CHAN[2]
0
Bit 1
R/W
CHAN[1]
0
Bit 0
R/W
CHAN[0]
0
The Channel Provisioning Register is used to provision and unprovision
channels, and also to query the provision status of channels. When a channel is
provisioned, chains of packet data for that channel will be accepted by the
TMAC256 and placed on the channel’s linked list of packets to be transmitted.
When a channel is unprovisioned, chains of packet data for that channel will be
rejected by the TMAC256 and returned to the TDR Free Queue with the status
bits in the queue element set to indicate the rejection.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
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implemented. However, when all four byte enables are negated, no access is
made to this register.
CHAN[7:0]:
The indirect data bits (CHAN[7:0]) report the channel number read from the
TMAC256 internal memory after an indirect read operation has completed.
Channel number to be written to the TMAC256 internal memory in an indirect
write operation must be set up in this register before triggering the write.
CHAN[7:0] reflects the value written until the completion of a subsequent
indirect read operation.
PROV:
The indirect provision enable bit (PROV) reports the channel provision enable
flag read from the TMAC256 internal memory after an indirect read operation
has completed. The provision enable flag to be written to the TMAC256
internal memory, in an indirect write operation, must be set up in this register
before triggering the write. When PROV is set high, the channel as indicated
by CHAN[7:0] is provisioned. When PROV is set low, the channel indicated
by CHAN[7:0] is unprovisioned. PROV reflects the value written until the
completion of a subsequent indirect read operation.
RWB:
The Read/Write Bar (RWB) bit selects between a provisioning/unprovisioning
operation (write) or a query operation (read). Writing a logic 0 to RWB
triggers the provisioning or unprovisioning of a channel as specified by
CHAN[7:0] and PROV. Writing a logic 1 to RWB triggers a query of the
channel specified by CHAN[7:0].
BUSY:
The indirect access status bit (BUSY) reports the progress of an indirect
access. BUSY is set high when this register is written to trigger an indirect
access, and will stay high until the access is complete. At which point, BUSY
will be set low. This register should be polled to determine when data from an
indirect read operation is available or to determine when a new indirect write
operation may commence.
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Register 0x308 : TMAC Descriptor Table Base LSW
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
TDTB[15]
0
Bit 14
R/W
TDTB[14]
0
Bit 13
R/W
TDTB[13]
0
Bit 12
R/W
TDTB[12]
0
Bit 11
R/W
TDTB[11]
0
Bit 10
R/W
TDTB[10]
0
Bit 9
R/W
TDTB[9]
0
Bit 8
R/W
TDTB[8]
0
Bit 7
R/W
TDTB[7]
0
Bit 6
R/W
TDTB[6]
0
Bit 5
R/W
TDTB[5]
0
Bit 4
R/W
TDTB[4]
0
Bit 3
R/W
TDTB[3]
0
Bit 2
R/W
TDTB[2]
0
Bit 1
R/W
TDTB[1]
0
Bit 0
R/W
TDTB[0]
0
This register provides the less significant word of the Transmit Descriptor Table
Base address. The contents of this register is held in a holding register until a
write access to the companion TMAC Transmit Descriptor Table Base MSW
register.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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Register 0x30C : TMAC Descriptor Table Base MSW
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
TDTB[31]
0
Bit 14
R/W
TDTB[30]
0
Bit 13
R/W
TDTB[29]
0
Bit 12
R/W
TDTB[28]
0
Bit 11
R/W
TDTB[27]
0
Bit 10
R/W
TDTB[26]
0
Bit 9
R/W
TDTB[25]
0
Bit 8
R/W
TDTB[24]
0
Bit 7
R/W
TDTB[23]
0
Bit 6
R/W
TDTB[22]
0
Bit 5
R/W
TDTB[21]
0
Bit 4
R/W
TDTB[20]
0
Bit 3
R/W
TDTB[19]
0
Bit 2
R/W
TDTB[18]
0
Bit 1
R/W
TDTB[17]
0
Bit 0
R/W
TDTB[16]
0
This register provides the more significant word of the Transmit Descriptor Table
Base address. The contents of the companion TMAC Transmit Descriptor Table
Base LSW register is held in a holding register until a write access to this
register, at which point, the base address of the transmit descriptor table is
updated.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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TDTB[31:0]:
The transmit descriptor table base bits (TDTB[31:0]) provides the base
address of the Transmit Descriptor Table in PCI host memory. This register is
initialised by the host. To calculate the physical address of a TD, the 15 bit TD
offset must be added to bits 31 to 4 of the Transmit Descriptor Table Base
(TDTB[31:4]).
The table must be on a 16 byte boundary and thus the least significant four
bits must be written to logic zero.
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Register 0x310 : TMAC Queue Base LSW
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
TQB[15]
0
Bit 14
R/W
TQB[14]
0
Bit 13
R/W
TQB[13]
0
Bit 12
R/W
TQB[12]
0
Bit 11
R/W
TQB[11]
0
Bit 10
R/W
TQB[10]
0
Bit 9
R/W
TQB[9]
0
Bit 8
R/W
TQB[8]
0
Bit 7
R/W
TQB[7]
0
Bit 6
R/W
TQB[6]
0
Bit 5
R/W
TQB[5]
0
Bit 4
R/W
TQB[4]
0
Bit 3
R/W
TQB[3]
0
Bit 2
R/W
TQB[2]
0
Bit 1
R/W
TQB[1]
0
Bit 0
R/W
TQB[0]
0
This register provides the less significant word of the Transmit Queue Base
address. The contents of this register is held in a holding register until a write
access to the companion TMAC Transmit Queue Base MSW register.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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Register 0x314 : TMAC Queue Base MSW
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
TQB[31]
0
Bit 14
R/W
TQB[30]
0
Bit 13
R/W
TQB[29]
0
Bit 12
R/W
TQB[28]
0
Bit 11
R/W
TQB[27]
0
Bit 10
R/W
TQB[26]
0
Bit 9
R/W
TQB[25]
0
Bit 8
R/W
TQB[24]
0
Bit 7
R/W
TQB[23]
0
Bit 6
R/W
TQB[22]
0
Bit 5
R/W
TQB[21]
0
Bit 4
R/W
TQB[20]
0
Bit 3
R/W
TQB[19]
0
Bit 2
R/W
TQB[18]
0
Bit 1
R/W
TQB[17]
0
Bit 0
R/W
TQB[16]
0
This register provides the more significant word of the Transmit Queue Base
address. The contents of the companion TMAC Transmit Descriptor Table Base
LSW register is held in a holding register until a write access to this register, at
which point, the base address of the transmit queue is updated.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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TQB[31:0]:
The transmit queue base bits (TQB[31:0]) provides the base address of the
Transmit Descriptor Reference Free and Transmit Descriptor Reference
Ready queue in PCI host memory. This register is initialised by the host. To
calculate the physical address of a particular transmit queue element, the
TQB bits are added with the appropriate queue start, end, read or write index
registers to form the physical address.
The base address must be dword aligned and thus the least significant two
bits must be written to logic zero.
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Register 0x318 : TMAC Descriptor Reference Free Queue Start
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
TDRFQS[15]
0
Bit 14
R/W
TDRFQS[14]
0
Bit 13
R/W
TDRFQS[13]
0
Bit 12
R/W
TDRFQS[12]
0
Bit 11
R/W
TDRFQS[11]
0
Bit 10
R/W
TDRFQS[10]
0
Bit 9
R/W
TDRFQS[9]
0
Bit 8
R/W
TDRFQS[8]
0
Bit 7
R/W
TDRFQS[7]
0
Bit 6
R/W
TDRFQS[6]
0
Bit 5
R/W
TDRFQS[5]
0
Bit 4
R/W
TDRFQS[4]
0
Bit 3
R/W
TDRFQS[3]
0
Bit 2
R/W
TDRFQS[2]
0
Bit 1
R/W
TDRFQS[1]
0
Bit 0
R/W
TDRFQS[0]
0
This register provides the Transmit Descriptor Reference Free Queue start
address.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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TDRFQS[15:0]:
The transmit packet descriptor reference (TDR) free queue start bits
(TDRFQS[15:0]) define bits 17 to 2 of the Transmit Packet Descriptor
Reference Free Queue start address. This register is initialised by the host.
The physical start address of the TDRF queue is the sum of TDRFQS[15:0]
left shifted by 2 bits with the TQB[31:0] bits in the TMAC Transmit Queue
Base register.
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Register 0x31C TMAC Descriptor Reference Free Queue Write
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
TDRFQW[15]
0
Bit 14
R/W
TDRFQW[14]
0
Bit 13
R/W
TDRFQW[13]
0
Bit 12
R/W
TDRFQW[12]
0
Bit 11
R/W
TDRFQW[11]
0
Bit 10
R/W
TDRFQW[10]
0
Bit 9
R/W
TDRFQW[9]
0
Bit 8
R/W
TDRFQW[8]
0
Bit 7
R/W
TDRFQW[7]
0
Bit 6
R/W
TDRFQW[6]
0
Bit 5
R/W
TDRFQW[5]
0
Bit 4
R/W
TDRFQW[4]
0
Bit 3
R/W
TDRFQW[3]
0
Bit 2
R/W
TDRFQW[2]
0
Bit 1
R/W
TDRFQW[1]
0
Bit 0
R/W
TDRFQW[0]
0
This register provides the Transmit Descriptor Reference Free Queue write
address.
Notes
1. This register is not byte addressable. Writing to this register modifies all the
bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are
not implemented. However, when all four byte enables are negated, no
access is made to this register.
2. If consecutive write accesses to this register are performed, they must be
spaced at least 4 SYSCLK periods apart.
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TDRFQW[15:0]:
The transmit packet descriptor reference (TPDR) free queue write bits
(TDRFQW[15:0]) define bits 17 to 2 of the Transmit Packet Descriptor
Reference Free Queue write pointer. This register is initialised by the host.
The physical write address in the TDRF queue is the sum of TDRFQW[15:0]
left shifted by 2 bits with the TQB[31:0] bits in the TMAC Transmit Queue
Base register.
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Register 0x320 : TMAC Descriptor Reference Free Queue Read
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
TDRFQR[15]
0
Bit 14
R/W
TDRFQR[14]
0
Bit 13
R/W
TDRFQR[13]
0
Bit 12
R/W
TDRFQR[12]
0
Bit 11
R/W
TDRFQR[11]
0
Bit 10
R/W
TDRFQR[10]
0
Bit 9
R/W
TDRFQR[9]
0
Bit 8
R/W
TDRFQR[8]
0
Bit 7
R/W
TDRFQR[7]
0
Bit 6
R/W
TDRFQR[6]
0
Bit 5
R/W
TDRFQR[5]
0
Bit 4
R/W
TDRFQR[4]
0
Bit 3
R/W
TDRFQR[3]
0
Bit 2
R/W
TDRFQR[2]
0
Bit 1
R/W
TDRFQR[1]
0
Bit 0
R/W
TDRFQR[0]
0
This register provides the Transmit Descriptor Reference Free Queue read
address.
Notes
1. This register is not byte addressable. Writing to this register modifies all the
bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are
not implemented. However, when all four byte enables are negated, no
access is made to this register.
2. If consecutive write accesses to this register are performed, they must be
spaced at least 4 SYSCLK periods apart.
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TDRFQR[15:0]:
The transmit packet descriptor reference (TPDR) free queue read bits
(TDRFQR[15:0]) define bits 17 to 2 of the Transmit Packet Descriptor
Reference Free Queue read pointer. This register is initialised by the host.
The physical read address in the TDRF queue is the sum of TDRFQR[15:0]
left shifted by 2 bits with the TQB[31:0] bits in the TMAC Transmit Queue
Base register.
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Register 0x324 : TMAC Descriptor Reference Free Queue End
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
TDRFQE[15]
0
Bit 14
R/W
TDRFQE[14]
0
Bit 13
R/W
TDRFQE[13]
0
Bit 12
R/W
TDRFQE[12]
0
Bit 11
R/W
TDRFQE[11]
0
Bit 10
R/W
TDRFQE[10]
0
Bit 9
R/W
TDRFQE[9]
0
Bit 8
R/W
TDRFQE[8]
0
Bit 7
R/W
TDRFQE[7]
0
Bit 6
R/W
TDRFQE[6]
0
Bit 5
R/W
TDRFQE[5]
0
Bit 4
R/W
TDRFQE[4]
0
Bit 3
R/W
TDRFQE[3]
0
Bit 2
R/W
TDRFQE[2]
0
Bit 1
R/W
TDRFQE[1]
0
Bit 0
R/W
TDRFQE[0]
0
This register provides the Transmit Descriptor Reference Free Queue end
address.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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TDRFQE[15:0]:
The transmit packet descriptor reference (TDR) free queue end bits
(TDRFQE[15:0]) define bits 17 to 2 of the Transmit Packet Descriptor
Reference Free Queue end address. This register is initialised by the host.
The physical end address of the TDRF queue is the sum of TDRFQE[15:0]
left shifted by 2 bits with the TQB[31:0] bits in the TMAC Transmit Queue
Base register.
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Register 0x328 :TMAC Descriptor Reference Ready Queue Start
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
TDRRQS[15]
0
Bit 14
R/W
TDRRQS[14]
0
Bit 13
R/W
TDRRQS[13]
0
Bit 12
R/W
TDRRQS[12]
0
Bit 11
R/W
TDRRQS[11]
0
Bit 10
R/W
TDRRQS[10]
0
Bit 9
R/W
TDRRQS[9]
0
Bit 8
R/W
TDRRQS[8]
0
Bit 7
R/W
TDRRQS[7]
0
Bit 6
R/W
TDRRQS[6]
0
Bit 5
R/W
TDRRQS[5]
0
Bit 4
R/W
TDRRQS[4]
0
Bit 3
R/W
TDRRQS[3]
0
Bit 2
R/W
TDRRQS[2]
0
Bit 1
R/W
TDRRQS[1]
0
Bit 0
R/W
TDRRQS[0]
0
This register provides the Transmit Descriptor Reference Ready Queue start
address.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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TDRRQS[15:0]:
The transmit packet descriptor reference (TDR) ready queue start bits
(TDRRQS[15:0]) define bits 17 to 2 of the Transmit Packet Descriptor
Reference Ready Queue start address. This register is initialised by the host.
The physical start address of the TDRF queue is the sum of TDRRQS[15:0]
left shifted by 2 bits with the TQB[31:0] bits in the TMAC Transmit Queue
Base register.
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Register 0x32C : TMAC Descriptor Reference Ready Queue Write
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
TDRRQW[15]
0
Bit 14
R/W
TDRRQW[14]
0
Bit 13
R/W
TDRRQW[13]
0
Bit 12
R/W
TDRRQW[12]
0
Bit 11
R/W
TDRRQW[11]
0
Bit 10
R/W
TDRRQW[10]
0
Bit 9
R/W
TDRRQW[9]
0
Bit 8
R/W
TDRRQW[8]
0
Bit 7
R/W
TDRRQW[7]
0
Bit 6
R/W
TDRRQW[6]
0
Bit 5
R/W
TDRRQW[5]
0
Bit 4
R/W
TDRRQW[4]
0
Bit 3
R/W
TDRRQW[3]
0
Bit 2
R/W
TDRRQW[2]
0
Bit 1
R/W
TDRRQW[1]
0
Bit 0
R/W
TDRRQW[0]
0
This register provides the Transmit Descriptor Reference Ready Queue write
address.
Notes
1. This register is not byte addressable. Writing to this register modifies all the
bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are
not implemented. However, when all four byte enables are negated, no
access is made to this register.
2. If consecutive write accesses to this register are performed, they must be
spaced at least 4 SYSCLK periods apart.
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TDRRQW[15:0]:
The transmit packet descriptor reference (TPDR) ready queue write bits
(TDRRQW[15:0]) define bits 17 to 2 of the Transmit Packet Descriptor
Reference Ready Queue write pointer. This register is initialised by the host.
The physical write address in the TDRF queue is the sum of TDRRQW[15:0]
left shifted by 2 bits with the TQB[31:0] bits in the TMAC Transmit Queue
Base register.
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Register 0x330 : TMAC Descriptor Reference Ready Queue Read
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
TDRRQR[15]
0
Bit 14
R/W
TDRRQR[14]
0
Bit 13
R/W
TDRRQR[13]
0
Bit 12
R/W
TDRRQR[12]
0
Bit 11
R/W
TDRRQR[11]
0
Bit 10
R/W
TDRRQR[10]
0
Bit 9
R/W
TDRRQR[9]
0
Bit 8
R/W
TDRRQR[8]
0
Bit 7
R/W
TDRRQR[7]
0
Bit 6
R/W
TDRRQR[6]
0
Bit 5
R/W
TDRRQR[5]
0
Bit 4
R/W
TDRRQR[4]
0
Bit 3
R/W
TDRRQR[3]
0
Bit 2
R/W
TDRRQR[2]
0
Bit 1
R/W
TDRRQR[1]
0
Bit 0
R/W
TDRRQR[0]
0
This register provides the Transmit Descriptor Reference Ready Queue read
address.
Notes
1. This register is not byte addressable. Writing to this register modifies all the
bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are
not implemented. However, when all four byte enables are negated, no
access is made to this register.
2. If consecutive write accesses to this register are performed, they must be
spaced at least 4 SYSCLK periods apart.
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TDRRQR[15:0]:
The transmit packet descriptor reference (TPDR) ready queue read bits
(TDRRQR[15:0]) define bits 17 to 2 of the Transmit Packet Descriptor
Reference Ready Queue read pointer. This register is initialised by the host.
The physical read address in the TDRF queue is the sum of TDRRQR[15:0]
left shifted by 2 bits with the TQB[31:0] bits in the TMAC Transmit Queue
Base register.
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Register 0x334 : TMAC Descriptor Reference Ready Queue End
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
TDRRQE[15]
0
Bit 14
R/W
TDRRQE[14]
0
Bit 13
R/W
TDRRQE[13]
0
Bit 12
R/W
TDRRQE[12]
0
Bit 11
R/W
TDRRQE[11]
0
Bit 10
R/W
TDRRQE[10]
0
Bit 9
R/W
TDRRQE[9]
0
Bit 8
R/W
TDRRQE[8]
0
Bit 7
R/W
TDRRQE[7]
0
Bit 6
R/W
TDRRQE[6]
0
Bit 5
R/W
TDRRQE[5]
0
Bit 4
R/W
TDRRQE[4]
0
Bit 3
R/W
TDRRQE[3]
0
Bit 2
R/W
TDRRQE[2]
0
Bit 1
R/W
TDRRQE[1]
0
Bit 0
R/W
TDRRQE[0]
0
This register provides the Transmit Descriptor Reference Ready Queue end
address.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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TDRRQE[15:0]:
The transmit packet descriptor reference (TDR) ready queue end bits
(TDRRQE[15:0]) define bits 17 to 2 of the Transmit Packet Descriptor
Reference Ready Queue end address. This register is initialised by the host.
The physical end address of the TDRF queue is the sum of TDRRQE[15:0]
left shifted by 2 bits with the TQB[31:0] bits in the TMAC Transmit Queue
Base register.
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Register 0x380 : THDL Indirect Channel Select
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R
BUSY
X
Bit 14
R/W
CRWB
0
Unused
XH
Bit 13
to
Bit 10
Bit 9
R/W
Reserved
0
Bit 8
R/W
Reserved
0
Bit 7
R/W
CHAN[7]
0
Bit 6
R/W
CHAN[6]
0
Bit 5
R/W
CHAN[5]
0
Bit 4
R/W
CHAN[4]
0
Bit 3
R/W
CHAN[3]
0
Bit 2
R/W
CHAN[2]
0
Bit 1
R/W
CHAN[1]
0
Bit 0
R/W
CHAN[0]
0
This register provides the channel number used to access the transmit channel
provision RAM. Writing to this register triggers an indirect channel register
access.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
CHAN[7:0]:
The indirect channel number bits (CHAN[7:0]) indicate the channel to be
configured or interrogated in the indirect access.
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CRWB:
The channel indirect access control bit (CRWB) selects between a configure
(write) or interrogate (read) access to the channel provision RAM. Writing a
logic zero to CRWB triggers an indirect write operation. Data to be written is
taken from the Indirect Channel Data registers. Writing a logic one to CRWB
triggers an indirect read operation. The data read can be found in the Indirect
Channel Data registers.
BUSY:
The indirect access status bit (BUSY) reports the progress of an indirect
access. BUSY is set high when this register is written to trigger an indirect
access, and will stay high until the access is complete. At which point, BUSY
will be set low. This register should be polled to determine when data from an
indirect read operation is available in the THDL Indirect Channel Data #1, #2
and #3 registers or to determine when a new indirect write operation may
commence.
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Register 0x384 : THDL Indirect Channel Data #1
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
PROV
0
Bit 14
R/W
CRC[1]
0
Bit 13
R/W
CRC[0]
0
Bit 12
R/W
DELIN
0
Bit 11
W
Reserved
X
Bit 10
W
FPTR[10]
0
Bit 9
W
FPTR[9]
0
Bit 8
W
FPTR[8]
0
Bit 7
W
FPTR[7]
0
Bit 6
W
FPTR[6]
0
Bit 5
W
FPTR[5]
0
Bit 4
W
FPTR[4]
0
Bit 3
W
FPTR[3]
0
Bit 2
W
FPTR[2]
0
Bit 1
W
FPTR[1]
0
Bit 0
W
FPTR[0]
0
This register contains data read from the channel provision RAM after an indirect
channel read operation or data to be inserted into the channel provision RAM in
an indirect channel write operation.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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FPTR[10:0]:
The indirect FIFO block pointer (FPTR[10:0]) informs the partial packet buffer
processor the circular linked list of blocks to use for a FIFO for the channel.
The FIFO pointer to be written to the channel provision RAM, in an indirect
write operation, must be set up in this register before triggering the write. The
FIFO pointer value can be any one of the block numbers provisioned, by
indirect block write operations, to form the circular buffer.
Reserved:
The reserved bit must be set low for correct operation of the FREEDM32P256 device.
DELIN:
The indirect delineate enable bit (DELIN) configures the HDLC processor to
perform flag sequence insertion and bit stuffing on the outgoing data stream.
The delineate enable bit to be written to the channel provision RAM, in an
indirect channel write operation, must be set up in this register before
triggering the write. When DELIN is set high, flag sequence insertion, bit
stuffing and ,optionally, CRC generation is performed on the outgoing HDLC
data stream. When DELIN is set low, the HDLC processor does not perform
any processing (flag sequence insertion, bit stuffing nor CRC generation) on
the outgoing stream. DELIN reflects the value written until the completion of
a subsequent indirect channel read operation.
CRC[1:0]:
The CRC algorithm (CRC[1:0]) configures the HDLC processor to perform
CRC generation on the outgoing HDLC data stream. The value of CRC[1:0]
to be written to the channel provision RAM, in an indirect channel write
operation, must be set up in this register before triggering the write. CRC[1:0]
is ignored when DELIN is low. CRC[1:0] reflects the value written until the
completion of a subsequent indirect channel read operation.
Table 24 – CRC[1:0] Settings
CRC[1]
CRC[0]
Operation
0
0
No CRC
0
1
CRC-CCITT
1
0
CRC-32
1
1
Reserved
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PROV:
The indirect provision enable bit (PROV) reports the channel provision enable
flag read from the channel provision RAM after an indirect channel read
operation has completed. The provision enable flag to be written to the
channel provision RAM, in an indirect write operation, must be set up in this
register before triggering the write. When PROV is set high, the HDLC
processor will service requests for data from the TCAS256 block. When
PROV is set low, the HDLC processor will ignore requests from the TCAS256
block. PROV reflects the value written until the completion of a subsequent
indirect channel read operation.
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Register 0x388 : THDL Indirect Channel Data #2
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
7BIT
0
Bit 14
R/W
PRIORITYB
0
Bit 13
R/W
INVERT
0
Bit 12
R/W
DFCS
0
Bit 11
W
Reserved
0
Bit 10
W
FLEN[10]
0
Bit 9
W
FLEN[9]
0
Bit 8
W
FLEN[8]
0
Bit 7
W
FLEN[7]
0
Bit 6
W
FLEN[6]
0
Bit 5
W
FLEN[5]
0
Bit 4
W
FLEN[4]
0
Bit 3
W
FLEN[3]
0
Bit 2
W
FLEN[2]
0
Bit 1
W
FLEN[1]
0
Bit 0
W
FLEN[0]
0
This register contains data to be inserted into the channel provision RAM in an
indirect write operation.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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FLEN[10:0]:
The indirect FIFO length (FLEN[10:0]) is the number of blocks, less one, that
is provisioned to the circular channel FIFO specified by the FPTR[10:0] block
pointer. The FIFO length to be written to the channel provision RAM, in an
indirect channel write operation, must be set up in this register before
triggering the write.
Reserved:
The reserved bit must be set low for correct operation of the FREEDM32P256 device.
DFCS:
The diagnose frame check sequence bit (DFCS) controls the inversion of the
FCS field inserted into the transmit packet. The value of DFCS to be written
to the channel provision RAM, in an indirect channel write operation, must be
set up in this register before triggering the write. When DFCS is set to one,
the FCS field in the outgoing HDLC stream is logically inverted allowing
diagnosis of downstream FCS verification logic. The outgoing FCS field is
not inverted when DFCS is set to zero. DFCS reflects the value written until
the completion of a subsequent indirect channel read operation.
INVERT:
The HDLC data inversion bit (INVERT) configures the HDLC processor to
logically invert the outgoing HDLC stream. The value of INVERT to be written
to the channel provision RAM, in an indirect channel write operation, must be
set up in this register before triggering the write. When INVERT is set to one,
the outgoing HDLC stream is logically inverted. The outgoing HDLC stream
is not inverted when INVERT is set to zero. INVERT reflects the value written
until the completion of a subsequent indirect channel read operation.
PRIORITYB:
The active low channel FIFO starving enable bit (PRIORITYB) informs the
partial packet processor of the priority of the channel relative to other
channels when requesting data from the DMA port. The value of PRIORITYB
to be written to the channel provision RAM, in an indirect channel write
operation, must be set up in this register before triggering the write. Channel
FIFOs with PRIORITYB set to one are inhibited from making expedited
requests for data to the TMAC256. When PRIORITYB is set to zero, both
normal and expedited requests can be made to the TMAC256. Channels
with HDLC data rate to FIFO size ratio that is significantly lower than other
channels should have PRIORITYB set to one. PRIORITYB reflects the value
written until the completion of a subsequent indirect channel read operation.
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7BIT:
The least significant stuff enable bit (7BIT) configures the HDLC processor to
stuff the least significant bit of each octet in the corresponding transmit link
(TD[n]). The value of 7BIT to be written to the channel provision RAM, in an
indirect channel write operation, must be set up in this register before
triggering the write. When 7BIT is set high, the least significant bit (last bit of
each octet transmitted) does not contain channel data and is forced to the
value configured by the BIT8 register bit. When 7BIT is set low, the entire
octet contains valid data and BIT8 is ignored. 7BIT reflects the value written
until the completion of a subsequent indirect channel read operation.
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Register 0x38C : THDL Indirect Channel Data #3
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R/W
TRANS
0
Bit 14
R/W
IDLE
0
Bit 13
Unused
X
Bit 12
Unused
X
Bit 11
R/W
LEVEL[3]
0
Bit 10
R/W
LEVEL[2]
0
Bit 9
R/W
LEVEL[1]
0
Bit 8
R/W
LEVEL[0]
0
Bit 7
R/W
FLAG[2]
0
Bit 6
R/W
FLAG[1]
0
Bit 5
R/W
FLAG[0]
0
Unused
X
Bit 4
Bit 3
R/W
XFER[3]
0
Bit 2
R/W
XFER[2]
0
Bit 1
R/W
XFER[1]
0
Bit 0
R/W
XFER[0]
0
This register contains data read from the channel provision RAM after an indirect
read operation or data to be inserted into the channel provision RAM in an
indirect write operation.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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XFER[3:0]:
The indirect channel transfer size (XFER[3:0]) specifies the amount of data
the partial packet processor requests from the TMAC256 block. The channel
transfer size to be written to the channel provision RAM, in an indirect write
operation, must be set up in this register before triggering the write. When
the channel FIFO free space reaches or exceeds the limit specified by
XFER[3:0], the partial packet processor will make a request for data to the
TMAC256 to retrieve the XFER[3:0] + 1 blocks of data. FIFO free space and
transfer size are measured in the number of 16-byte blocks. XFER[3:0]
reflects the value written until the completion of a subsequent indirect channel
read operation.
To prevent lockup, the channel transfer size (XFER[3:0]) can be configured to
be less than or equal to the start transmission level set by LEVEL[3:0] and
TRANS. Alternatively, the channel transfer size can be set, such that, the
total number of blocks in the logical channel FIFO minus the start
transmission level is an integer multiple of the channel transfer size.
The case of a single block transfer size is a special. When BURSTEN is set
high and XFER[3:0] = 'b0000, the transfer size is variable. The THDL256 will
request the TMAC256 to transfer as much data as there is free space in the
FIFO, up to a maximum set by BURST[3:0].
FLAG[2:0]:
The flag insertion control (FLAG[2:0]) configures the minimum number of
flags or bytes of idle bits the HDLC processor inserts between HDLC packets.
The value of FLAG[2:0] to be written to the channel provision RAM, in an
indirect channel write operation, must be set up in this register before
triggering the write. The minimum number of flags or bytes of idle (8 bits of
1's) inserted between HDLC packets is shown in the table below. FLAG[2:0]
reflects the value written until the completion of a subsequent indirect channel
read operation.
Table 25 – FLAG[2:0] Settings
FLAG[2:0]
Minimum Number of Flag/Idle Bytes
000
1 flag / 0 Idle byte
001
2 flags / 0 idle byte
010
4 flags / 2 idle bytes
011
8 flags / 6 idle bytes
100
16 flags / 14 idle bytes
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FLAG[2:0]
Minimum Number of Flag/Idle Bytes
101
32 flags / 30 idle bytes
110
64 flags / 62 idle bytes
111
128 flags / 126 idle bytes
LEVEL[3:0]:
The indirect channel FIFO trigger level (LEVEL[3:0]), in concert with the
TRANS bit, configure the various channel FIFO free space levels which
trigger the HDLC processor to start transmission of a HDLC packet as well as
trigger the partial packet buffer to make DMA request for data as shown in the
following table. The channel FIFO trigger level to be written to the channel
provision RAM, in an indirect write operation, must be set up in this register
before triggering the write. LEVEL[3:0] reflects the value written until the
completion of a subsequent indirect channel read operation.
The HDLC processor starts transmitting a packet when the channel FIFO free
space is less than or equal to the level specified in the appropriate Start
Transmission Level column of the following table or when an end of a packet
is stored in the channel FIFO. When the channel FIFO free space is greater
than or equal to the level specified in the Starving Trigger Level column of the
following table and the HDLC processor is transmitting a packet and an end
of a packet is not stored in the channel FIFO, the partial packet buffer makes
expedite requests to the TMAC256 to retrieve XFER[3:0] + 1 blocks of data.
To prevent lockup, the channel transfer size (XFER[3:0]) can be configured to
be less than or equal to the start transmission level set by LEVEL[3:0] and
TRANS. Alternatively, the channel transfer size can be set such that the total
number of blocks in the logical channel FIFO, minus the start transmission
level, is an integer multiple of the channel transfer size. The starving trigger
level must always be set to a number of blocks greater than or equal to the
channel transfer size.
IDLE:
The interframe time fill bit (IDLE) configures the HDLC processor to use flag
bytes or HDLC idle as the interframe time fill between HDLC packets. The
value of IDLE to be written to the channel provision RAM, in an indirect
channel write operation, must be set up in this register before triggering the
write. When IDLE is set low, the HDLC processor uses flag bytes as the
interframe time fill. When IDLE is set high, the HDLC processor uses HDLC
idle (all one's bit with no bit-stuffing pattern is transmitted) as the interframe
time fill. IDLE reflects the value written until the completion of a subsequent
indirect channel read operation.
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TRANS:
The indirect transmission start bit (TRANS), in concert with the LEVEL[3:0]
bits, configure the various channel FIFO free space levels which trigger the
HDLC processor to start transmission of a HDLC packet as well as trigger the
partial packet buffer to make DMA request for data as shown in the following
table. The transmission start mode to be written to the channel provision
RAM, in an indirect write operation, must be set up in this register before
triggering the write. TRANS reflects the value written until the completion of a
subsequent indirect channel read operation.
The HDLC processor starts transmitting a packet when the channel FIFO free
space is less than or equal to the level specified in the appropriate Start
Transmission Level column of the following table or when an end of a packet
is stored in the channel FIFO. When the channel FIFO free space is greater
than or equal to the level specified in the Starving Trigger Level column of the
following table and the HDLC processor is transmitting a packet and an end
of a packet is not stored in the channel FIFO, the partial packet buffer makes
expedite requests to the TMAC256 to retrieve XFER[3:0] + 1 blocks of data.
To prevent lockup, the channel transfer size (XFER[3:0]) can be configured to
be less than or equal to the start transmission level set by LEVEL[3:0] and
TRANS. Alternatively, the channel transfer size can be set, such that, the
total number of blocks in the logical channel FIFO minus the start
transmission level is an integer multiple of the channel transfer size. The
starving trigger level must always be set to a number of blocks greater than or
equal to the channel transfer size.
Table 26 – Level[3:0]/TRANS Settings
LEVEL[3:0]
Starving
Trigger Level
Start
Transmission
Level (TRANS=0)
Start Transmission
Level (TRANS=1)
0000
2 Blocks
(32 bytes free)
1 Block
(16 bytes free)
1 Block
(16 bytes free)
0001
3 Blocks
(48 bytes free)
2 Blocks
(32 bytes free)
1 Block
(16 bytes free)
0010
4 Blocks
(64 bytes free)
3 Blocks
(48 bytes free)
2 Blocks
(32 bytes free)
0011
6 Blocks
(96 bytes free)
4 Blocks
(64 bytes free)
3 Blocks
(48 bytes free)
0100
8 Blocks
(128 bytes free)
6 Blocks
(96 bytes free)
4 Blocks
(64 bytes free)
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LEVEL[3:0]
Starving
Trigger Level
Start
Transmission
Level (TRANS=0)
Start Transmission
Level (TRANS=1)
0101
12 Blocks
(192 bytes free)
8 Blocks
(128 bytes free)
6 Blocks
(96 bytes free)
0110
16 Blocks
(256 bytes free)
12 Blocks
(192 bytes free)
8 Blocks
(128 bytes free)
0111
24 Blocks
(384 bytes free)
16 Blocks
(256 bytes free)
12 Blocks
(192 bytes free)
1000
32 Blocks
(512 bytes free)
24 Blocks
(384 bytes free)
16 Blocks
(256 bytes free)
1001
48 Blocks
(768 bytes free)
32 Blocks
(512 bytes free)
24 Blocks
(384 bytes free)
1010
64 Blocks
(1 Kbytes free)
48 Blocks
(768 bytes free)
32 Blocks
(512 bytes free)
1011
96 Blocks
(1.5 Kbytes free)
64 Blocks
(1 Kbytes free)
48 Blocks
(768 bytes free)
1100
192 Blocks
(3 Kbytes free)
128 Blocks
(2 Kbytes free)
96 Blocks
(1.5 Kbytes free)
1101
384 Blocks
(6 Kbytes free)
256 Blocks
(4 Kbytes free)
192 Blocks
(2 Kbytes free)
1110
768 Blocks
(12 Kbytes free)
512 Blocks
(8 Kbytes free)
384 Blocks
(4 Kbytes free)
1111
1536 Blocks
(24 Kbytes free)
1024 Blocks
(16 Kbytes free)
768 Blocks
(8 Kbytes free)
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Register 0x3A0 : THDL Indirect Block Select
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R
BUSY
X
Bit 14
R/W
BRWB
0
Unused
XH
Bit 13
to
Bit 12
Bit 11
R/W
Reserved
X
Bit 10
R/W
BLOCK[10]
0
Bit 9
R/W
BLOCK[9]
0
Bit 8
R/W
BLOCK[8]
0
Bit 7
R/W
BLOCK[7]
0
Bit 6
R/W
BLOCK[6]
0
Bit 5
R/W
BLOCK[5]
0
Bit 4
R/W
BLOCK[4]
0
Bit 3
R/W
BLOCK[3]
0
Bit 2
R/W
BLOCK[2]
0
Bit 1
R/W
BLOCK[1]
0
Bit 0
R/W
BLOCK[0]
0
This register provides the block number used to access the block pointer RAM.
Writing to this register triggers an indirect block register access.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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BLOCK[10:0]:
The indirect block number (BLOCK[10:0]) indicate the block to be configured
or interrogated in the indirect access.
Reserved:
The reserved bit must be set low for correct operation of the FREEDM32P256 device.
BRWB:
The block indirect access control bit (BRWB) selects between a configure
(write) or interrogate (read) access to the block pointer RAM. Writing a logic
zero to BRWB triggers an indirect block write operation. Data to be written is
taken from the Indirect Block Data register. Writing a logic one to BRWB
triggers an indirect block read operation. The data read can be found in the
Indirect Block Data register.
BUSY:
The indirect access status bit (BUSY) reports the progress of an indirect
access. BUSY is set high when this register is written to trigger an indirect
access, and will stay high until the access is complete. At which point, BUSY
will be set low. This register should be polled to determine when data from an
indirect read operation is available in the THDL Indirect Block Data register or
to determine when a new indirect write operation may commence.
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Register 0x3A4 : THDL Indirect Block Data
Bit
Type
Bit 31
to
Bit 16
Bit 15
R/W
Bit 14
to
Bit 12
Function
Default
Unused
XXXXH
Reserved
0
Unused
XH
Bit 11
R/W
Reserved
X
Bit 10
R/W
BPTR[10]
0
Bit 9
R/W
BPTR[9]
0
Bit 8
R/W
BPTR[8]
0
Bit 7
R/W
BPTR[7]
0
Bit 6
R/W
BPTR[6]
0
Bit 5
R/W
BPTR[5]
0
Bit 4
R/W
BPTR[4]
0
Bit 3
R/W
BPTR[3]
0
Bit 2
R/W
BPTR[2]
0
Bit 1
R/W
BPTR[1]
0
Bit 0
R/W
BPTR[0]
0
This register contains data read from the transmit block pointer RAM after an
indirect block read operation or data to be inserted into the transmit block pointer
RAM in an indirect block write operation.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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BPTR[10:0]:
The indirect block pointer (BPTR[10:0]) configures the block pointer of the
block specified by the Indirect Block Select register. The block pointer to be
written to the transmit block pointer RAM, in an indirect write operation, must
be set up in this register before triggering the write. The block pointer value is
the block number of the next block in the linked list. A circular list of blocks
must be formed in order to use the block list as a channel FIFO buffer.
FPTR[10:0] reflects the value written until the completion of a subsequent
indirect block read operation.
When provisioning a channel FIFO, all blocks pointers must be re-written to
properly initialize the FIFO.
Reserved:
The reserved bits must be set low for correct operation of the FREEDM32P256 device.
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Register 0x3B0 : THDL Configuration
Bit
Type
Bit 31
to
Bit 10
Function
Default
Unused
XXXXXXH
Bit 9
R/W
BIT8
0
Bit 8
R/W
TSTD
0
Bit 7
R/W
BURSTEN
0
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
R/W
BURST[3]
0
Bit 2
R/W
BURST[2]
0
Bit 1
R/W
BURST[1]
0
Bit 0
R/W
BURST[0]
0
This register configures all provisioned channels.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
BURST[3:0]:
The DMA burst length bits (BURST[3:0]) configure the maximum amount of
transmit data that can be requested in a single DMA transaction for channels
whose channel transfer size is set to one block (XFER[3:0] = 'b0000).
BURST[3:0] has no effect when BURSTEN is set low, nor on channels
configured with other transfer sizes. BURST[3:0] defines the maximum
number of 16 byte blocks, less one, that is transferred in each DMA
transaction. Thus, the minimum number of blocks is one (16 bytes) and the
maximum is sixteen (256 bytes).
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BURSTEN:
The burst length enable bit (BURSTEN) controls the use of BURST[3:0] in
determining the amount of data requested in a single DMA transaction for
channels whose channel transfer size is set to one block (XFER[3:0] =
'b0000). BURSTEN has no effect on channels configured with other transfer
sizes. When BURSTEN is set high, the maximum size of DMA transfer is
limited by BURST[3:0]. The transmit HDLC processor may combine several
channel transfer size amounts into a single transaction. When BURSTEN is
set low, the amount of data in a DMA transfer is limited to one block.
TSTD:
The telecom standard bit (TSTD) controls the bit ordering of the HDLC data
transferred from the PCI host. When TSTD is set low, the least significant bit
of the each byte on the PCI bus (AD[0], AD[8], AD[16] and AD[24]) is the first
HDLC bit transmitted and the most significant bit of each byte (AD[7], AD[15],
AD[23] and AD[31]) is the last HDLC bit transmitted (datacom standard).
When TSTD is set high, AD[0], AD[8], AD[16] and AD[24] are the last HDLC
bit transmitted and AD[7], AD[15], AD[23] and AD[31] are the first HDLC bit
transmitted (telecom standard).
BIT8:
The least significant stuff control bit (BIT8) carries the value placed in the
least significant bit of each octet when the HDLC processor is configured
(7BIT set high) to stuff the least significant bit of each octet in the
corresponding transmit link (TD[n]). When BIT8 is set high, the least
significant bit (last bit of each octet transmitted) is forced high. When BIT8 is
set low, the least significant bit is forced low. BIT8 is ignored when 7BIT is set
low.
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Register 0x400 : TCAS Indirect Link and Time-slot Select
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R
BUSY
X
Bit 14
R/W
RWB
0
Unused
X
Bit 13
Bit 12
R/W
Reserved
0
Bit 11
R/W
Reserved
0
Bit 10
R/W
LINK[4]
0
Bit 9
R/W
LINK[3]
0
Bit 8
R/W
LINK[2]
0
Bit 7
R/W
LINK[1]
0
Bit 6
R/W
LINK[0]
0
Unused
X
Bit 5
Bit 4
R/W
TSLOT[4]
0
Bit 3
R/W
TSLOT[3]
0
Bit 2
R/W
TSLOT[2]
0
Bit 1
R/W
TSLOT[1]
0
Bit 0
R/W
TSLOT[0]
0
This register provides the link number and time-slot number used to access the
transmit channel provision RAM. Writing to this register triggers an indirect
register access and transfers the contents of the Indirect Channel Data register
to an internal holding register.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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TSLOT[4:0]:
The indirect time-slot number bits (TSLOT[4:0]) indicate the time-slot to be
configured or interrogated in the indirect access. For a channelised T1/J1
link, time-slots 1 to 24 are valid. For a channelised E1 link, time-slots 1 to 31
are valid. For a H-MVIP link, time-slots 0 to 31 are valid. For unchannelised
links, only time-slot 0 is valid.
LINK[4:0]:
The indirect link number bits (LINK[4:0]) select amongst the 32 transmit links
to be configured or interrogated in the indirect access.
Reserved:
The reserved bits must be set low for correct operation of the FREEDM32P256 device.
RWB:
The indirect access control bit (RWB) selects between a configure (write) or
interrogate (read) access to the transmit channel provision RAM. The
address to the transmit channel provision RAM is constructed by
concatenating the TSLOT[4:0] and LINK[4:0] bits. Writing a logic zero to
RWB triggers an indirect write operation. Data to be written is taken from the
PROV and the CHAN[7:0] bits of the Indirect Data register. Writing a logic
one to RWB triggers an indirect read operation. Addressing of the RAM is the
same as in an indirect write operation. The data read can be found in the
PROV and the CHAN[7:0] bits of the Indirect Channel Data register.
BUSY:
The indirect access status bit (BUSY) reports the progress of an indirect
access. BUSY is set high when this register is written to trigger an indirect
access, and will stay high until the access is complete. At which point, BUSY
will be set low. This register should be polled to determine when data from an
indirect read operation is available in the TCAS Indirect Channel Data register
or to determine when a new indirect write operation may commence.
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Register 0x404 : TCAS Indirect Channel Data
Bit
Type
Bit 31
to
Bit 16
Bit 15
R/W
Bit 14
to
Bit 10
Function
Default
Unused
XXXXH
PROV
0
Unused
XXH
Bit 9
R/W
Reserved
0
Bit 8
R/W
Reserved
0
Bit 7
R/W
CHAN[7]
0
Bit 6
R/W
CHAN[6]
0
Bit 5
R/W
CHAN[5]
0
Bit 4
R/W
CHAN[4]
0
Bit 3
R/W
CHAN[3]
0
Bit 2
R/W
CHAN[2]
0
Bit 1
R/W
CHAN[1]
0
Bit 0
R/W
CHAN[0]
0
This register contains the data read from the transmit channel provision RAM
after an indirect read operation or the data to be inserted into the transmit
channel provision RAM in an indirect write operation.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
CHAN[7:0]:
The indirect data bits (CHAN[7:0]) report the channel number read from the
transmit channel provision RAM after an indirect read operation has
completed. Channel number to be written to the transmit channel provision
RAM in an indirect write operation must be set up in this register before
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triggering the write. CHAN[7:0] reflects the value written until the completion
of a subsequent indirect read operation.
PROV:
The indirect provision enable bit (PROV) reports the channel provision enable
flag read from transmit channel provision RAM after an indirect read
operation has completed. The provision enable flag to be written to the
transmit channel provision RAM in an indirect write operation must be set up
in this register before triggering the write. When PROV is set high, the
current time-slot is assigned to the channel as indicated by CHAN[7:0].
When PROV is set low, the time-slot does not belong to any channel. The
transmit link data is set to the contents of the Idle Time-slot Fill Data register.
PROV reflects the value written until the completion of a subsequent indirect
read operation.
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Register 0x408 : TCAS Framing Bit Threshold
Bit
Type
Bit 31
to
Bit 7
Function
Default
Unused
XXXXXXXH
Bit 6
R/W
FTHRES[6]
0
Bit 5
R/W
FTHRES[5]
1
Bit 4
R/W
FTHRES[4]
0
Bit 3
R/W
FTHRES[3]
0
Bit 2
R/W
FTHRES[2]
1
Bit 1
R/W
FTHRES[1]
0
Bit 0
R/W
FTHRES[0]
1
This register contains the threshold used by the clock activity monitors to detect
for framing bits/bytes.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
FTHRES[6:0]:
The framing bit threshold bits (FTHRES[6:0]) contains the threshold used by
the clock activity monitor to detect for the presence of framing bits. A counter
in the clock activity monitor of each receive link increments on each rising
edge of SYSCLK and is cleared, when the BSYNC bit of that link is set low,
by each rising edge of the corresponding TCLK[n]. When the BSYNC bit of
that link is set high, the counter is cleared at every fourth rising edge of the
corresponding TCLK[n]. When the counter exceeds the threshold given by
FTHRES[6:0], a framing bit/byte has been detected.
FTHRES[6:0] should be set as a function of the SYSCLK period and the
expected gapping width of TCLK[n] during data bits and during framing
bits/bytes. Legal range of FTHRES[6:0] is 'b0000001 to 'b1111110.
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Note: For operation with T1/J1 links and SYSCLK = 45 MHz, FTHRESH[6:0]
should be set to ‘b0100101’. The default value of this register reflects this
mode of operation.
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Register 0x40C : TCAS Idle Time-slot Fill Data
Bit
Type
Bit 31
to
Bit 8
Function
Default
Unused
XXXXXXH
Bit 7
R/W
FDATA[7]
1
Bit 6
R/W
FDATA[6]
1
Bit 5
R/W
FDATA[5]
1
Bit 4
R/W
FDATA[4]
1
Bit 3
R/W
FDATA[3]
1
Bit 2
R/W
FDATA[2]
1
Bit 1
R/W
FDATA[1]
1
Bit 0
R/W
FDATA[0]
1
This register contains the data to be written to disabled time-slots of a
channelised link.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
FDATA[7:0]:
The fill data bits (FDATA[7:0]) are transmitted during disabled (PROV set low)
time-slots of channelised links.
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Register 0x410 : TCAS Channel Disable
Bit
Type
Bit 31
to
Bit 16
Bit 15
R/W
Bit 14
to
Bit 10
Function
Default
Unused
XXXXH
CHDIS
0
Unused
XXH
Bit 9
R/W
Reserved
0
Bit 8
R/W
Reserved
0
Bit 7
R/W
DCHAN[7]
0
Bit 6
R/W
DCHAN[6]
0
Bit 5
R/W
DCHAN[5]
0
Bit 4
R/W
DCHAN[4]
0
Bit 3
R/W
DCHAN[3]
0
Bit 2
R/W
DCHAN[2]
0
Bit 1
R/W
DCHAN[1]
0
Bit 0
R/W
DCHAN[0]
0
This register controls the disabling of one specific channel to allow orderly
provisioning of time-slots.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
DCHAN[7:0]:
The disable channel number bits (DCHAN[7:0]) selects the channel to be
disabled. When CHDIS is set high, the channel specified by DCHAN[7:0] is
disabled. Data in time-slots associated with the specified channel is set to
FDATA[7:0] in the Idle Time-slot Fill Data register. When CHDIS is set low,
the channel specified by DCHAN[7:0] operates normally.
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CHDIS:
The channel disable bit (CHDIS) controls the disabling of the channels
specified by DCHAN[7:0]. When CHDIS is set high, the channel selected by
DCHAN[7:0] is disabled. Data in time-slots associated with the specified
channel is set to FDATA[7:0] in the Idle Time-slot Fill Data register. When
CHDIS is set low, the channel specified by DCHAN[7:0] operates normally.
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Register 0x480 – 0x488 : TCAS Links #0 to #2 Configuration
Bit
Type
Bit 31
to
Bit 5
Bit 4
R/W
Bit 3
Function
Default
Unused
XXXXXXXH
BSYNC
0
Unused
X
Bit 2
R/W
MODE[2]
0
Bit 1
R/W
MODE[1]
0
Bit 0
R/W
MODE[0]
0
This register configures operational modes of transmit links #0 to #2.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
MODE[2:0]:
The mode select bits (MODE[2:0]) configures the corresponding transmit link.
Table 27 details this procedure. When link 4m (0£m£7) is configured for
operation in 8.192 Mbps H-MVIP mode, links 4m+1, 4m+2 and 4m+3 are
driven with constant ones. However, links 4m+1, 4m+2 and 4m+3 must be
configured for 8.192 Mbps H-MVIP mode for correct operation of the
TCAS256. From a channel assignment point of view in the TCAS256
(Registers 0x100, 0x104), time-slots 0 through 31 of link 4m are mapped to
time-slots 0 through 31 of the H-MVIP link, time-slots 0 through 31 of link
4m+1 are mapped to time-slots 32 through 63 of the H-MVIP link, time-slots 0
through 31 of link 4m+2 are mapped to time-slots 64 through 95 of the HMVIP link and time-slots 0 through 31 of link 4m+3 are mapped to time-slots
96 through 127 of the H-MVIP link.
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Table 27 - Transmit Links #0 to #2 Configuration
MODE[2:0]
000
001
010
011
100
101
110
111
Link Configuration
Unchannelised
Channelised T1/J1 (24 time slots labeled 1-24)
Channelised E1 (31 time slots labeled 1-31)
2 Mbps H-MVIP (32 time slots labeled 0-31)
Reserved
Reserved
Reserved
8 Mbps H-MVIP (128 time slots mapped to timeslots 0 through 31 of links 4m, 4m+1, 4m+2 and
4m+3)
BSYNC:
The byte synchronization enable bit (BSYNC) controls the interpretation of
gaps in TCLK[n] when link #n is in unchannelised mode (MODE[2:0]=”000”).
When BSYNC is set high, the data bit on TD[n] clocked in by a downstream
device on the first rising edge of TCLK[n] after an extended quiescent period
is considered to be the most significant bit of a data byte. When BSYNC is
set quiescent, gaps in TCLK[n] carry no special significance. BSYNC is
ignored when MODE[2:0]¹”000”.
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Register 0x48C – 0x4FC : TCAS Links #3 to #31 Configuration
Bit
Type
Bit 31
to
Bit 3
Function
Default
Unused
XXXXXXXXH
Bit 2
R/W
MODE[2]
0
Bit 1
R/W
MODE[1]
0
Bit 0
R/W
MODE[0]
0
This register configures operational modes of transmit links #3 to #31.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
MODE[2:0]:
The mode select bits (MODE[2:0]) configures the corresponding transmit link.
Table 28 details this procedure. When link 4m (0£m£7) is configured for
operation in 8.192 Mbps H-MVIP mode, links 4m+1, 4m+2 and 4m+3 are
driven with constant ones. However, links 4m+1, 4m+2 and 4m+3 must be
configured for 8.192 Mbps H-MVIP mode for correct operation of the
TCAS256. From a channel assignment point of view in the TCAS256
(Registers 0x400, 0x404), time-slots 0 through 31 of link 4m are mapped to
time-slots 0 through 31 of the H-MVIP link, time-slots 0 through 31 of link
4m+1 are mapped to time-slots 32 through 63 of the H-MVIP link, time-slots 0
through 31 of link 4m+2 are mapped to time-slots 64 through 95 of the HMVIP link and time-slots 0 through 31 of link 4m+3 are mapped to time-slots
96 through 127 of the H-MVIP link.
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Table 28 - Transmit Links #3 to #31 Configuration
MODE[2:0]
000
001
010
011
100
101
110
111
Link Configuration
Unchannelised
Channelised T1/J1 (24 time slots labeled 1-24)
Channelised E1 (31 time slots labeled 1-31)
2 Mbps H-MVIP (32 time slots labeled 0-31)
Reserved
Reserved
Reserved
8 Mbps H-MVIP (128 time slots mapped to timeslots 0 through 31 of links 4m, 4m+1, 4m+2 and
4m+3)
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Register 0x500 : PMON Status
Bit
Type
Bit 31
to
Bit 6
Function
Default
Unused
XXXXXXXH
Bit 5
R
C2DET
X
Bit 4
R
C1DET
X
Bit 3
R
UFDET
X
Bit 2
R
OFDET
X
Bit 1
Unused
X
Bit 0
Unused
X
This register contains status information indicating whether a non-zero count has
been latched in the count registers.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
OFDET:
The overflow detect bit (OFDET) indicates the status of the PMON Receive
FIFO Overflow Count register. OFDET is set high when overflow events have
occurred during the latest PMON accumulation interval. OFDET is set low if
no overflow events are detected.
UFDET:
The underflow detect bit (UFDET) indicates the status of the PMON Transmit
FIFO Underflow Count register. UFDET is set high when underflow events
have occurred during the latest PMON accumulation interval. UFDET is set
low if no underflow events are detected.
C1DET:
The configurable event #1 detect bit (C1DET) indicates the status of the
PMON Configurable Count #1 register. C1DET is set high when selected
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events have occurred during the latest PMON accumulation interval. C1DET
is set low if no selected events are detected.
C2DET:
The configurable event #2 detect bit (C2DET) indicates the status of the
PMON Configurable Count #2 register. C2DET is set high when selected
events have occurred during the latest PMON accumulation interval. C2DET
is set low if no selected events are detected.
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Register 0x504 : PMON Receive FIFO Overflow Count
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R
OF[15]
X
Bit 14
R
OF[14]
X
Bit 13
R
OF[13]
X
Bit 12
R
OF[12]
X
Bit 11
R
OF[11]
X
Bit 10
R
OF[10]
X
Bit 9
R
OF[9]
X
Bit 8
R
OF[8]
X
Bit 7
R
OF[7]
X
Bit 6
R
OF[6]
X
Bit 5
R
OF[5]
X
Bit 4
R
OF[4]
X
Bit 3
R
OF[3]
X
Bit 2
R
OF[2]
X
Bit 1
R
OF[1]
X
Bit 0
R
OF[0]
X
This register reports the number of receive FIFO overflow events in the previous
accumulation interval.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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OF[15:0]:
The OF[15:0] bits reports the number of receive FIFO overflow events that
have been detected since the last time this register was polled. This register
is polled by writing to the FREEDM-32P256 Master Clock / BERT Activity
Monitor and Accumulation Trigger register. The write access transfers the
internally accumulated error count to the FIFO overflow register and
simultaneously resets the internal counter to begin a new cycle of error
accumulation.
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Register 0x508 : PMON Transmit FIFO Underflow Count
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R
UF[15]
X
Bit 14
R
UF[14]
X
Bit 13
R
UF[13]
X
Bit 12
R
UF[12]
X
Bit 11
R
UF[11]
X
Bit 10
R
UF[10]
X
Bit 9
R
UF[9]
X
Bit 8
R
UF[8]
X
Bit 7
R
UF[7]
X
Bit 6
R
UF[6]
X
Bit 5
R
UF[5]
X
Bit 4
R
UF[4]
X
Bit 3
R
UF[3]
X
Bit 2
R
UF[2]
X
Bit 1
R
UF[1]
X
Bit 0
R
UF[0]
X
This register reports the number of transmit FIFO underflow events in the
previous accumulation interval.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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UF[15:0]:
The UF[15:0] bits reports the number of transmit FIFO underflow events that
have been detected since the last time this register was polled. This register
is polled by writing to the FREEDM-32P256 Master Clock / BERT Activity
Monitor and Accumulation Trigger register. The write access transfers the
internally accumulated error count to the FIFO underflow register and
simultaneously resets the internal counter to begin a new cycle of error
accumulation.
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Register 0x50C : PMON Configurable Count #1
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R
C1[15]
X
Bit 14
R
C1[14]
X
Bit 13
R
C1[13]
X
Bit 12
R
C1[12]
X
Bit 11
R
C1[11]
X
Bit 10
R
C1[10]
X
Bit 9
R
C1[9]
X
Bit 8
R
C1[8]
X
Bit 7
R
C1[7]
X
Bit 6
R
C1[6]
X
Bit 5
R
C1[5]
X
Bit 4
R
C1[4]
X
Bit 3
R
C1[3]
X
Bit 2
R
C1[2]
X
Bit 1
R
C1[1]
X
Bit 0
R
C1[0]
X
This register reports the number events, selected by the FREEDM-32P256
Master Performance Monitor Control register, that occurred in the previous
accumulation interval.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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C1[15:0]:
The C1[15:0] bits reports the number of selected events that have been
detected since the last time this register was polled. This register is polled by
writing to the FREEDM-32P256 Master Clock / BERT Activity Monitor and
Accumulation Trigger register. The write access transfers the internally
accumulated error count to the configurable count #1 register and
simultaneously resets the internal counter to begin a new cycle of event
accumulation.
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Register 0x510 : PMON Configurable Count #2
Bit
Type
Bit 31
to
Bit 16
Function
Default
Unused
XXXXH
Bit 15
R
C2[15]
X
Bit 14
R
C2[14]
X
Bit 13
R
C2[13]
X
Bit 12
R
C2[12]
X
Bit 11
R
C2[11]
X
Bit 10
R
C2[10]
X
Bit 9
R
C2[9]
X
Bit 8
R
C2[8]
X
Bit 7
R
C2[7]
X
Bit 6
R
C2[6]
X
Bit 5
R
C2[5]
X
Bit 4
R
C2[4]
X
Bit 3
R
C2[3]
X
Bit 2
R
C2[2]
X
Bit 1
R
C2[1]
X
Bit 0
R
C2[0]
X
This register reports the number events, selected by the FREEDM-32P256
Master Performance Monitor Control register, that occurred in the previous
accumulation interval.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
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C2[15:0]:
The C2[15:0] bits reports the number of selected events that have been
detected since the last time this register was polled. This register is polled by
writing to the FREEDM-32P256 Master Clock / BERT Activity Monitor and
Accumulation Trigger register. The write access transfers the internally
accumulated error count to the configurable count #2 register and
simultaneously resets the internal counter to begin a new cycle of event
accumulation.
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PCI CONFIGURATION REGISTER DESCRIPTION
PCI configuration registers are implemented by the PCI Interface. These
registers can only be accessed when the PCI Interface is a target and a
configuration cycle is in progress as indicated using the IDSEL input.
Notes on PCI Configuration Register Bits:
1. Writing values into unused register bits has no effect. However, to ensure
software compatibility with future, feature-enhanced versions of the product,
unused register bits must be written with logic zero. Reading back unused
bits can produce either a logic one or a logic zero; hence unused register bits
should be masked off by software when read.
2. Except where noted, all configuration bits that can be written into can also be
read back. This allows the processor controlling the FREEDM-32P256 to
determine the programming state of the block.
3. Writable PCI configuration register bits are cleared to logic zero upon reset
unless otherwise noted.
4. Writing into read-only PCI configuration register bit locations does not affect
FREEDM-32P256 operation unless otherwise noted.
5. Certain register bits are reserved. These bits are associated with megacell
functions that are unused in this application. To ensure that the FREEDM32P256 operates as intended, reserved register bits must only be written with
their default values. Similarly, writing to reserved registers should be
avoided.
10.1 PCI Configuration Registers
PCI configuration registers can only be accessed by the PCI host. For each
register description below, the hexadecimal register number indicates the PCI
offset.
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Register 0x00 : Vendor Identification/Device Identification
Bit
Type
Function
Default
Bit 31
to
Bit 16
R
DEVID[15:0]
7382H
Bit 15
to
Bit 0
R
VNDRID[15:0]
11F8H
VNDRID[15:0]:
The VNDRID[15:0] bits identifies the manufacturer of the device. Valid vendor
identifiers are allocated by the PCI SIG.
DEVID[15:0]:
The DEVID[15:0] bits define the particular device. Valid device identifiers will
be specified by PMC-Sierra. The default value of DEVID[15:0] is that of the
FREEDM-32P256 device.
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Register 0x04 : Command/Status
Bit
Type
Function
Default
Bit 31
R/W
PERR
0
Bit 30
R/W
SERR
0
Bit 29
R/W
MABT
0
Bit 28
R/W
RTABT
0
Bit 27
R/W
TABT
0
Bit 26
R
DVSLT[1]
0
Bit 25
R
DVSLT[0]
1
Bit 24
R/W
DPR
0
Bit 23
R
FBTBE
1
Bit 22
R
Reserved
0
Bit 21
R
66MHZ_CAPABLE
1
Bit 20
to
Bit 16
R
Reserved
00H
Bit 15
to
Bit 10
R
Reserved
00H
Bit 9
R
FBTBEN
0
Bit 8
R/W
SERREN
0
Bit 7
R
ADSTP
0
Bit 6
R/W
PERREN
0
Bit 5
R
VGASNP
0
Bit 4
R
MWAI
0
Bit 3
R
SPCEN
0
Bit 2
R/W
MSTREN
0
Bit 1
R/W
MCNTRL
0
Bit 0
R
IOCNTRL
0
The lower 16 bits of this register make up the Command register which provides
basic control over the GPIC's ability to respond to PCI accesses. When a 0 is
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written to all bits in the command register, the GPIC is logically disconnected
from the PCI bus for all accesses except configuration accesses. The upper 16bits is used to record status information for PCI bus related events. Reads to the
status portion of this register behave normally. Writes are slightly different in that
bits can be reset, but not set. A bit is reset whenever the register is written, and
the data in the corresponding bit location is a 1.
IOCNTRL:
When IOCNTRL is set to zero, the GPIC will not respond to PCI bus I/O
accesses.
MCNTRL:
When MCNTRL is set to one, the GPIC will respond to PCI bus memory
accesses. Clearing MCNTRL disables memory accesses.
MSTREN:
When MSTREN is set to one, the GPIC can act as a Master. Clearing
MSTREN disables the GPIC from becoming a Master.
SPCEN:
The GPIC does not decode PCI special cycles. The SPCEN bit is forced low.
MWAI:
The GPIC does not generate memory-write-and-invalidate commands. The
MWAI bit is forced low.
VGASNP:
The GPIC is not a VGA device. The VGASNP bit is forced low.
PERREN:
When the PERREN bit is set to one, the GPIC can report parity errors.
Clearing the PERREN bit causes the GPIC to ignore parity errors.
ADSTP:
The GPIC does not perform address and data stepping. The ADSTP bit is
forced low.
SERREN:
When the SERREN bit is set high, the GPIC can drive the SERRB line.
Clearing the SERREN bit disables the SERRB line. SERREN and PERREN
must be set to report an address parity error.
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FBTBEN:
As a master, the GPIC does not generate fast back-to-back cycles to different
devices. This bit is forced low.
The upper 16-bits make up the PCI Status field. The status field tracks the
status of PCI bus related events. Reads to this register behave normally. Writes
are slightly different in that bits can be reset, but not set. A bit is reset whenever
the register is written, and the data in the corresponding bit location is a one.
66MHZ_CAPABLE:
The 66 MHz Capable bit is hardwired to one to indicate the GPIC is capable
of operating in 66 MHz mode.
FBTBE:
The FBTBE bit is hardwired to one to indicate the GPIC supports fast backto-back transactions with other targets.
DPR:
The Data Parity Reported (DPR) bit is set high if the GPIC is an initiator and
asserts or detects a parity error on the PERRB signal while the PERREN bit
is set in the Command register. The DPR bit is cleared by the PCI Host.
DVSLT[1:0]:
The Device Select Timing (DEVSLT) bits specify the allowable timings for the
assertion of DEVSELB by the GPIC as a target. These are encoded as 00B
for fast, 01B for medium, 10B for slow and 11B is not used. The GPIC allows
for medium timing.
TABT:
The Target Abort (TABT) bit is set high by the GPIC when as a target, it
terminates a transaction with a target abort. The TABT bit is cleared by the
PCI Host.
RTABT:
The Received Target Abort (RTABT) bit is set high by the GPIC when as an
initiator, its transaction is terminated by a target abort. The RTABT bit is
cleared by the PCI Host.
MABT:
The Master Abort (MABT) bit is set high by the GPIC when as an initiator, its
transaction is terminated by a master abort and a special cycle was not in
progress. The MABT bit is cleared by the PCI Host.
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SERR:
The System Error (SERR) bit is set high whenever the GPIC asserts the
SERRB output. The SERR bit is cleared by the PCI Host.
PERR:
The Parity Error (PERR) bit is set high whenever the GPIC detects a parity
error, even if parity error handling is disabled by clearing PERREN in the
Command register. The PERR bit is cleared by the PCI Host.
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Register 0x08 : Revision Identifier/Class Code
Bit
Type
Function
Default
Bit 31
to
Bit 24
R
CCODE[23:16]
02H
Bit 23
to
Bit 16
R
CCODE[15:8]
80H
Bit 15
to
Bit 8
R
CCODE[7:0]
00H
Bit 7
to
Bit 0
R
REVID[7:0]
02H
REVID[7:0]:
The Revision Identifier (REVID[7:0]) bits specify a device specific revision
identifier and are chosen by PMC-Sierra.
CCODE[23:0]:
The class code (CCODE[23:0]) bits are divided into three groupings:
CCODE[23:16] define the base class of the device, CCODE[15:8] define the
sub-class of the device and CCODE[7:0] specify a register specific
programming interface.
Note:
Base Class Code:
02H
Network Controller
Sub-Class Code:
80H
Other Controllers
Register Class Code:
00H
None defined.
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Register 0x0C : Cache Line Size/Latency Timer/Header Type
Bit
Type
Function
Default
Bit 31
to
Bit 24
R
Reserved
00H
Bit 23
R
MLTFNC
0
Bit 22
to
Bit 16
R
HDTYPE[6:0]
00H
Bit 15
to
Bit 8
R/W
LT[7:0]
00H
Bit 7
to
Bit 0
R/W
CLSIZE
00H
CLSIZE[7:0]:
The Cache Line Size (CLSIZE[7:0]) bits specify the size of the system
cacheline in units of dwords. The GPIC uses this value to determine the type
of read command to issue in a Master Read transfer. If the transfer size is
equal to one, the GPIC will issue a Memory Read command. If the transfer
size is equal to or less than the CLSIZE, the GPIC will issue a Memory Read
Line command. For transfers larger than CLSIZE, the GPIC issues a
Memory Read Multiple command.
LT[7:0]:
The Latency Timer (LT[7:0]) bits specify, in units of the PCI clock, the value of
the Latency Timer for the GPIC. At reset the value is zero. The value of the
LT is application specific and should be programmed by software.
HDTYPE[6:0]:
The Header Type (HDTYPE[7:0]) bits specify the layout of the base address
registers. Only the 00H encoding is supported.
MLTFNC:
The Multi-Function (MLTFNC) bit specifies if the GPIC supports multiple PCI
functions. If this bit is set low, the device only supports one function and if the
bit is set high, the device supports multi-functions. The MLTFNC bit is set low
to indicate the GPIC only supports one PCI function.
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Register 0x10 : CBI Memory Base Address Register
Bit
Type
Function
Default
Bit 31
to
Bit 13
R/W
BSAD[27:9]
00000H
Bit 12
to
Bit 4
R
BSAD[8:0]
000H
Bit 3
R
PRFTCH
0
Bit 2
R
TYPE[1]
0
Bit 1
R
TYPE[0]
0
Bit 0
R
MSI
0
The GPIC supports memory mapping only. At boot-up the internal registers
space is mapped to memory space. The device driver can disable memory space
through the PCI Configuration Command register.
MSI:
MSI is forced low to indicate that the internal registers map into memory
space.
TYPE[1:0]:
The TYPE field indicates where the internal registers can be mapped. The
encoding 00B indicates the registers may be located anywhere in the 32 bit
address space, 01B indicates that the registers must be mapped below 1
Meg in memory space, 10B indicates the base register is 64 bits and the
encoding 11B is reserved.
The TYPE field is set to 00B to indicate that the CBI registers can be mapped
anywhere in the 32 bit address space.
PRFTCH:
The Prefetchable (PRFTCH) bit is set if there are no side effects on reads
and data is returned on all the lanes regardless of the byte enables.
Otherwise the bit is cleared. TSBs contain registers, such as interrupt status
registers, in which bits are cleared on a read. If the PCI Host is caching data
there is a possibility an interrupt status could be lost if data is prefetched, but
the cache is flushed and the data is not used. The PRFTCH bit is forced low
to indicate that prefetching of data is not supported for internal registers.
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BSAD[27:0]:
The Base Address (BSAD[27:0]) bits defines the size and location of the
memory space required for the CBI registers. The BSAD[27:0] bits
correspond to the most significant 28 bits of the PCI address space.
The size of the address space required can be determined by writing all ones to
Base Address register and then reading from it. By scanning the returned value
from the least significant bit upwards, the size of the required address space can
be determined. The binary weighted value of the first one bit found (after the
configuration bits) indicates the required amount of space. The BSAD[8:0] bits
are forced low to indicate that the CBI registers require 8K bytes of memory
space.
After determining the memory requirements of the CBI registers, the PCI Host
can map them to its desired location by modifying the BSAD[27:9] bits in the
Base Address register.
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Register 0x3C : Interrupt Line / Interrupt Pin / MIN_GNT / MAX_LAT
Bit
Type
Function
Default
Bit 31
to
Bit 24
R
MAXLAT[7:0]
0FH
Bit 23
to
Bit 16
R
MINGNT[7:0]
05H
Bit 15
to
Bit 8
R
INTPIN[7:0]
01H
Bit 7
to
Bit 0
R/W
INTLNE[7:0]
00H
INTLNE[7:0]:
The Interrupt Line (INTLNE[7:0]) field is used to indicate interrupt line routing
information. The values in this register are system specific and set by the PCI
Host.
INTPIN[7:0]:
The Interrupt Pin (INTPIN[7:0]) field is used to specify the interrupt pin the
GPIC uses. Since the GPIC will use INTAB on the PCI bus, the value in this
register is set to one.
MINGNT[7:0]:
The Minimum Grant (MINGNT[7:0]) field specifies how long of a burst period
the bus master needs (in increments of 250 nsec).
MAXLAT[7:0]:
The Maximum Latency (MAXLAT[7:0]) field specifies how often a bus master
needs access to the PCI bus (in increments of 250 nsec).
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TEST FEATURES DESCRIPTION
The FREEDM-32P256 also supports a standard IEEE 1149.1 five signal JTAG
boundary scan test port for use in board testing. All device inputs may be read
and all device outputs may be forced via the JTAG test port.
11.1 Test Mode Registers
Test mode registers are used to apply test vectors during production testing of
the FREEDM-32P256. Production testing is enabled by asserting the PMCTEST
pin. During production tests, FREEDM-32P256 registers are selected by the
TA[12:0] pins. The address of a register on TA[12:0] is identical to the PCI offset
of that register when production testing is disabled (PMCTEST low). Read
accesses are enabled by asserting TRDB low while write accesses are enabled
by asserting TWRB low. Test mode register data is conveyed on the TDAT[15:0]
pins. Test mode registers (as opposed to normal mode registers) are selected
when TA[12]/TRS is set high.
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Table 29 – Test Mode Register Memory Map
Address TA[12:0]
Register
0x0000 - 0x07FC
Normal Mode Registers
0x0800 - 0x107C
Reserved
0x1080 - 0x10FC
GPIC Test Registers
0x1100 - 0x11FC
RCAS Test Registers
0x1200 - 0x123C
RHDL Test Registers
0x1240 - 0x127C
Reserved
0x1280 - 0x12FC
RMAC Test Registers
0x1300 - 0x137C
TMAC Test Registers
0x1380 - 0x13BC
THDL Test Registers
0x13C0 - 0x13FC
Reserved
0x1400 - 0x14FC
TCAS Test Registers
0x1500 - 0x151C
PMON Test Registers
0x1520 - 0x1FFC
Reserved
Notes on Test Mode Register Bits:
1. Writing values into unused register bits has no effect. However, to ensure
software compatibility with future, feature-enhanced versions of the product,
unused register bits must be written with logic zero. Reading back unused
bits can produce either a logic one or a logic zero; hence unused register bits
should be masked off by software when read.
2. Writable test mode register bits are not initialized upon reset unless otherwise
noted.
11.2 JTAG Test Port
The FREEDM-32P256 JTAG Test Access Port (TAP) allows access to the TAP
controller and the 4 TAP registers: instruction, bypass, device identification and
boundary scan. Using the TAP, device input logic levels can be read, device
outputs can be forced, the device can be identified and the device scan path can
be bypassed. For more details on the JTAG port, please refer to the Operations
section.
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Table 30 – Instruction Register
Length - 3 bits
Instructions
Selected Register
Instruction Code IR[2:0]
EXTEST
Boundary Scan
000
IDCODE
Identification
001
SAMPLE
Boundary Scan
010
BYPASS
Bypass
011
BYPASS
Bypass
100
STCTEST
Boundary Scan
101
BYPASS
Bypass
110
BYPASS
Bypass
111
11.2.1 Identification Register
Length - 32 bits
Version number - 2H
Part Number - 7382H
Manufacturer's identification code - 0CDH
Device identification - 273820CDH
11.2.2 Boundary Scan Register
The boundary scan register is made up of 365 boundary scan cells, divided into
input observation (in_cell), output (out_cell), and bi-directional (io_cell) cells.
These cells are detailed in the following pages. The first 32 cells form the ID
code register, and carry the code 273820CDH. The cells are arranged as
follows:
Table 31 – Boundary Scan Chain
Pin/ Enable
Register Bit
Cell Type
Device I.D.
RBCLK_OEN
0
OUT_CELL
-
RBCLK
1
OUT_CELL
-
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Pin/ Enable
FRAME ENGINE AND DATA LINK MANAGER 32P256
Register Bit
Cell Type
Device I.D.
RBD_OEN
2
OUT_CELL
-
RBD
3
OUT_CELL
-
TMV8DC
4
IN_CELL
-
TFP8B
5
IN_CELL
-
TMV8FPC
6
IN_CELL
-
TFPB[0]
7
IN_CELL
-
TMVCK[0]
8
IN_CELL
-
TD_OEN[0]
9
OUT_CELL
-
TD[0]
10
OUT_CELL
-
TCLK[0]
11
IN_CELL
-
TD_OEN[1]
12
OUT_CELL
-
TD[1]
13
OUT_CELL
-
TCLK[1]
14
IN_CELL
-
TD_OEN[2]
15
OUT_CELL
-
TD[2]
16
OUT_CELL
-
TCLK[2]
17
IN_CELL
-
TD_OEN[3]
18
OUT_CELL
-
TD[3]
19
OUT_CELL
-
TCLK[3]
20
IN_CELL
-
TD_OEN[4]
21
OUT_CELL
-
TD[4]
22
OUT_CELL
-
TCLK[4]
23
IN_CELL
-
TD_OEN[5]
24
OUT_CELL
-
TD[5]
25
OUT_CELL
-
TCLK[5]
26
IN_CELL
-
TD_OEN[6]
27
OUT_CELL
-
TD[6]
28
OUT_CELL
-
TCLK[6]
29
IN_CELL
-
TD_OEN[7]
30
OUT_CELL
-
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Pin/ Enable
FRAME ENGINE AND DATA LINK MANAGER 32P256
Register Bit
Cell Type
Device I.D.
TD[7]
31
OUT_CELL
-
TCLK[7]
32
IN_CELL
-
TFPB[1]
33
IN_CELL
-
TMVCK[1]
34
IN_CELL
-
TD_OEN[8]
35
OUT_CELL
-
TD[8]
36
OUT_CELL
-
TCLK[8]
37
IN_CELL
-
TD_OEN[9]
38
OUT_CELL
-
TD[9]
39
OUT_CELL
-
TCLK[9]
40
IN_CELL
-
TD_OEN[10]
41
OUT_CELL
-
TD[10]
42
OUT_CELL
-
TCLK[10]
43
IN_CELL
-
TD_OEN[11]
44
OUT_CELL
-
TD[11]
45
OUT_CELL
-
TCLK[11]
46
IN_CELL
-
TD_OEN[12]
47
OUT_CELL
-
TD[12]
48
OUT_CELL
-
TCLK[12]
49
IN_CELL
-
TD_OEN[13]
50
OUT_CELL
-
TD[13]
51
OUT_CELL
-
TCLK[13]
52
IN_CELL
-
TD_OEN[14]
53
OUT_CELL
-
TD[14]
54
OUT_CELL
-
TCLK[14]
55
IN_CELL
-
TD_OEN[15]
56
OUT_CELL
-
TD[15]
57
OUT_CELL
-
TCLK[15]
58
IN_CELL
-
TFPB[2]
59
IN_CELL
-
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Pin/ Enable
FRAME ENGINE AND DATA LINK MANAGER 32P256
Register Bit
Cell Type
Device I.D.
TMVCK[2]
60
IN_CELL
-
TD_OEN[16]
61
OUT_CELL
-
TD[16]
62
IO_CELL
-
TCLK[16]
63
IN_CELL
-
TD_OEN[17]
64
OUT_CELL
-
TD[17]
65
IO_CELL
-
TCLK[17]
66
IN_CELL
-
TD_OEN[18]
67
OUT_CELL
-
TD[18]
68
IO_CELL
-
TCLK[18]
69
IN_CELL
-
TD_OEN[19]
70
OUT_CELL
-
TD[19]
71
IO_CELL
-
TCLK[19]
72
IN_CELL
-
TD_OEN[20]
73
OUT_CELL
-
TD[20]
74
IO_CELL
-
TCLK[20]
75
IN_CELL
-
TD_OEN[21]
76
OUT_CELL
-
TD[21]
77
IO_CELL
-
TCLK[21]
78
IN_CELL
-
TD_OEN[22]
79
OUT_CELL
-
TD[22]
80
IO_CELL
-
TCLK[22]
81
IN_CELL
-
TD_OEN[23]
82
OUT_CELL
-
TD[23]
83
IO_CELL
-
TCLK[23]
84
IN_CELL
-
TFPB[3]
85
IN_CELL
-
TMVCK[3]
86
IN_CELL
-
TD_OEN[24]
87
OUT_CELL
-
TD[24]
88
IO_CELL
-
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Pin/ Enable
FRAME ENGINE AND DATA LINK MANAGER 32P256
Register Bit
Cell Type
Device I.D.
TCLK[24]
89
IN_CELL
-
TD_OEN[25]
90
OUT_CELL
-
TD[25]
91
IO_CELL
-
TCLK[25]
92
IN_CELL
-
TD_OEN[26]
93
OUT_CELL
-
TD[26]
94
IO_CELL
-
TCLK[26]
95
IN_CELL
-
TD_OEN[27]
96
OUT_CELL
-
TD[27]
97
IO_CELL
-
TCLK[27]
98
IN_CELL
-
TD_OEN[28]
99
OUT_CELL
-
TD[28]
100
IO_CELL
-
TCLK[28]
101
IN_CELL
-
TD_OEN[29]
102
OUT_CELL
-
TD[29]
103
IO_CELL
-
TCLK[29]
104
IN_CELL
-
TD_OEN[30]
105
OUT_CELL
-
TD[30]
106
IO_CELL
-
TCLK[30]
107
IN_CELL
-
TD_OEN[31]
108
OUT_CELL
-
TD[31]
109
IO_CELL
-
TCLK[31]
110
IN_CELL
-
TBD
111
IN_CELL
-
TBCLK_OEN
112
OUT_CELL
-
TBCLK
113
OUT_CELL
-
PMCTEST
114
IN_CELL
-
Logic 0
115
IN_CELL
-
Logic 0
116
IN_CELL
-
Logic 0
117
IN_CELL
-
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Pin/ Enable
FRAME ENGINE AND DATA LINK MANAGER 32P256
Register Bit
Cell Type
Device I.D.
M66EN
118
IN_CELL
-
AD_OEN[0]
119
OUT_CELL
-
AD[0]
120
IO_CELL
-
AD_OEN[1]
121
OUT_CELL
-
AD[1]
122
IO_CELL
-
AD_OEN[2]
123
OUT_CELL
-
AD[2]
124
IO_CELL
-
AD_OEN[3]
125
OUT_CELL
-
AD[3]
126
IO_CELL
-
AD_OEN[4]
127
OUT_CELL
-
AD[4]
128
IO_CELL
-
AD_OEN[5]
129
OUT_CELL
-
AD[5]
130
IO_CELL
-
AD_OEN[6]
131
OUT_CELL
-
AD[6]
132
IO_CELL
-
AD_OEN[7]
133
OUT_CELL
-
AD[7]
134
IO_CELL
-
CBEB_OEN[0]
135
OUT_CELL
-
CBEB[0]
136
IO_CELL
-
AD_OEN[8]
137
OUT_CELL
-
AD[8]
138
IO_CELL
-
AD_OEN[9]
139
OUT_CELL
-
AD[9]
140
IO_CELL
-
AD_OEN[10]
141
OUT_CELL
-
AD[10]
142
IO_CELL
-
AD_OEN[11]
143
OUT_CELL
-
AD[11]
144
IO_CELL
-
AD_OEN[12]
145
OUT_CELL
-
AD[12]
146
IO_CELL
-
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Pin/ Enable
FRAME ENGINE AND DATA LINK MANAGER 32P256
Register Bit
Cell Type
Device I.D.
AD_OEN[13]
147
OUT_CELL
-
AD[13]
148
IO_CELL
-
AD_OEN[14]
149
OUT_CELL
-
AD[14]
150
IO_CELL
-
AD_OEN[15]
151
OUT_CELL
-
AD[15]
152
IO_CELL
-
CBEB_OEN[1]
153
OUT_CELL
-
CBEB[1]
154
IO_CELL
-
PAR_OEN
155
OUT_CELL
-
PAR
156
IO_CELL
-
SERRB_OEN
157
OUT_CELL
-
SERRB
158
IO_CELL
-
PERRB_OEN
159
OUT_CELL
-
PERRB
160
IO_CELL
-
LOCKB
161
IN_CELL
-
STOPB_OEN
162
OUT_CELL
-
STOPB
163
IO_CELL
-
DEVSELB_OEN
164
OUT_CELL
-
DEVSELB
165
IO_CELL
-
TRDYB_OEN
166
OUT_CELL
-
TRDYB
167
IO_CELL
-
IRDYB_OEN
168
OUT_CELL
IRDYB
169
IO_CELL
-
FRAMEB_OEN
170
OUT_CELL
-
FRAMEB
171
IO_CELL
-
CBEB_OEN[2]
172
OUT_CELL
-
CBEB[2]
173
IO_CELL
-
AD_OEN[16]
174
OUT_CELL
-
AD[16]
175
IO_CELL
-
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Pin/ Enable
FRAME ENGINE AND DATA LINK MANAGER 32P256
Register Bit
Cell Type
Device I.D.
AD_OEN[17]
176
OUT_CELL
-
AD[17]
177
IO_CELL
-
AD_OEN[18]
178
OUT_CELL
-
AD[18]
179
IO_CELL
-
AD_OEN[19]
180
OUT_CELL
-
AD[19]
181
IO_CELL
-
AD_OEN[20]
182
OUT_CELL
-
AD[20]
183
IO_CELL
-
AD_OEN[21]
184
OUT_CELL
-
AD[21]
185
IO_CELL
-
AD_OEN[22]
186
OUT_CELL
-
AD[22]
187
IO_CELL
-
AD_OEN[23]
188
OUT_CELL
-
AD[23]
189
IO_CELL
-
IDSEL
190
IN_CELL
-
CBEB_OEN[3]
191
OUT_CELL
-
CBEB[3]
192
IO_CELL
-
AD_OEN[24]
193
OUT_CELL
-
AD[24]
194
IO_CELL
-
AD_OEN[25]
195
OUT_CELL
-
AD[25]
196
IO_CELL
-
AD_OEN[26]
197
OUT_CELL
-
AD[26]
198
IO_CELL
-
AD_OEN[27]
199
OUT_CELL
-
AD[27]
200
IO_CELL
-
AD_OEN[28]
201
OUT_CELL
-
AD[28]
202
IO_CELL
-
AD_OEN[29]
203
OUT_CELL
-
AD[29]
204
IO_CELL
-
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Pin/ Enable
FRAME ENGINE AND DATA LINK MANAGER 32P256
Register Bit
Cell Type
Device I.D.
AD_OEN[30]
205
OUT_CELL
-
AD[30]
206
IO_CELL
-
AD_OEN[31]
207
OUT_CELL
-
AD[31]
208
IO_CELL
-
REQB_OEN
209
OUT_CELL
-
REQB
210
IO_CELL
-
Logic 0
211
IN_CELL
-
GNTB
212
IN_CELL
-
PCICLK
213
IN_CELL
-
Logic 0
214
IN_CELL
-
PCICLKO_OEN
215
OUT_CELL
-
PCICLKO
216
OUT_CELL
-
Logic 0
217
IN_CELL
-
PCIINTB_OEN
218
OUT_CELL
-
PCIINTB
219
IO_CELL
-
Logic 0
220
IN_CELL
-
Logic 0
221
IN_CELL
-
Logic 0
222
IN_CELL
-
Logic 0
223
IN_CELL
-
Logic 0
224
IN_CELL
-
Logic 0
225
IN_CELL
-
Logic 0
226
IN_CELL
-
Logic 0
227
IN_CELL
-
Unconnected
228
OUT_CELL
-
Unconnected
229
IO_CELL
-
Unconnected
230
OUT_CELL
-
Unconnected
231
IO_CELL
-
Unconnected
232
OUT_CELL
-
Unconnected
233
IO_CELL
-
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Pin/ Enable
FRAME ENGINE AND DATA LINK MANAGER 32P256
Register Bit
Cell Type
Device I.D.
Unconnected
234
OUT_CELL
-
Unconnected
235
IO_CELL
-
Unconnected
236
OUT_CELL
-
Unconnected
237
IO_CELL
-
Unconnected
238
OUT_CELL
-
Unconnected
239
IO_CELL
-
Unconnected
240
OUT_CELL
-
Unconnected
241
IO_CELL
-
Unconnected
242
OUT_CELL
-
Unconnected
243
IO_CELL
-
Unconnected
244
OUT_CELL
-
Unconnected
245
IO_CELL
-
Unconnected
246
OUT_CELL
-
Unconnected
247
IO_CELL
-
Unconnected
248
OUT_CELL
-
Unconnected
249
IO_CELL
-
Unconnected
250
OUT_CELL
-
Unconnected
251
IO_CELL
-
Unconnected
252
OUT_CELL
-
Unconnected
253
IO_CELL
-
Unconnected
254
OUT_CELL
-
Unconnected
255
IO_CELL
-
Unconnected
256
OUT_CELL
-
Unconnected
257
IO_CELL
-
Unconnected
258
OUT_CELL
-
Unconnected
259
IO_CELL
-
Unconnected
260
OUT_CELL
-
Unconnected
261
IO_CELL
-
Unconnected
262
OUT_CELL
-
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Pin/ Enable
FRAME ENGINE AND DATA LINK MANAGER 32P256
Register Bit
Cell Type
Device I.D.
Unconnected
263
IO_CELL
-
Unconnected
264
OUT_CELL
-
Unconnected
265
IO_CELL
-
Unconnected
266
OUT_CELL
-
Unconnected
267
IO_CELL
-
Unconnected
268
OUT_CELL
-
Unconnected
269
IO_CELL
-
Unconnected
270
OUT_CELL
-
Unconnected
271
IO_CELL
-
Logic 0
272
IN_CELL
-
Logic 0
273
IN_CELL
-
Logic 0
274
IN_CELL
-
Logic 0
275
IN_CELL
-
Logic 0
276
IN_CELL
-
Logic 0
277
IN_CELL
-
Logic 0
278
IN_CELL
-
Logic 0
279
IN_CELL
-
Logic 0
280
IN_CELL
-
Logic 0
281
IN_CELL
-
Logic 1
282
IN_CELL
-
Logic 1
283
IN_CELL
-
Logic 1
284
IN_CELL
-
Logic 1
285
IN_CELL
-
Unconnected
286
OUT_CELL
-
Unconnected
287
OUT_CELL
-
RCLK[31]
288
IN_CELL
-
RD[31]
289
IN_CELL
-
RCLK[30]
290
IN_CELL
-
RD[30]
291
IN_CELL
-
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Pin/ Enable
FRAME ENGINE AND DATA LINK MANAGER 32P256
Register Bit
Cell Type
Device I.D.
RCLK[29]
292
IN_CELL
-
RD[29]
293
IN_CELL
-
RCLK[28]
294
IN_CELL
-
RD[28]
295
IN_CELL
-
RCLK[27]
296
IN_CELL
-
RD[27]
297
IN_CELL
-
RCLK[26]
298
IN_CELL
-
RD[26]
299
IN_CELL
-
RCLK[25]
300
IN_CELL
-
RD[25]
301
IN_CELL
-
RCLK[24]
302
IN_CELL
-
RD[24]
303
IN_CELL
-
RMVCK[3]
304
IN_CELL
-
RFPB[3]
305
IN_CELL
-
RCLK[23]
306
IN_CELL
-
RD[23]
307
IN_CELL
-
RCLK[22]
308
IN_CELL
-
RD[22]
309
IN_CELL
-
RCLK[21]
310
IN_CELL
-
RD[21]
311
IN_CELL
-
RCLK[20]
312
IN_CELL
-
RD[20]
313
IN_CELL
-
RCLK[19]
314
IN_CELL
-
RD[19]
315
IN_CELL
-
RCLK[18]
316
IN_CELL
-
RD[18]
317
IN_CELL
-
RCLK[17]
318
IN_CELL
-
RD[17]
319
IN_CELL
-
RCLK[16]
320
IN_CELL
-
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Register Bit
Cell Type
Device I.D.
RD[16]
321
IN_CELL
-
RMVCK[2]
322
IN_CELL
-
RFPB[2]
323
IN_CELL
-
RCLK[15]
324
IN_CELL
-
RD[15]
325
IN_CELL
-
RSTB
326
IN_CELL
-
RCLK[14]
327
IN_CELL
-
RD[14]
328
IN_CELL
-
RCLK[13]
329
IN_CELL
-
RD[13]
330
IN_CELL
-
RCLK[12]
331
IN_CELL
-
RD[12]
332
IN_CELL
-
RCLK[11]
333
IN_CELL
1
RD[11]
334
IN_CELL
0
RCLK[10]
335
IN_CELL
1
RD[10]
336
IN_CELL
1
RCLK[9]
337
IN_CELL
0
RD[9]
338
IN_CELL
0
RCLK[8]
339
IN_CELL
1
RD[8]
340
IN_CELL
1
RMVCK[1]
341
IN_CELL
0
RFPB[1]
342
IN_CELL
0
RCLK[7]
343
IN_CELL
0
RD[7]
344
IN_CELL
0
RCLK[6]
345
IN_CELL
0
RD[6]
346
IN_CELL
1
SYSCLK
347
IN_CELL
0
RCLK[5]
348
IN_CELL
0
RD[5]
349
IN_CELL
0
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Register Bit
Cell Type
Device I.D.
RCLK[4]
350
IN_CELL
0
RD[4]
351
IN_CELL
0
RCLK[3]
352
IN_CELL
1
RD[3]
353
IN_CELL
1
RCLK[2]
354
IN_CELL
1
RD[2]
355
IN_CELL
0
RCLK[1]
356
IN_CELL
0
RD[1]
357
IN_CELL
1
RCLK[0]
358
IN_CELL
1
RD[0]
359
IN_CELL
1
RMVCK[0]
360
IN_CELL
0
RFPB[0]
361
IN_CELL
0
RMV8FPC
362
IN_CELL
1
RFP8B
363
IN_CELL
0
RMV8DC
364
IN_CELL
0
TDO
TAP Output
-
TDI
TAP Input
-
TCK
TAP Clock
-
TMS
TAP Input
-
TRSTB
TAP Input
-
Notes:
1. RMV8DC is the first bit of the scan chain (closest to TDI).
2. Enable cell pinname_OEN, tristates pin pinname when set high.
3. Cells ‘Logic 0’ and ‘Logic 1’ are Input Observation cells whose input pad is
bonded to VSS or VDD internally.
4. Cells titled ‘Unconnected’ are Output or Bi-directional cells whose pad is
unconnected to the device package. In the case of bi-directional cells, the
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pad always drives (i.e. never tri-states) and the pad input is the same logic
value as the pad output.
Figure 17 – Input Observation Cell (IN_CELL)
IDCODE
Scan Chain Out
INPUT
to internal
logic
Input
Pad
G1
G2
SHIFT-DR
I.D. Code bit
12
1 2 MUX
12
12
D
C
CLOCK-DR
Scan Chain In
In this diagram and those that follow, CLOCK-DR is equal to TCK when the
current controller state is SHIFT-DR or CAPTURE-DR, and unchanging
otherwise. The multiplexor in the center of the diagram selects one of four
inputs, depending on the status of select lines G1 and G2. The ID Code bit is as
listed in the table above.
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Figure 18 – Output Cell (OUT_CELL)
Scan Chain Out
G1
EXTEST
Output or Enable
from system logic
IDCODE
SHIFT-DR
I.D. code bit
1
G1
G2
1
1
1
1
1
2
2 MUX
2
2
Output or
Enable
MUX
D
D
C
C
CLOCK-DR
UPDATE-DR
Scan Chain In
Figure 19 – Bi-directional Cell (IO_CELL)
Scan Chain Out
G1
EXTEST
OUTPUT from
internal logic
IDCODE
1
OUTPUT
to pin
MUX
1
G1
G2
SHIFT-DR
INPUT
from pin
I.D. code bit
INPUT
to internal
logic
12
1 2 MUX
12
12
D
C
D
C
CLOCK-DR
UPDATE-DR
Scan Chain In
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Figure 20 – Layout of Output Enable and Bi-directional Cells
Scan Chain Out
OUTPUT ENABLE
from internal
logic (0 = drive)
OUT_CELL
Scan Chain In
Scan Chain Out
INPUT to
internal logic
OUTPUT from
internal logic
IO_CELL
I/O
PAD
Scan Chain In
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OPERATIONS
This section presents connection details to the PM4388 TOCTL device, and
operating details for the JTAG boundary scan feature.
12.1 TOCTL Connections
The required connections between the PM4388 TOCTL and the FREEDM32P256 are shown in the following table:
Table 32 – FREEDM–TOCTL Connections
FREEDM-32P256
Pin
Direction
TOCTL Pin
RCLK[n]
¬
ICLK/ISIG[m]
RD[n]
¬
ID[m]
n.c.
¬
IFP[m]
TCLK[n]
¬
EFP/RCLK/ESIG[m]
TD[n]
®
ED[m]
All 8 framers in the TOCTL should be programmed to operate in “Clock Master:
NxDS0” mode in both the ingress and egress direction.
12.2 JTAG Support
The FREEDM-32P256 supports the IEEE Boundary Scan Specification as
described in the IEEE 1149.1 standards. The Test Access Port (TAP) consists of
the five standard pins, TRSTB, TCK, TMS, TDI and TDO used to control the TAP
controller and the boundary scan registers. The TRSTB input is the active low
reset signal used to reset the TAP controller. TCK is the test clock used to
sample data on input, TDI and to output data on output, TDO. The TMS input is
used to direct the TAP controller through its states. The basic boundary scan
architecture is shown below.
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Figure 21 – Boundary Scan Architecture
Boundary Scan
Register
TDI
Device Identification
Register
Bypass
Register
Instruction
Register
and
Decode
Mux
DFF
TDO
Control
TMS
Test
Access
Port
Controller
Select
Tri-state Enable
TRSTB
TCK
The boundary scan architecture consists of a TAP controller, an instruction
register with instruction decode, a bypass register, a device identification register
and a boundary scan register. The TAP controller interprets the TMS input and
generates control signals to load the instruction and data registers. The
instruction register with instruction decode block is used to select the test to be
executed and/or the register to be accessed. The bypass register offers a single
bit delay from primary input, TDI to primary output , TDO. The device
identification register contains the device identification code.
The boundary scan register allows testing of board inter-connectivity. The
boundary scan register consists of a shift register placed in series with device
inputs and outputs. Using the boundary scan register, all digital inputs can be
sampled and shifted out on primary output TDO. In addition, patterns can be
shifted in on primary input, TDI and forced onto all digital outputs.
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TAP Controller
The TAP controller is a synchronous finite state machine clocked by the rising
edge of primary input, TCK. All state transitions are controlled using primary
input, TMS. The finite state machine is described below.
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Figure 22 – TAP Controller Finite State Machine
TRSTB=0
Test-Logic-Reset
1
0
1
1
Run-Test-Idle
1
Select-IR-Scan
Select-DR-Scan
0
0
0
1
1
Capture-IR
Capture-DR
0
0
Shift-IR
Shift-DR
1
1
0
1
1
Exit1-IR
Exit1-DR
0
0
Pause-IR
Pause-DR
0
1
0
1
0
0
Exit2-DR
Exit2-IR
1
1
Update-IR
Update-DR
1
0
1
0
0
All transitions dependent on input TMS
Test-Logic-Reset
The test logic reset state is used to disable the TAP logic when the device is in
normal mode operation. The state is entered asynchronously by asserting input,
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TRSTB. The state is entered synchronously regardless of the current TAP
controller state by forcing input, TMS high for 5 TCK clock cycles. While in this
state, the instruction register is set to the IDCODE instruction.
Run-Test-Idle
The run test/idle state is used to execute tests.
Capture-DR
The capture data register state is used to load parallel data into the test data
registers selected by the current instruction. If the selected register does not
allow parallel loads or no loading is required by the current instruction, the test
register maintains its value. Loading occurs on the rising edge of TCK.
Shift-DR
The shift data register state is used to shift the selected test data registers by
one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK.
Update-DR
The update data register state is used to load a test register's parallel output
latch. In general, the output latches are used to control the device. For
example, for the EXTEST instruction, the boundary scan test register's parallel
output latches are used to control the device's outputs. The parallel output
latches are updated on the falling edge of TCK.
Capture-IR
The capture instruction register state is used to load the instruction register with
a fixed instruction. The load occurs on the rising edge of TCK.
Shift-IR
The shift instruction register state is used to shift both the instruction register and
the selected test data registers by one stage. Shifting is from MSB to LSB and
occurs on the rising edge of TCK.
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Update-IR
The update instruction register state is used to load a new instruction into the
instruction register. The new instruction must be scanned in using the Shift-IR
state. The load occurs on the falling edge of TCK.
The Pause-DR and Pause-IR states are provided to allow shifting through the
test data and/or instruction registers to be momentarily paused.
Boundary Scan Instructions
The following is a description of the standard instructions. Each instruction
selects a serial test data register path between input, TDI and output, TDO.
BYPASS
The bypass instruction shifts data from input, TDI to output, TDO with one TCK
clock period delay. The instruction is used to bypass the device.
EXTEST
The external test instruction allows testing of the interconnection to other
devices. When the current instruction is the EXTEST instruction, the boundary
scan register is place between input, TDI and output, TDO. Primary device
inputs can be sampled by loading the boundary scan register using the
Capture-DR state. The sampled values can then be viewed by shifting the
boundary scan register using the Shift-DR state. Primary device outputs can be
controlled by loading patterns shifted in through input TDI into the boundary scan
register using the Update-DR state.
SAMPLE
The sample instruction samples all the device inputs and outputs. For this
instruction, the boundary scan register is placed between TDI and TDO. Primary
device inputs and outputs can be sampled by loading the boundary scan register
using the Capture-DR state. The sampled values can then be viewed by shifting
the boundary scan register using the Shift-DR state.
IDCODE
The identification instruction is used to connect the identification register
between TDI and TDO. The device's identification code can then be shifted out
using the Shift-DR state.
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STCTEST
The single transport chain instruction is used to test out the TAP controller and
the boundary scan register during production test. When this instruction is the
current instruction, the boundary scan register is connected between TDI and
TDO. During the Capture-DR state, the device identification code is loaded into
the boundary scan register. The code can then be shifted out output, TDO using
the Shift-DR state.
INTEST
The internal test instruction is used to exercise the device's internal core logic.
When this instruction is the current instruction, the boundary scan register is
connected between TDI and TDO. During the Update-DR state, patterns shifted
in on input, TDI are used to drive primary inputs. During the Capture-DR state,
primary outputs are sampled and loaded into the boundary scan register.
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FUNCTIONAL TIMING
13.1 Receive H-MVIP Link Timing
The timing relationship of the receive data clock (RMV8DC), frame pulse clock
(RMV8FPC), data (RD[n]) and frame pulse (RFP8B[n]) signals of a link
configured for 8.192 Mbps H-MVIP operation with a type 0 frame pulse is shown
in Figure 23. The falling edges of each RMV8FPC are aligned to a falling edge
of the corresponding RMV8DC for 8.192 Mbps H-MVIP operation. The
FREEDM-32P256 samples RFP8B low on the falling edge of RMV8FPC and
references this point as the start of the next frame. The FREEDM-32P256
samples the data provided on RD[n] at the ¾ point of the data bit using the rising
edge of RMV8DC as indicated for bit 1 (B1) of time-slot 0 (TS 0) in Figure 23.
B1 is the most significant bit and B8 is the least significant bit of each octet.
Time-slots can be ignored by setting the PROV bit in the corresponding word of
the receive channel provision RAM in the RCAS256 block to low.
Figure 23 – Receive 8.192 Mbps H-MVIP Link Timing
RM V8DC
(16 M Hz)
RM V8F PC
(4 MHz)
RF P8B
RD[n]
B8
TS 127
B1
B2
B3
B4
B5
B6
B7
TS 0
B8
B1
TS 1
The timing relationship of the receive data clock (RMVCK[n]), data (RD[m],
where 8n£m£8n+7) and frame pulse (RFPB[n]) signals of a link configured for
2.048 Mbps H-MVIP operation with a type 0 frame pulse is shown in Figure 24.
The FREEDM-32P256 samples RFPB[n] low on the falling edge of the
corresponding RMVCK[n] and references this point as the start of the next
frame. The FREEDM-32P256 samples the data provided on RD[m] at the ¾
point of the data bit using the rising edge of the corresponding RMVCK[n] as
indicated for bit 1 (B1) of time-slot 0 (TS 0) in Figure 24. B1 is the most
significant bit and B8 is the least significant bit of each octet. Time-slots can be
ignored by setting the PROV bit in the corresponding word of the receive channel
provision RAM in the RCAS256 block to low.
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Figure 24 – Receive 2.048 Mbps H-MVIP Link Timing
RM VCK[n]
(4 MHz)
RFPB[n]
RD[m ]
B8
B1
B2
B3
TS 31
B4
B5
B6
B7
B8
TS 0
B1
TS 1
13.2 Transmit H-MVIP Link Timing
The timing relationship of the transmit data clock (TMV8DC), frame pulse clock
(TMV8FPC), data (TD[n]) and frame pulse (TFP8B) signals of a link configured
for 8.192 Mbps H-MVIP operation with a type 0 frame pulse is shown in Figure
25. The falling edges of each TMV8FPC are aligned to a falling edge of the
corresponding TMV8DC for 8.192 Mbps H-MVIP operation. The FREEDM32P256 samples TFP8B low on the falling edge of TMV8FPC and references
this point as the start of the next frame. The FREEDM-32P256 updates the data
provided on TD[n] on every second falling edge of TMV8DC as indicated for bit 2
(B2) of time-slot 0 (TS 0) in Figure 25. The first bit of the next frame is updated
on TD[n] on the falling TMV8DC clock edge for which TFP8B is also sampled
low. B1 is the most significant bit and B8 is the least significant bit of each octet.
Time-slots that are not provisioned to belong to any channel (PROV bit in the
corresponding word of the transmit channel provision RAM in the TCAS256
block set low) transmits the contents of the Idle Fill Time-slot Data register.
Figure 25 – Transmit 8.192 Mbps H-MVIP Link Timing
TM V8DC
(16 M Hz)
TM V8F PC
(4 MHz)
TF P8B
TD[n]
B8
TS 127
B1
B2
B3
B4
B5
B6
B7
TS 0
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B8
B1
TS 1
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The timing relationship of the transmit data clock (TMVCK[n]), data (TD[m],
where 8n£m£8n+7) and frame pulse (TFPB[n]) signals of a link configured for
2.048 Mbps H-MVIP operation with a type 0 frame pulse is shown in Figure 26.
The FREEDM-32P256 samples TFPB[n] low on the falling edge of the
corresponding TMVCK[n] and references this point as the start of the next frame.
The FREEDM-32P256 updates the data provided on TD[m] on every second
falling edge of the corresponding TMVCK[n] as indicated for bit 2 (B2) of timeslot 0 (TS 0) in Figure 26. The first bit of the next frame is updated on TD[n] on
the falling TMVCK[n] clock edge for which TFPB[n] is also sampled low. B1 is
the most significant bit and B8 is the least significant bit of each octet. Timeslots that are not provisioned to belong to any channel (PROV bit in the
corresponding word of the transmit channel provision RAM in the TCAS256
block set low) transmits the contents of the Idle Fill Time-slot Data register.
Figure 26 – Transmit 2.048 Mbps H-MVIP Link Timing
TM VC K[n]
(4 MHz)
TFPB[n]
TD[m ]
B8
B1
B2
TS 31
B3
B4
B5
B6
B7
TS 0
B8
B1
TS 1
13.3 Receive non H-MVIP Link Timing
The timing relationship of the receive clock (RCLK[n]) and data (RD[n]) signals of
an unchannelised link is shown in Figure 27. The receive data is viewed as a
contiguous serial stream. There is no concept of time-slots in an unchannelised
link. Every eight bits are grouped together into a byte with arbitrary alignment.
The first bit received (B1 in Figure 27) is deemed the most significant bit of an
octet. The last bit received (B8) is deemed the least significant bit. Bits that are
to be processed by the FREEDM-32P256 are clocked in on the rising edge of
RCLK[n]. Bits that should be ignored (X in Figure 27) are squelched by holding
RCLK[n] quiescent. In Figure 27, the quiescent period is shown to be a low level
on RCLK[n]. A high level, effected by extending the high phase of the previous
valid bit, is also acceptable. Selection of bits for processing is arbitrary and is
not subject to any byte alignment nor frame boundary considerations.
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Figure 27 – Unchannelised Receive Link Timing
RCLK[n]
RD[n]
B1 B2 B3 B4 X B5 X X X B6 B7 B8 B1 X
The timing relationship of the receive clock (RCLK[n]) and data (RD[n]) signals of
a channelised T1/J1 link is shown in Figure 28. The receive data stream is a
T1/J1 frame with a single framing bit (F in Figure 28) followed by octet bound
time-slots 1 to 24. RCLK[n] is held quiescent during the framing bit. The RD[n]
data bit (B1 of TS1) clocked in by the first rising edge of RCLK[n] after the
framing bit is the most significant bit of time-slot 1. The RD[n] bit (B8 of TS24)
clocked in by the last rising edge of RCLK[n] before the framing bit is the least
significant bit of time-slot 24. In Figure 28, the quiescent period is shown to be a
low level on RCLK[n]. A high level, effected by extending the high phase of bit
B8 of time-slot TS24, is equally acceptable. In channelised T1/J1 mode,
RCLK[n] can only be gapped during the framing bit. It must be active
continuously at 1.544 MHz during all time-slot bits. Time-slots can be ignored by
setting the PROV bit in the corresponding word of the receive channel provision
RAM in the RCAS256 block to low.
Figure 28 – Channelised T1/J1 Receive Link Timing
RCLK[n]
RD[n]
B7 B8 F B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3
TS 24
TS 1
TS 2
The timing relationship of the receive clock (RCLK[n]) and data (RD[n]) signals of
a channelised E1 link is shown in Figure 29. The receive data stream is an E1
frame with a singe framing byte (F1 to F8 in Figure 29) followed by octet bound
time-slots 1 to 31. RCLK[n] is held quiescent during the framing byte. The RD[n]
data bit (B1 of TS1) clocked in by the first rising edge of RCLK[n] after the
framing byte is the most significant bit of time-slot 1. The RD[n] bit (B8 of TS31)
clocked in by the last rising edge of RLCLK[n] before the framing byte is the least
significant bit of time-slot 31. In Figure 29, the quiescent period is shown to be a
low level on RCLK[n]. A high level, effected by extending the high phase of bit
B8 of time-slot TS31, is equally acceptable. In channelised E1 mode, RCLK[n]
can only be gapped during the framing byte. It must be active continuously at
2.048 MHz during all time-slot bits. Time-slots can be ignored by setting the
PROV bit in the corresponding word of the receive channel provision RAM in the
RCAS256 block to low.
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Figure 29 – Channelised E1 Receive Link Timing
RCLK[n]
RD[n]
B6 B7 B8 F1 F2 F3 F4 F5 F6 F7 F8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4
TS 31
FAS / NFAS
TS 1
TS 2
13.4 Transmit non H-MVIP Link Timing
The timing relationship of the transmit clock (TCLK[n]) and data (TD[n]) signals
of a unchannelised link is shown in Figure 30. The transmit data is viewed as a
contiguous serial stream. There is no concept of time-slots in an unchannelised
link. Every eight bits are grouped together into a byte with arbitrary byte
alignment. Octet data is transmitted from most significant bit (B1 in Figure 30)
and ending with the least significant bit (B8 in Figure 30). Bits are updated on
the falling edge of TCLK[n]. A transmit link may be stalled by holding the
corresponding TCLK[n] quiescent. In Figure 30, bits B5 and B2 are shown to be
stalled for one cycle while bit B6 is shown to be stalled for three cycles. In Figure
30, the quiescent period is shown to be a low level on TCLK[n]. A high level,
effected by extending the high phase of the previous valid bit, is also acceptable.
Gapping of TCLK[n] can occur arbitrarily without regard to byte nor frame
boundaries.
Figure 30 – Unchannelised Transmit Link Timing
TCLK[n]
TD[n]
B1 B2 B3 B4
B5
B6
B7 B8 B1
B2
The timing relationship of the transmit clock (TCLK[n]) and data (TD[n]) signals
of a channelised T1/J1 link is shown in Figure 31. The transmit data stream is a
T1/J1 frame with a single framing bit (F in Figure 31) followed by octet bound
time-slots 1 to 24. TCLK[n] is held quiescent during the framing bit. The most
significant bit of each time-slot is transmitted first (B1 in Figure 31). The least
significant bit of each time-slot is transmitted last (B8 in Figure 31). The TD[n] bit
(B8 of TS24) before the framing bit is the least significant bit of time-slot 24. In
Figure 31, the quiescent period is shown to be a low level on TCLK[n]. A high
level, effected by extending the high phase of bit B8 of time-slot TS24, is equally
acceptable. In channelised T1/J1 mode, TCLK[n] can only be gapped during the
framing bit. It must be active continuously at 1.544 MHz during all time-slot bits.
Time-slots that are not provisioned to belong to any channel (PROV bit in the
corresponding word of the transmit channel provision RAM in the TCAS256
block set low) transmit the contents of the Idle Fill Time-slot Data register.
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Figure 31 – Channelised T1/J1 Transmit Link Timing
TCLK[n]
TD[n]
B7 B8
TS 24
B1
F
B2 B3 B4 B5 B6 B7 B8 B1 B2 B3
TS 1
TS 2
The timing relationship of the transmit clock (TCLK[n]) and data (TD[n]) signals
of a channelised E1 link is shown in Figure 32. The transmit data stream is an
E1 frame with a singe framing byte (FAS/NFAS in Figure 32) followed by octet
bound time-slots 1 to 31. TCLK[n] is held quiescent during the framing byte.
The most significant bit of each time-slot is transmitted first (B1 in Figure 32).
The least significant bit of each time-slot is transmitted last (B8 in Figure 32).
The TD[n] bit (B8 of TS31) before the framing byte is the least significant bit of
time-slot 31. In Figure 32, the quiescent period is shown to be a low level on
TCLK[n]. A high level, effected by extending the high phase of bit B8 of time-slot
31, is equally acceptable. In channelised E1 mode, TCLK[n] can only be gapped
during the framing byte. It must be active continuously at 2.048 MHz during all
time-slot bits. Time-slots that are not provisioned to belong to any channel
(PROV bit in the corresponding word of the transmit channel provision RAM in
the TCAS256 block set low) transmit the contents of the Idle Time-slot Fill Data
register.
Figure 32 – Channelised E1 Transmit Link Timing
TCLK[n]
TD[n]
B6 B7 B8
TS 31
B1
FAS / NFAS
B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4
TS 2
TS 1
13.5 PCI Interface
A PCI burst read cycle is shown In Figure 33. The cycle is valid for target and
initiator accesses. The target is responsible for incrementing the address during
the data burst. The 'T' symbol stands for a turn around cycle. A turn around
cycle is required on all signals which can be driven by more than one agent.
During Clock 1, the initiator drives FRAMEB to indicate the start of a cycle. It
also drives the address onto the AD[31:0] bus and drives the C/BEB[3:0] lines
with the read command. In the example below, the command would indicate a
burst read. The IRDYB, TRDYB and DEVSELB signals are in turnaround mode
(i.e. no agent is driving the signals for this clock cycle). This cycle on the PCI
bus is called the address phase.
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During Clock 2, the initiator ceases to drive the AD[31:0] bus in order that the
target can drive it in the next cycle. The initiator also drives the C/BEB[3:0] lines
with the byte enables for the read data. IRDYB is driven active by the initiator to
indicate it is ready to accept the data transfer. All subsequent cycles on the PCI
bus are called data phases.
During Clock 3, the target claims the transaction by driving DEVSELB active. It
also places the first data word onto the AD[31:0] bus and drives TRDYB to
indicate to the initiator that the data is valid.
During Clock 4, the initiator latches in the first data word. The target negates
TRDYB to indicate to the initiator that it is not ready to transfer another data
word.
During Clock 5, the target places the second data word onto the AD[31:0] bus
and drives TRDYB to indicate to the initiator that the data is valid.
During Clock 6, the initiator latches the second data word and negates IRDYB to
indicate to the target that it is not ready for the next transfer. The target shall
drive the third data word until the initiator accepts it.
During Clock 7, the initiator asserts IRDYB to indicate to the target it is ready for
the third data word. It also negates FRAMEB since this shall be the last transfer.
During Clock 8, the initiator latches in the last word and negates IRDYB. The
target, having seen FRAMEB negated in the last clock cycle, negates TRDYB
and DEVSELB. All of the above signals shall be driven to their inactive state in
this clock cycle, except for FRAMEB which shall be tristated. The target shall
stop driving the AD[31:0] bus and the initiator shall stop driving the C/BEB[3:0]
bus; this shall be the turnaround cycle for these signals.
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Figure 33 – PCI Read Cycle
1
2
3
4
5
6
7
8
9
PCICLK
T
FRAMEB
AD[31:0]
Address
T
C/BEB[3:0]
Bus Cmd
Byte Enable
IRDYB
TRDYB
DEVSELB
Data 1
Data 3
T
Byte Enable
T
Data 2
Byte Enable
T
T
T
A PCI burst write transaction is shown in Figure 34. The cycle is valid for target
and initiator accesses. The target is responsible for incrementing the address for
the duration of the data burst. The 'T' symbol stands for a turn around cycle. A
turn around cycle is required on all signals which can be driven by more than one
agent.
During clock 1, the initiator drives FRAMEB to indicate the start of a cycle. It also
drives the address onto the AD[31:0] bus and drives the C/BEB[3:0] lines with
the write command (in the above example the command would indicate a burst
write). The IRDYB, TRDYB and DEVSELB signals are in turnaround mode (no
agent is driving the signals for this clock cycle). This cycle on the PCI bus is
called the address phase.
During clock 2, the initiator ceases to drive the address onto the AD[31:0] bus
and starts driving the first data word. The initiator also drives the C/BEB[3:0]
lines with the byte enables for the write data. IRDYB is driven active by the
initiator to indicate it is ready to accept the data transfer. The target claims the
transaction by driving DEVSELB active and drives TRDYB to indicate to the
initiator that it is ready to accept the data. All subsequent cycles on the PCI bus
are called data phases.
During clock 3, the target latches in the first data word. The initiator starts to
drive the next data word onto the AD[31:0] lines.
During clock 4, the target latches in the second data word. Both the initiator and
the target indicate that they are not ready to transfer any more data by negating
the ready lines.
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During clock 5, the initiator is ready to transfer the next data word so it drives the
AD[31:0] lines with the third data word and asserts IRDYB. The initiator negates
FRAMEB since this is the last data phase of this cycle. The target is still not
ready so a wait state shall be added.
During clock 6, the target is still not ready so another wait state is added.
During clock 7, the target asserts TRDYB to indicate that it is ready to complete
the transfer.
During clock 8, the target latches in the last word and negates TRDYB and
DEVSELB, having seen FRAMEB negated previously. The initiator negates
IRDYB. All of the above signals shall be driven to their inactive state in this clock
cycle except for FRAMEB which shall be tristated.
Figure 34 – PCI Write Cycle
1
2
3
4
5
6
7
8
9
PCICLK
T
FRAMEB
AD[31:0]
C/BEB[3:0]
IRDYB
TRDYB
DEVSELB
Address Data 1
Data 2
Bus Cmd Byte En Byte En
T
Data 3
T
Byte Enable
T
T
T
The PCI Target Disconnect (Figure 35) illustrates the case when the target wants
to prematurely terminate the current cycle. Note, when the FREEDM-32P256 is
the target, it never prematurely terminates the current cycle.
A target can terminate the current cycle by asserting the STOPB signal to the
initiator. Whether data is transferred or not depends on the state of the ready
signals at the time that the target disconnects. If the FREEDM-32P256 is the
initiator and the target terminates the current access, the FREEDM-32P256 will
retry the access after two PCI bus cycles.
During clock 1, an access is in progress.
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During clock 2, the target indicates that it wishes to disconnect by asserting
STOPB. Data may be transferred depending on the state of the ready lines.
During clock 3, the initiator negates FRAMEB to signal the end of the cycle.
During clock 4, the target negates STOPB and DEVSELB in response to the
FRAMEB signal being negated.
Figure 35 – PCI Target Disconnect
1
2
3
4
5
6
PCICLK
FRAMEB
T
STOPB
DEVSELB
The PCI Target Abort Diagram (Figure 36) illustrates the case when the target
wants to abort the current cycle. Note, when the FREEDM-32P256 is the target,
it never aborts the current cycle. A target abort is an indication of a serious error
and no data is transferred.
A target can terminate the current cycle by asserting STOPB and negating
DEVSELB. If the FREEDM-32P256 is the initiator and the target aborts the
current access, the abort condition is reported to the PCI Host.
During clock 1, a cycle is in progress.
During clock 2, the target negates DEVSELB and TRDYB and asserts STOPB to
indicate an abort condition to the initiator.
During clock 3, the initiator negates FRAMEB in response to the abort request.
During clock 4, the target negates STOPB signal in response to the FRAMEB
signal being negated.
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Figure 36 – PCI Target Abort
1
2
3
4
5
6
PCICLK
T
FRAMEB
TRDYB
STOPB
DEVSELB
The PCI Bus Request Cycle Diagram (Figure 37) illustrates the case when the
initiator is requesting the bus from the bus arbiter.
When the FREEDM-32P256 is the initiator, it requests the PCI bus by asserting
its REQB output to the central arbiter. The arbiter grants the bus to the
FREEDM-32P256 by asserting the GNTB line. The FREEDM-32P256 will wait
till both the FRAMEB and IRDYB lines are idle before starting its access on the
PCI bus. The arbiter can remove the GNTB signal at any time, but the
FREEDM-32P256 will complete the current transfer before relinquishing the bus.
Figure 37 – PCI Bus Request Cycle
1
2
3
4
5
6
PCICLK
REQB
GNTB
FRAMEB
T
The PCI Initiator Abort Termination Diagram (Figure 38) illustrates the case when
the initiator aborts a transaction on the PCI bus.
An initiator may terminate a cycle if no target claims it within five clock cycles. A
target may not have responded because it was incapable of dealing with the
request or a bad address was generated by the initiator. IRDYB must be valid
one clock after FRAMEB is deasserted as in a normal cycle. When the
FREEDM-32P256 is the initiator and aborts the transaction, it reports the error
condition to the PCI Host.
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Figure 38 – PCI Initiator Abort Termination
1
2
3
4
5
6
7
PCICLK
T
FRAMEB
TRDYB
IRDYB
DEVSELB
T
T
T
The PCI Exclusive Lock Cycle Diagram (Figure 39) illustrates the case when the
current initiator locks the PCI bus. The FREEDM-32P256 will never initiate an
lock, but will behave appropriately when acting as a target.
During clock 1, the present initiator has gained access of the LOCKB signal and
the PCI bus. The first cycle of a locked access must be a read cycle. The
initiator asserts FRAMEB and drives the address of the target on the AD[31:0]
lines.
During clock 2, the present initiator asserts LOCKB to indicate to the target that a
locked cycle is in progress.
During clock 3, the target samples the asserted LOCKB signal and marks itself
locked. The data cycle has to complete in order for the lock to be maintained. If
for some reason the cycle was aborted, the initiator must negate LOCKB.
During clock 4, the data transfer completes and the target is locked.
During clock 6, another initiator may use the PCI bus but it cannot use the
LOCKB signal. If the other initiator attempts to access the locked target that it
did not lock, the target would reject the access.
During clock 7, the same initiator that locked this target accesses the target. The
initiator asserts FRAMEB and negates LOCKB to re-establish the lock.
During clock 8, the target samples LOCKB deasserted and locks itself.
During clock 9, the initiator does not want to continue the lock so it negates
LOCKB. The target samples LOCKB and FRAMEB deasserted it removes its
lock.
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Figure 39 – PCI Exclusive Lock Cycle
1
2
3
4
5
6
7
8
9
PCICLK
T
FRAMEB
AD[31:0]
LOCKB
IRDYB
TRDYB
DEVSELB
Address
Data
T
T
Address
Data
T
T
T
T
T
T
T
T
Fast back-to-back transactions are used by an initiator to conduct two
consecutive transactions on the PCI bus without the required idle cycle between
them. This can only occur if there is a guarantee that there will be no contention
between the initiator or targets involved in the two transactions. In the first case,
an initiator may perform fast back-to-back transactions if the first transaction is a
write and the second transaction is to the same target. All targets must be able
to decode the above transaction. In the second case, all of the targets on the
PCI bus support fast back-to-back transactions, as indicated in the PCI Status
configuration register. The FREEDM-32P256 only supports the first type of fast
back-to-back transactions and is shown in Figure 40.
During clock 1, the initiator drives FRAMEB to indicate the start of a cycle. It also
drives the address onto the AD[31:0] bus and drives the C/BEB[3:0] lines with
the write command. In this example the command would indicate a single write.
The IRDYB, TRDYB and DEVSELB signals are in turnaround mode and are not
being driven for this clock cycle. This cycle on the PCI bus is called the address
phase.
During clock 2, the initiator ceases to drive the address onto the AD[31:0] bus
and starts driving the data element. The initiator also drives the C/BEB[3:0] lines
with the byte enables for the write data. IRDYB is driven active by the initiator to
indicate that the data is valid.
The initiator negates FRAMEB since this the last data phase of this cycle. The
target claims the transaction by driving DEVSELB active and drives TRDYB to
indicate to the initiator that it is ready to accept the data.
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During clock 3, the target latches in the data element and negates TRDYB and
DEVSELB, having seen FRAMEB negated previously. The initiator negates
IRDYB and drives FRAMEB to start the next cycle. It also drives the address
onto the AD[31:0] bus and drives the C/BEB[3:0] lines with the write command.
In this example the command would indicate a burst write.
During clock 4, the initiator ceases to drive the address onto the AD[31:0] bus
and starts driving the first data element. The initiator also drives the C/BEB[3:0]
lines with the byte enables for the write data. IRDYB is driven active by the
initiator to indicate that the data is valid. The target claims the transaction by
driving DEVSELB active and drives TRDYB to indicate to the initiator that it is
ready to accept the data.
During clock 5, the initiator is ready to transfer the next data element so it drives
the AD[31:0] lines with the second data element. The initiator negates FRAMEB
since this is the last data phase of this cycle. The target accepts the first data
element and negates TRDYB to indicate its is not ready for the next data
element.
During clock 6, the target is still not ready so a wait state shall be added.
During clock 7, the target asserts TRDYB to indicate that it is ready to complete
the transfer.
During clock 8, the target latches in the last element and negates TRDYB and
DEVSELB, having seen FRAMEB negated previously. The initiator negates
IRDYB. All of the above signals shall be driven to their inactive state in this clock
cycle, except for FRAMEB which shall be tristated. The target stops driving the
AD[31:0] bus and the initiator stops driving the C/BEB[3:0] bus. This shall be the
turnaround cycle for these signals.
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Figure 40 – PCI Fast Back to Back
1
2
3
4
5
6
7
8
9
PCICLK
T
FRAMEB
AD[31:0]
C/BEB[3:0]
Address
Data
Data
Address
Bus Cmd Byte En Bus Cmd
T
Data
T
Byte Enable
T
IRDYB
T
TRDYB
T
DEVSELB
13.6 BERT Interface
The timing relationship between the receive link clock and data (RCLK[n] /
RD[n]) and the receive BERT port signals (RBCLK / RBD) is shown in Figure 41.
BERT is not supported for H-MVIP links. For non H-MVIP links, the selected
RCLK[n] is placed on RBCLK after an asynchronous delay. The selected receive
link data (RD[n]) is sampled on the rising edge of the associated RCLK[n] and
transferred to RBD on the falling edge of RBCLK.
Figure 41 – Receive BERT Port Timing
RCLK[n]
RD[n]
B1 B2 B3 B4 X B5 X X
X B6 B7 B8 B1 X
RBCLK
RBD
B1 B2 B3
B4
B5
B6 B7 B8
B1
The timing relationship between the transmit link clock and data (TCLK[n] /
TD[n]) and the transmit BERT port signals (TBCLK / TBD) is shown in Figure 42.
BERT is not supported for H-MVIP links. TCLK[n] is shown to have an arbitrary
gapping. When TCLK[n] is quiescent, TBD is ignored (X in Figure 42). The
selected TCLK[n] is buffered and placed on TBCLK. The transmit BERT data
(TBD) is sampled on the rising edge of the TBCLK and transferred to the
selected TD[n] on the falling edge of TCLK[n].
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Figure 42 – Transmit BERT Port Timing
TCLK[n]
TBCLK
TBD
TD[n]
B1 B2 B3 B4 X B5 X X X B6 B7 B8 B1 X B2
B1 B2 B3
B4
B5
B6 B7 B8
B1
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ABSOLUTE MAXIMUM RATINGS
Maximum rating are the worst case limits that the device can withstand without
sustaining permanent damage. They are not indicative of normal operating
conditions.
Table 33 – FREEDM-32P256 Absolute Maximum Ratings
Case Temperature under Bias
-40°C to +85°C
Storage Temperature
-40°C to +125°C
Supply Voltage (+3.3 Volt VDD3.3)
-0.3V to +4.6V
Supply Voltage (+2.5 Volt VDD2.5)
-0.3V to +3.5V
Voltage on Any non-PCI Pin
-0.3V to +6.0V
Voltage on Any PCI Pin
-0.5V to VDD3.3 + 0.5V
Static Discharge Voltage
±1000 V
Latch-Up Current
±100 mA
DC Input Current
±20 mA
Lead Temperature
+230°C
Absolute Maximum Junction
Temperature
+150°C
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D.C. CHARACTERISTICS
(TA = -40°C to +85°C, VDD3.3 = 3.0 V to 3.6 V, VDD2.5 = 2.3 V to 2.7V)
Table 34 – FREEDM-32P256 D.C. Characteristics
Symbol
Parameter
Min
Typ
Max
Units
VDD3.3
3.3V Power Supply
3.0
3.3
3.6
Volts
Note 4.
VDD2.5
2.5V Power Supply
2.3
2.5
2.7
Volts
Note 4.
VIL
PCI Input Low
Voltage (Bidirs)
-0.5
0.8
Volts
Guaranteed Input LOW
Voltage for PCI bidirs.
VIL
PCI Input Low
Voltage (Inputs)
-0.5
0.6
Volts
Guaranteed Input LOW
Voltage for PCI inputs
(PCICLK, IDSEL, LOCKB,
GNTB, M66EN).
VIH
PCI Input High
Voltage
0.5 *
VDD3.3
VDD3.3
+ 0.5
Volts
Guaranteed Input HIGH
Voltage for PCI
inputs/bidirs.
VOL
Output or Bidirectional Low
Voltage
0.4
Volts
IOL = -4 mA for all outputs
except TBCLK, RBCLK,
RBD, PCICLKO, where
IOL = -8 mA. Note 3.
VOH
Output or Bidirectional High
Voltage
2.4
Volts
IOH = 4 mA for all outputs
except TBCLK, RBCLK,
RBD, PCICLKO, where
IOH = 8 mA. Note 3.
VT+
Schmitt Triggered
Input High Voltage
2.0
5.5
Volts
VT-
Schmitt Triggered
Input Low Voltage
-0.2
0.6
Volts
IILPU
Input Low Current
+10
45
+100
µA
VIL = GND, Notes 1, 3, 4.
IIHPU
Input High Current
-10
0
+10
µA
VIH = VDD, Notes 1, 3
IIL
Input Low Current
-10
0
+10
µA
VIL = GND, Notes 2, 3
IIH
Input High Current
-10
0
+10
µA
VIH = VDD, Notes 2, 3
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Symbol
ISSUE 3
Parameter
FRAME ENGINE AND DATA LINK MANAGER 32P256
Min
Typ
Max
Units
Conditions
CIN
Input Capacitance
5
pF
Excludes package.
Package typically 2 pF.
Note 4.
COUT
Output
Capacitance
5
pF
All pins. Excludes
package. Package typically
2 pF. Note 4.
CIO
Bi-directional
Capacitance
5
pF
All pins. Excludes
package. Package typically
2 pF. Note 4.
LPIN
Pin Inductance
2
nH
All pins. Note 4.
IDDOP
Operating Current.
245
mA
VDD2.5 = 2.7V, Outputs
Unloaded. RCLK[31:0] =
TCLK[31:0] = 2.048 MHz.
RMVCK[3:0], TMVCK[3:0],
RMV8DC and TMV8DC
tied low. Note 4.
IDDOP
Operating Current.
330
mA
VDD2.5 = 2.7V, Outputs
Unloaded. RCLK[2:0] =
TCLK[2:0] = 51.84 MHz.
RCLK[31:3], TCLK[31:3],
RMVCK[3:0], TMVCK[3:0],
RMV8DC and TMV8DC
tied low. Note 4.
Notes on D.C. Characteristics:
1. Input pin or bi-directional pin with internal pull-up resistor.
2. Input pin or bi-directional pin without internal pull-up resistor.
3. Negative currents flow into the device (sinking), positive currents flow out of
the device (sourcing).
4. Typical values are given as a design aid. The product is not tested to the
typical values given in the data sheet.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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RELEASED
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16
ISSUE 3
FRAME ENGINE AND DATA LINK MANAGER 32P256
FREEDM-32P256 TIMING CHARACTERISTICS
(TA = -40°C to +85°C, VDD3.3 = 3.0 V to 3.6 V, VDD2.5 = 2.3 V to 2.7V)
Table 35 – FREEDM-32P256 Link Input (Figure 43 to Figure 46)
Symbol
Description
Min
Max
Units
RCLK[31:0] Frequency (See Note 3)
1.542
1.546
MHz
RCLK[31:0] Frequency (See Note 4)
2.046
2.050
MHz
RCLK[2:0] Frequency (See Note 5)
51.84
MHz
RCLK[31:3] Frequency (See Note 5)
10
MHz
RCLK[31:0] Duty Cycle
40
60
%
RMVCK[3:0] Frequency (See Note 6)
4.092
4.100
MHz
RMVCK[3:0] Duty Cycle
40
60
%
RMV8DC Frequency (See Note 7)
16.368
16.400
MHz
RMV8DC Duty Cycle
40
60
%
RMV8FPC Frequency (See Note 8)
4.092
4.100
MHz
RMV8FPC Duty Cycle
40
60
%
RMV8DC to RMV8FPC skew
-10
10
ns
SYSCLK Frequency
†
45
MHz
SYSCLK Duty Cycle
40
60
%
tSRD
RD[2:0] Set-Up Time
1
ns
tHRD
RD[2:0] Hold Time
2
ns
tSRD
RD[31:3] Set-Up Time
5
ns
tHRD
RD[31:3] Hold Time
5
ns
tSRD_2MVIP
RD[31:0] Set-Up Time (2.048 Mbps HMVIP Mode)
5
ns
tHRD_2MVIP
RD[31:0] Hold Time (2.048 Mbps HMVIP Mode)
5
ns
tSRD_8MVIP
RD[31:0] Set-Up Time (8.192 Mbps HMVIP Mode)
5
ns
tPMVC
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FRAME ENGINE AND DATA LINK MANAGER 32P256
Symbol
Description
Min
Max
Units
tHRD_8MVIP
RD[31:0] Hold Time (8.192 Mbps HMVIP Mode)
5
ns
tSRFPB
RFPB[3:0] Set-Up Time
50
ns
tHRFPB
RFPB[3:0] Hold Time
50
ns
TSRFP8B
RFP8B Set-Up Time
50
ns
THRFP8B
RFP8B Hold Time
50
ns
tSTBD
TBD Set-Up Time (See Note 9)
15
ns
tHTBD
TBD Hold Time
0
ns
† The minimum SYSCLK frequency is one half of PCICLK freqency or 25MHz,
whichever is the greater.
Notes on Input Timing:
1. When a set-up time is specified between an input and a clock, the set-up time is the
time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the
clock.
2. When a hold time is specified between an input and a clock, the hold time is the
time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the
input.
3. Applicable only to channelised T1/J1 links and measured between framing bits.
4. Applicable only to channelised E1 links and measured between framing bytes.
5. Applicable only to unchannelised links of any format and measured between any
two RCLK rising edges.
6. Applicable only to 2.048 Mbps H-MVIP links and measured between any two
RMVCK[n] falling edges.
7. Applicable only to 8.192 Mbps H-MVIP links and measured between any two
RMV8DC falling edges.
8. Applicable only to H-MVIP links and measured between any two RMV8FPC falling
edges.
9. TBD set-up time is measured with a 20 pF load on TBCLK. The set-up time
increases by typically 1 ns for each 10 pF of extra load on TBCLK.
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FRAME ENGINE AND DATA LINK MANAGER 32P256
Figure 43 – Receive Data & Frame Pulse Timing (2.048 Mbps H-MVIP Mode)
RMVCK[n]
tS RFPB
tH RFPB
RFPB[n]
tS RD _2MV IP
tH RD_2MVIP
RD[m]
(m =8n,8n+1...8n+7)
Figure 44 – Receive Data & Frame Pulse Timing (8.192 Mbps H-MVIP Mode)
RMV8FPC
tS RFP8B
tH RFP8B
RFP8B
tP MVC
RMV8DC
tS RD_8MV IP
tH RD_8MVIP
RD[n]
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Figure 45 – Receive Data Timing (Non H-MVIP Mode)
RCLK[n]
tS RD
tH RD
RD[n]
Figure 46 – BERT Input Timing
TBCLK
tS TBD
tH TBD
TBD
Table 36 – FREEDM-32P256 Link Output (Figure 47 to Figure 50)
Symbol
Description
Min
Max
Units
TCLK[31:0] Frequency (See Note 4)
1.542
1.546
MHz
TCLK[31:0] Frequency (See Note 5)
2.046
2.050
MHz
TCLK[2:0] Frequency (See Note 6)
51.84
MHz
TCLK[31:3] Frequency (See Note 6)
10
MHz
TCLK[31:0] Duty Cycle
40
60
%
TMVCK[3:0] Frequency (See Note 7)
4.092
4.100
MHz
TMVCK[3:0] Duty Cycle
40
60
%
TMV8DC Frequency (See Note 8)
16.368
16.400
MHz
TMV8DC Duty Cycle
40
60
%
TMV8FPC Frequency (See Note 9)
4.092
4.100
MHz
TMV8FPC Duty Cycle
40
60
%
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
309
PM7382 FREEDM-32P256
RELEASED
DATA SHEET
PMC-2010333
ISSUE 3
FRAME ENGINE AND DATA LINK MANAGER 32P256
Symbol
Description
Min
Max
Units
tPMVC
TMV8DC to TMV8FPC skew
-10
10
ns
tSTFPB
TFPB[3:0] Set-Up Time
50
ns
tHTFPB
TFPB[3:0] Hold Time
50
ns
TSTFP8B
TFP8B Set-Up Time
50
ns
THTF8PB
TFP8B Hold Time
50
ns
tPTD
TCLK[2:0] Low to TD[2:0] Valid
3
12
ns
tPTD
TCLK[31:3] Low to TD[31:3] Valid
4
25
ns
tPTD_2MVIP TMVCK[3:0] Low to TD[31:0] Valid
(2.048 Mbps H-MVIP Mode)
4
25
ns
tPTD_8MVIP TMV8DC Low to TD[31:0] Valid
(8.192 Mbps H-MVIP Mode)
4
25
ns
tPRBD
-5
5
ns
RBCLK Low to RBD Valid
Notes on Output Timing:
1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of
the reference signal to the 1.4 Volt point of the output.
2. Maximum and minimum output propagation delays are measured with a 50 pF load
on all the outputs, except for the TD[2:0] outputs, which are measured with a 20pF
load, and the PCI outputs/bidirs, which are measured with a 10pF load. Maximum
propagation delay for TD[2:0] increases by typically 1 ns for each 10 pF of extra
load.
3. Output propagation delays of signal outputs that are specified in relation to a
reference output are measured with a 50 pF load on both the signal output and the
reference output.
4. Applicable only to channelised T1/J1 links and measured between framing bits.
5. Applicable only to channelised E1 links and measured between framing bytes.
6. Applicable only to unchannelised links of any format and measured between any
two TCLK rising edges.
7. Applicable only to 2.048 Mbps H-MVIP links and measured between any two
TMVCK[n] falling edges.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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FRAME ENGINE AND DATA LINK MANAGER 32P256
8. Applicable only to 8.192 Mbps H-MVIP links and measured between any two
TMV8DC falling edges.
9. Applicable only to H-MVIP links and measured between any two TMV8FPC falling
edges.
10. Output tristate delay is the time in nanoseconds from the 1.4 Volt point of the
reference signal to the point where the total current delivered through the output is
less than or equal to the leakage current.
Figure 47 – Transmit Data & Frame Pulse Timing (2.048 Mbps H-MVIP Mode)
TMVCK[n]
tS T FPB
tH T FPB
TFPB[n]
tP TD_2MVIP
TD[m ]
(m =8n,8n+1...8n+7)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
311
PM7382 FREEDM-32P256
RELEASED
DATA SHEET
PMC-2010333
ISSUE 3
FRAME ENGINE AND DATA LINK MANAGER 32P256
Figure 48 – Transmit Data & Frame Pulse Timing (8.192 Mbps H-MVIP Mode)
TMV8FPC
tS T FP8B
tH T FP 8B
TFP8B
tP MVC
TMV8DC
tP TD_8MVIP
TD[n]
Figure 49 – Transmit Data Timing (Non H-MVIP Mode)
TCLK[n]
tP TD
TD[n]
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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FRAME ENGINE AND DATA LINK MANAGER 32P256
Figure 50 – BERT Output Timing
RBCLK
tP RBD
RBD
Table 37 – PCI Interface (Figure 51)
Symbol
Description
Min
Max
Units
PCICLK Frequency (See Note 1)
25
66
MHz
PCICLK Duty Cycle
40
60
%
tSPCI
All PCI Input and Bi-directional Setup time to PCICLK
4
ns
tHPCI
All PCI Input and Bi-directional Hold
time to PCICLK
0.5
ns
tPPCI
PCICLK to all PCI Outputs Valid
2
tZPCI
PCI Output active from PCICLK to
Tristate
tZNPCI
All PCI Outputs Tristate from
PCICLK to active
8.5
ns
14
ns
2
ns
Notes on PCI Timing:
1. PCICLK cannot change frequency without resetting the FREEDM-32P256
device.
2. The phrase “all PCI Outputs” in the above table excludes PCIINTB and
PCICLKO.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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DATA SHEET
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FRAME ENGINE AND DATA LINK MANAGER 32P256
Figure 51 – PCI Interface Timing
PCICLK
tS
PCI
tH
PCI
PCI INPUT
tP
PCI
PCI OUTPUT
tZ
PCI TRISTATE
OUTPUT
PCI
Data Valid
tZN
PCI
PCI TRISTATE
OUTPUT
Data Valid
Table 38 – JTAG Port Interface (Figure 52)
Symbol
Description
Min
TCK Frequency
Max
Units
1
MHz
60
%
TCK Duty Cycle
40
tSTMS
TMS Set-up time to TCK
50
ns
tHTMS
TMS Hold time to TCK
50
ns
tSTDI
TDI Set-up time to TCK
50
ns
tHTDI
TDI Hold time to TCK
50
ns
tPTDO
TCK Low to TDO Valid
2
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
60
314
ns
PM7382 FREEDM-32P256
RELEASED
DATA SHEET
PMC-2010333
ISSUE 3
FRAME ENGINE AND DATA LINK MANAGER 32P256
Figure 52 – JTAG Port Interface Timing
TCK
tS TMS
tH TMS
tS TDI
tH TDI
TMS
TDI
TCK
tP TDO
TDO
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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RELEASED
DATA SHEET
PMC-2010333
17
ISSUE 3
FRAME ENGINE AND DATA LINK MANAGER 32P256
ORDERING AND THERMAL INFORMATION
Table 39 – FREEDM-32P256 Ordering Information
PART NO.
DESCRIPTION
PM7382-PI
329 Plastic Ball Grid Array (PBGA)
Table 40 – FREEDM-32P256 Thermal Information
PART NO.
AMBIENT TEMPERATURE
Theta Ja
PM7382-PI
-40°C to +85°C
25 °C/W
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
316
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RELEASED
DATA SHEET
PMC-2010333
18
ISSUE 3
FRAME ENGINE AND DATA LINK MANAGER 32P256
MECHANICAL INFORMATION
Figure 53 – 329 Pin Plastic Ball Grid Array (PBGA)
Note – The FREEDM-32P256 is manufactured using the 4-layer variant of the package
shown in the drawing below.
A
0.20 (2X)
D
D1
B
A1 BAL L
CO RNER
A1 BALL
COR N ER
Px
22
23
0.20 (2X)
21
20
18
19
16
14
1 7 15
12
13 11
10
8
9
6
7
4
5
2
3
1
b
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
A1 BAL L
INDICATO R
E1
E
e
V
W
Y
AA
AB
AC
J
45 o CHAMFER
4 PLA CES
"d" DIA .
3 PLA CES
e
I
TO P VIEW
A
Py
BO TT OM VIEW
30 o TYP +/- 1 o
A2
b bb C
aaa
c
C
C
A1
SEATING PLA NE
SID E VIEW
NO TE S: 1) ALL D IM EN SIO NS IN M ILLIM ETER .
2) DIME NSIO N aaa DE NO TE S C O P LA NA RITY.
3) DIME NS IO N bbb DE NO TE S PAR ALLE L.
PACK AGE TYPE : 329 PLASTIC BALL G RID AR RAY - PBG A
BO DY S IZE : 31 x 31 x 2.33 M M (4 layer)
A
A
A1
Min.
2.12
2.12
0.50
Nom
.
Max.
2.33
2.33
0.60
1.17 31.00 26.00 31.00 26.00 1.53
2.54
2.56
0.70
1.22 31.20 26.70 31.20 26.70
Dim .
(2 layer) (4 layer)
A2
D
D1
E
E1
1.12 30.80 25.50 30.80 25.50
c
c
d
e
Px
0.60
-
-
-
-
27.84 27.84
-
1.53
0.76
0.56
0.56
1.0
1.27
27.94 27.94
-
-
0.90
-
-
-
-
I
J
b
-
-
-
(2 layer ) (4 layer)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
317
Py
aaa bbb
28.04 28.04 0.15
0.15
PM7382 FREEDM-32P256
RELEASED
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FRAME ENGINE AND DATA LINK MANAGER 32P256
NOTES:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or
suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility
with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly
disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and
implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement.
In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits,
lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility
of such damage.
The technology discussed is protected by one or more of the following Patents:
U.S. Patent Nos. 5,640,398 and 6,188,699
Can. Patent No. 2,161,921
Relevant patent applications and other patents may also exist.
© 2001 PMC-Sierra, Inc
PMC-Sierra, Inc.
PMC-2010333 (R3)
Issue date: August 2001
8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
PM7382 FREEDM-32P256
RELEASED
DATA SHEET
PMC-2010333
ISSUE 3
FRAME ENGINE AND DATA LINK MANAGER 32P256
CONTACTING PMC-SIERRA, INC.
PMC-Sierra, Inc.
8555 Baxter Place Burnaby, BC
Canada V5A 4V7
Tel:
(604) 415-6000
Fax:
(604) 415-6200
Document Information:
Corporate Information:
Application Information:
Web Site:
[email protected]
[email protected]
[email protected]
http://www.pmc-sierra.com
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or
suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility
with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly
disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and
implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement.
In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits,
lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility
of such damage.
The technology discussed is protected by one or more of the following Patents:
U.S. Patent Nos. 5,640,398 and 6,188,699
Can. Patent No. 2,161,921
Relevant patent applications and other patents may also exist.
© 2001 PMC-Sierra, Inc
PMC-Sierra, Inc.
PMC-2010333 (R3)
Issue date: August 2001
8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000