PM7388 FREEDM 336A1024 Preliminary Frame Engine and Datalink Manager FEATURES configurable on a per multilink bundle. Optionally full packet transfers are supported on a per bundle basis. • Supports up to 168 multilink bundles with up to 12 member links per bundle. These bundles are composed of independent HDLC channels. • Support for up to 100 ms of intra bundle skew in the receive direction when supporting the minimum. fragment size. • Support for PPP header compression as per RFC 1661. • Single-chip multi-channel packet processor supporting line rate throughput transfers of packet sizes from 40 to 9.6 Kbytes, for up to an aggregate of 336 T1s, 252 E1s, or 12 DS-3s. • Provides simultaneous support of PPP, Frame Relay, Multilink-PPP and Multilink-Frame Relay protocols. Alternative protocols supported via HDLC termination and full packet store of the data within the HDLC structure. PPP MULTILINK PPP AND FRAME RELAY BUNDLES • Support for 16 COS levels in accordance with RFC 2686. • Either 12 bit or 24 bit sequence number, with short and long fragment header formats, is supported. • Capable of supporting fragment sizes from 1 to 9.6 Kbytes. • Support for 3 egress fragmentation sizes (128, 256, and 512 bytes) • Link Control protocol packets are identified by the PID as control protocols and will be forwarded to the Any-PHY interface. FRAME RELAY • Link layer address lookup can be performed based on HDLC channel and 10 bit DLCI for HDLC channels supporting Frame Relay protocols. • The lookup algorithm can support a maximum of 16 K connection identifiers (CIs) amongst multilink FR bundles. The connection identifiers are ignored in singlelink FR channels. • Control frames are identified and forwarded to Any-PHY interface. • 12 bit sequence numbers supported. • FECN, BECN, and DE ingress processing as per FRF.12. DDLL140 BCLK AD[31:0] ADSB CSB WR BURSTB BLAST READYB BTERMB WRDONEB INTHIB INTLOB BUSPOL TDO TDI TCK TMS TRSTB DLLTEST SYSCLK TCLK[11:0] TD[11:0] RSTB PMCTEST SCAN_EN BLOCK DIAGRAM JTAG Microprocessor I/F (BUMP2) Tx ANY-PHY I/F (TAPI-12) ACIFP Egress Queue Manager (EQM-12) CIFPOUT ADATA[7:0] ADP APL AV5 Insert SBI (INSBI336) Transmit Channel Assigner (TCAS-12) Tx HDLC Processor / Partial Packet Buffer (THDL-12) Tx Fragment Builder (TFRAG) Performance Monitor (PM-12) CB DRAM Controller (CB_DRAMC) REFCLK DDATA[7:0] DPL DV5 Extract SBI (EXSBI336) Receive Channel Assigner (RCAS-12) DC1FP Frame Builder (FRMBLD) Ingress Queue Manager (EQM-12) RD[11:0] RS DRAM Controller (RS_DRAMC) RCLK[11:0] PMC-1991475 (p2) Rx Fragment Builder (RFRAG) RSDAT[31:0] RSADD[12:0] RSWEB RSCSB RSRASB RSCASB RSBS[1:0] DQM DDP Rx HDLC Processor / Partial Packet Buffer (RHDL-12) CCDAT[35:0] CCADD[17:0] CCWEB CCSELB CCBSELB[1:0] SRAM Controller (SRAMC) AJUST_REQ PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE TXCLK TXADDR[15:0] TPA TXDATA[15:0] TXPRTY TRDY TSX TEOP TMOD TERR Rx ANY-PHY I/F (RAPI-12) CBDAT[47:0] CBADD[12:0] CBWEB CBCSB CBRASB CBCASB CBBS[1:0] RXCLK RXADDR[3:0] RPA RENB RXDATA[15:0] RXPRTY RVAL RSX RSOP REOP RMOD RERR Data Control Copyright PMC-Sierra, Inc. 2001 Preliminary PM7388 FREEDM 336A1024 Frame Engine and Datalink Manager HDLC INTERFACES • Support for up to 1024 bidirectional HDLC channels, with individual HDLC channel speeds ranging from 56 Kbps to 52 Mbps. In a channelized application, the number of time-slots assigned to an HDLC channel is programmable from 1 to 24 (for T1/J1) and from 1 to 31 (for E1). • The 1024 HDLC channels can be assigned to a mixture of physical links via the 77 MHz SBI interface. The SBI transports the equivalent of 12 STS-1 synchronous payload envelopes (SPE). Each STS-1 SPE can be individually configured to carry 28 T1/J1s, 21 E1s or 1 DS3. • For each channel, supports programmable flag sequence detection and generation, bit stuffing and destuffing, and validation and generation of either CRC-CCITT or CRC-32 frame check sequences. • For each channel, the receiver checks for packet abort sequences, octet aligned packet length and for minimum and maximum packet length. • 104 MHz, 8 bit Any-PHY Level 3 or 52 MHz Any-PHY Level 2 packet interface for transfer of packet, frame or fragment data using an external controller. The interface is capable of supporting full datagram transfer on a per Any-PHY channel basis, or fragmented packets or frames on a per Any-PHY channel basis. • A 77 MHz SBI bus supporting up to 336 links. • 12 separate clock and data interfaces to support 12 links of arbitrary data rate up to 52 MHz (eg, DS3/E3). The device can be configured to process data from either the clock and data interfaces or from the SBI on a per clock-data-link/SPE basis. • A 100 MHz, 48-bit SDRAM interface for ingress and egress per packet/fragment storage. • A 100 MHz, 32-bit SDRAM interface for ingress re-sequencing data. structures. • A 100 MHz, 36-bit SSRAM interface for Ingress/Egress Context storage. • Provides a standard 5 signal P1149.1 JTAG test port for boundary scan. • A 32-bit microprocessor interface for configuration and status monitoring. TECHNOLOGIES • 40 mm x 40 mm, 520 pin (1.27 mm pitch) enhanced ball grid array (SBGA) package. • Low power 0.18 mm CMOS technology using 1.8 V core power and 3.3 V I/O. APPLICATIONS • IETF PPP interfaces for routers. • Frame Relay interfaces for ATM or Frame Relay switches and multiplexers. • Internet/Intranet access equipment. TYPICAL APPLICATION OC-48 PORT CARD SOLUTION SBI TelecomBus PM8316 TEMUX-84 SER OC-48 DES PM7388 FREEDM336A1024 PM8316 TEMUX-84 PM7388 FREEDM336A1024 PM8316 TEMUX-84 PM7388 FREEDM336A1024 PM5315 SPECTRA2488 PM8316 TEMUX-84 Head Office: PMC-Sierra, Inc. 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: 604.415.6000 Fax: 604.415.6200 To order documentation, send email to: [email protected] or contact the head office, Attn: Document Coordinator All product documentation is available on our web site at: http://www.pmc-sierra.com For corporate information, send email to: [email protected] PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PM7388 FREEDM336A1024 PMC-1991475 (p2) Copyright PMC-Sierra, Inc. 2001. All rights reserved. August 2001. Any-PHY, SPECTRA-2488, TEMUX84, FREEDM-336A1024,SBI, and PMC-Sierra are trademarks of PMC-Sierra, Inc.