SLRS055 − APRIL 2004
D 500-mA-Rated Collector Current
D
D
D
D
D, N, OR NS PACKAGE
(TOP VIEW)
(Single Output)
High-Voltage Outputs . . . 50 V
Output Clamp Diodes
Inputs Compatible With Various Types of
Logic
Relay-Driver Applications
1B
2B
3B
4B
5B
6B
7B
E
description/ordering information
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
1C
2C
3C
4C
5C
6C
7C
COM
The ULN2004AI is a high-voltage, high-current
Darlington transistor array. This device consists
of seven npn Darlington pairs that feature
high-voltage outputs with common-cathode clamp diodes for switching inductive loads. The collector-current
rating of a single Darlington pair is 500 mA. The Darlington pairs can be paralleled for higher-current capability.
Applications include relay drivers, hammer drivers, lamp drivers, display drivers (LED and gas discharge), line
drivers, and logic buffers.
The ULN2004AI has a 10.5-kΩ series base resistor for each Darlington pair for operation directly with TTL or
5-V CMOS devices.
ORDERING INFORMATION
PDIP (N)
−40°C to 105°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
SOIC (D)
Tube of 25
ULN2004AIN
Tube of 40
ULN2004AID
Reel of 2500
ULN2004AIDR
TOP-SIDE
MARKING
ULN2004AIN
ULN2004AI
SOP (NS)
Reel of 2000
ULN2004AINSR
ULN2004AI
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
!" #!$% &"'
&! #" #" (" " ") !"
&& *+' &! #", &" ""%+ %!&"
", %% #""'
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SLRS055 − APRIL 2004
logic diagram
9
1B
2B
3B
4B
5B
6B
7B
1
16
2
15
3
14
4
13
5
12
6
11
7
10
COM
1C
2C
3C
4C
5C
6C
7C
schematics (each Darlington pair)
COM
Input
B
Output
C
10.5 kΩ
7.2 kΩ
3 kΩ
All resistor values shown are nominal.
2
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• DALLAS, TEXAS 75265
E
SLRS055 − APRIL 2004
absolute maximum ratings at 25°C free-air temperature (unless otherwise noted)†
Collector-emitter voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 V
Clamp diode reverse voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 V
Input voltage, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V
Peak collector current (see Notes 2 and 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA
Output clamp current, IOK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA
Total emitter-terminal current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −2.5 A
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 105°C
Package thermal impedance, θJA (see Notes 2 and 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
Operating virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the emitter/substrate terminal E, unless otherwise noted.
2. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
electrical characteristics, TA = 25°C
PARAMETER
VI(on)
VCE(sat)
On-state input voltage
Collector-emitter saturation voltage
TEST
FIGURE
6
VCE = 2 V
MIN
TYP
MAX
IC = 125 mA
IC = 200 mA
5
IC = 275 mA
IC = 350 mA
7
IC = 100 mA
IC = 200 mA
0.9
1.1
1
1.3
II = 500 µA,
VCE = 50 V,
IC = 350 mA
II = 0
1.2
1.6
1
Clamp forward voltage
8
II
Input current
4
IR
Ci
Clamp reverse current
7
IF = 350 mA
VI = 5 V
1.7
VI = 12 V
VR = 50 V
VI = 0,
POST OFFICE BOX 655303
f = 1 MHz
• DALLAS, TEXAS 75265
V
8
II = 250 µA,
II = 350 µA,
Collector cutoff current
UNIT
6
5
ICEX
VF
Input capacitance
TEST CONDITIONS
50
µA
2
V
0.35
0.5
1
1.45
15
V
mA
50
µA
25
pF
3
SLRS055 − APRIL 2004
electrical characteristics, TA = −40°C to 105°C
TEST
FIGURE
PARAMETER
VI(on)
On-state input voltage
VCE(sat)
ICEX
6
Collector-emitter saturation voltage
Collector cutoff current
VCE = 2 V
MIN
TYP
MAX
IC = 125 mA
IC = 200 mA
5
IC = 275 mA
IC = 350 mA
7
IC = 100 mA
IC = 200 mA
0.9
1.1
1
1.3
IC = 350 mA
II = 0
1.2
1.6
1
II = 500 µA,
VCE = 50 V,
2
VCE = 50 V
II = 0
VI = 1 V
IF = 350 mA
VCE = 50 V,
8
Off-state input current
3
II
Input current
4
IR
Ci
Clamp reverse current
7
µA
500
50
VI = 5 V
VI = 12 V
VR = 50 V
VI = 0,
V
50
100
1.7
IC = 500 µA
V
8
II = 250 µA,
II = 350 µA,
Clamp forward voltage
UNIT
6
5
VF
II(off)
Input capacitance
TEST CONDITIONS
f = 1 MHz
2
V
µA
65
0.35
0.5
1
1.45
mA
100
µA
15
25
pF
TYP
MAX
0.25
1
µs
0.25
1
µs
switching characteristics, TA = 25°C
PARAMETER
tPLH
tPHL
VOH
TEST CONDITIONS
Propagation delay time, low- to high-level output
See Figure 8
Propagation delay time, high- to low-level output
See Figure 8
High-level output voltage after switching
VS = 50 V,
See Figure 9
IO ≈ 300 mA,
MIN
VS − 20
UNIT
mV
switching characteristics, TA = −40°C to 105°C
PARAMETER
tPLH
tPHL
VOH
4
TEST CONDITIONS
Propagation delay time, low- to high-level output
See Figure 8
Propagation delay time, high- to low-level output
See Figure 8
High-level output voltage after switching
VS = 50 V,
See Figure 9
POST OFFICE BOX 655303
IO ≈ 300 mA,
• DALLAS, TEXAS 75265
MIN
VS − 500
TYP
MAX
1
10
UNIT
µs
1
10
µs
mV
SLRS055 − APRIL 2004
PARAMETER MEASUREMENT INFORMATION
Open
Open
VCE
ICEX
VCE
ICEX
Open
VI
Figure 1. ICEX Test Circuit
Open
Figure 2. ICEX Test Circuit
VCE
Open
II(off)
IC
II(on)
Open
VI
Figure 3. II(off) Test Circuit
Figure 4. II Test Circuit
Open
Open
IC
hFE =
II
VCE
II
IC
VI(on)
VCE
IC
NOTE: II is fixed for measuring VCE(sat), variable for
measuring hFE.
Figure 5. hFE, VCE(sat) Test Circuit
Figure 6. VI(on) Test Circuit
VR
IR
VF
Open
IF
Open
Figure 7. IR Test Circuit
POST OFFICE BOX 655303
Figure 8. VF Test Circuit
• DALLAS, TEXAS 75265
5
SLRS055 − APRIL 2004
PARAMETER MEASUREMENT INFORMATION
Input
50%
50%
tPHL
tPLH
50%
Output
50%
VOLTAGE WAVEFORMS
Figure 9. Propagation Delay-Time Waveforms
VS
Input
2 mH
Open
1N3064
200 Ω
Pulse
Generator
(see Note A)
Output
CL = 15 pF
(see Note B)
TEST CIRCUIT
≤5 ns
≤10 ns
90%
1.5 V
Input
10%
VIH
(see Note C)
90%
1.5 V
10%
40 µs
0V
VOH
Output
VOL
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: PRR = 12.5 kHz, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
C. For testing, VIH = 3 V
Figure 10. Latch-Up Test Circuit and Voltage Waveforms
6
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• DALLAS, TEXAS 75265
SLRS055 − APRIL 2004
TYPICAL CHARACTERISTICS
COLLECTOR-EMITTER
SATURATION VOLTAGE
vs
TOTAL COLLECTOR CURRENT
(TWO DARLINGTONS IN PARALLEL)
VCE(sat)
VCE(sat) − Collector-Emitter Saturation Voltage − V
2.5
TA = 25°C
2
II = 250 µA
II = 350 µA
II = 500 µA
1.5
1
0.5
0
0
100
200
300
400
500
600
700
2.5
TA = 25°C
II = 250 µA
2
II = 350 µA
1.5
II = 500 µA
1
0.5
0
0
800
100
200
300
400
500
600
700
800
IC(tot) − Total Collector Current − mA
IC − Collector Current − mA
Figure 12
Figure 11
COLLECTOR CURRENT
vs
INPUT CURRENT
500
RL = 10 Ω
TA = 25°C
450
IC
IC − Collector Current − mA
VCE(sat)
VCE(sat) − Collector-Emitter Saturation Voltage − V
COLLECTOR-EMITTER
SATURATION VOLTAGE
vs
COLLECTOR CURRENT
(ONE DARLINGTON)
400
VS = 10 V
350
VS = 8 V
300
250
200
150
100
50
0
0
25
50
75
100
125
150
175
200
II − Input Current − µA
Figure 13
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• DALLAS, TEXAS 75265
7
SLRS055 − APRIL 2004
APPLICATION INFORMATION
VCC
VCC
1
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
RP
Lamp
Test
TTL
Output
Figure 14. TTL to Load
8
V
V
POST OFFICE BOX 655303
TTL
Output
Figure 15. Use of Pullup Resistors
to Increase Drive Current
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
ULN2004AID
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ULN2004AIDE4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ULN2004AIDR
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ULN2004AIDRE4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ULN2004AIN
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
ULN2004AINE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
ULN2004AINSR
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ULN2004AINSRE4
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
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Addendum-Page 1
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