SN74CB3Q16811 24-BIT SWITCH WITH PRECHARGED OUTPUTS 2.5-V/3.3-V LOW-VOLTAGE FET BUS SWITCH www.ti.com SCDS153B – OCTOBER 2003 – REVISED MARCH 2005 • FEATURES • • • • • • • • • • Member of the Texas Instruments Widebus™ Family SN74CB3Q Bus Switches Are Equivalent to IDTQS3VH Bus Switches 5-V Tolerant I/Os With Device Powered Up or Powered Down Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 5 Ω Typ) Rail-to-Rail Switching on Data I/O Ports – 0- to 5-V Switching With 3.3-V VCC – 0- to 3.3-V Switching With 2.5-V VCC B-Port Outputs Are Precharged by Bias Voltage (BIASV) to Minimize Signal Distortion During Live Insertion and Hot Plugging Supports PCI Hot Plug Bidirectional Data Flow With Near-Zero Propagation Delay Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 4 pF Typ) Fast Switching Frequency (fON = 20 MHz Max) • • • • • • • • Data and Control Inputs Provide Undershoot Clamp Diodes Low Power Consumption (ICC = 0.75 mA Typ) VCC Operating Range From 2.3 V to 3.6 V Data I/Os Support 0- to 5-V Signaling Levels (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V) Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 – 2000-V Human-Body Model (A114-B, Class II) – 1000-V Charged-Device Model (C101) Supports Both Digital and Analog Applications: PCI Hot Plug, Hot Docking, Memory Interleaving, Bus Isolation, and Low-Distortion Signal Gating DESCRIPTION/ORDERING INFORMATION The SN74CB3Q16811 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q16811 provides an optimized interface solution ideally suited for broadband communications, networking, and data-intensive computing systems. ORDERING INFORMATION PACKAGE (1) TA (1) TOP-SIDE MARKING SN74CB3Q16811DL Tape and reel SN74CB3Q16811DLR TSSOP – DGG Tape and reel SN74CB3Q16811DGGR CB3Q16811 TVSOP – DGV Tape and reel SN74CB3Q16811DGVR BW811 SSOP – DL –40°C to 85°C ORDERABLE PART NUMBER Tube CB3Q16811 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DESCRIPTION/ORDERING INFORMATION (CONTINUED) The SN74CB3Q16811 is organized as two 12-bit bus switches with separate output-enable (1OE, 2OE) inputs. It can be used as two 12-bit bus switches or as one 24-bit bus switch. When OE is low, the associated 12-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 12-bit bus switch is OFF, and a high-impedance state exists between the A and B ports. The B port is precharged to bias voltage (BIASV) through the equivalent of a 10-kΩ resistor when OE is high or if the device is powered down (VCC = 0 V). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2005, Texas Instruments Incorporated SN74CB3Q16811 24-BIT SWITCH WITH PRECHARGED OUTPUTS 2.5-V/3.3-V LOW-VOLTAGE FET BUS SWITCH www.ti.com SCDS153B – OCTOBER 2003 – REVISED MARCH 2005 During insertion (or removal) of a card into (or from) an active bus, the card's output voltage may be close to GND. When the connector pins make contact, the card's parasitic capacitance tries to force the bus signal to GND, creating a possible glitch on the active bus. This glitching effect can be reduced by using a bus switch with precharged bias voltage (BIASV) of the bus switch equal to the input threshold voltage level of the receivers on the active bus. This method ensures that any glitch produced by insertion (or removal) of the card does not cross the input threshold region of the receivers on the active bus, minimizing the effects of live-insertion noise. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. DGG, DGV, OR DL PACKAGE (TOP VIEW) BIASV 1A1 1A2 1A3 1A4 1A5 1A6 GND 1A7 1A8 1A9 1A10 1A11 1A12 2A1 2A2 VCC 2A3 GND 2A4 2A5 2A6 2A7 2A8 2A9 2A10 2A11 2A12 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 1OE 2OE 1B1 1B2 1B3 1B4 1B5 GND 1B6 1B7 1B8 1B9 1B10 1B11 1B12 2B1 2B2 2B3 GND 2B4 2B5 2B6 2B7 2B8 2B9 2B10 2B11 2B12 Table 1. FUNCTION TABLE (EACH 12-BIT BUS SWITCH) 2 INPUT OE INPUT/OUTPUT A FUNCTION L B A port = B port H Z Disconnect B port = BIASV SN74CB3Q16811 24-BIT SWITCH WITH PRECHARGED OUTPUTS 2.5-V/3.3-V LOW-VOLTAGE FET BUS SWITCH www.ti.com SCDS153B – OCTOBER 2003 – REVISED MARCH 2005 LOGIC DIAGRAM (POSITIVE LOGIC) 1 BIASV 2 1A1 54 1B1 SW 14 1A12 42 SW 1B12 56 1OE 41 15 2A1 SW 28 2A12 2B1 29 SW 2B12 55 2OE 3 SN74CB3Q16811 24-BIT SWITCH WITH PRECHARGED OUTPUTS 2.5-V/3.3-V LOW-VOLTAGE FET BUS SWITCH www.ti.com SCDS153B – OCTOBER 2003 – REVISED MARCH 2005 SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW) BIASV A B VCC Charge Pump EN(1) (1) EN is the internal enable signal applied to the switch. Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 4.6 V BIASV BIAS supply voltage range –0.5 7 V VIN Control input voltage range (2) (3) –0.5 7 V VI/O Switch I/O voltage range (2) (3) (4) –0.5 7 IIK Control input clamp current VIN < 0 –50 mA II/OK I/O port clamp current VI/O < 0 –50 mA ±64 mA ±100 mA II/O ON-state switch current (5) Continuous current through VCC or GND θJA Tstg (1) (2) (3) (4) (5) (6) 4 Package thermal impedance (6) Storage temperature range DGG package 64 DGV package 48 DL package 56 –65 150 UNIT V °C/W °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to ground, unless otherwise specified. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. VI and VO are used to denote specific conditions for VI/O. II and IO are used to denote specific conditions for II/O. The package thermal impedance is calculated in accordance with JESD 51-7. SN74CB3Q16811 24-BIT SWITCH WITH PRECHARGED OUTPUTS 2.5-V/3.3-V LOW-VOLTAGE FET BUS SWITCH www.ti.com SCDS153B – OCTOBER 2003 – REVISED MARCH 2005 Recommended Operating Conditions (1) MIN MAX VCC Supply voltage BIASV Bias voltage VIH High-level control input voltage VIL Low-level control input voltage VI/O Data input/output voltage TA Operating free-air temperature (1) UNIT 2.3 3.6 V 0 5 V VCC = 2.3 V to 2.7 V 1.7 5.5 VCC = 2.7 V to 3.6 V 2 5.5 VCC = 2.3 V to 2.7 V 0 0.7 VCC = 2.7 V to 3.6 V 0 0.8 0 5.5 V –40 85 °C V V All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Electrical Characteristics (1) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK TEST CONDITIONS VCC = 3.6 V, II = –18 mA IIN Control inputs VCC = 3.6 V, VIN = 0 to 5.5 V IO B port VCC = 3.V, BIASV = 2.4 V, VO = 0, Switch OFF, VIN = VCC or GND IOZ (3) VCC = 3.6 V, VO = 0 to 5.5 V, VI = 0, Switch OFF, VIN = VCC or GND Ioff VCC = 0, VO = 0 to 5.5 V, VI = 0 ICC VCC = 3.6 V, II/O = 0, Switch ON or OFF, VIN = VCC or GND Other inputs at VCC or GND ∆ICC (4) VCC = 3.6 V, One input at 3 V, ICCD (5) Per control input VCC = 3.6 V, A and B ports open, Control input switching at 50% duty cycle Cin Control inputs VCC = 3.3 V, VIN = 5.5 V, 3.3 V, or 0 VCC = 3.3 V, Switch OFF, VIN = VCC or GND, VCC = 3.3 V, Cio(OFF) Cio(ON) ron (6) Control inputs A port VCC = 2.3 V, TYP at VCC = 2.5 V VCC = 3 V (1) (2) (3) (4) (5) (6) MIN TYP (2) MAX –1.8 V ±1 µA 0.2 1 UNIT mA ±1 µA 1 µA 3 mA 30 µA mA/ MHz 0.38 0.45 3.5 5 pF VI/O = 5.5 V, 3.3 V, or 0 4 5 pF Switch ON, VIN = VCC or GND, VI/O = 5.5 V, 3.3 V, or 0 10 12.5 pF VI = 0, IO = 30 mA 5 8 VI = 1.7 V, IO = –15 mA 5 9 VI = 0, IO = 30 mA 5 6.5 VI = 2.4 V, IO = –15 mA 5 8 Ω VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins. All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. For I/O ports, the parameter IOZ includes the input leakage current. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. This parameter specifies the dynamic power-supply current associated with the operating frequency of a single control input (see Figure 2). Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals. 5 SN74CB3Q16811 24-BIT SWITCH WITH PRECHARGED OUTPUTS 2.5-V/3.3-V LOW-VOLTAGE FET BUS SWITCH www.ti.com SCDS153B – OCTOBER 2003 – REVISED MARCH 2005 Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) FROM (INPUT) (1) (2) VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V FROM (INPUT) TO (OUTPUT) fOE (1) OE A or B 10 20 tpd (2) A or B B or A 0.09 0.15 PARAMETER tPZH BIASV = GND tPZL BIASV = 3 V tPHZ BIASV = GND tPLZ BIASV = 3 V OE A or B OE A or B MIN MAX MIN UNIT MAX 1.5 8 1.5 8 1.5 8 1.5 8 1 7.5 1 7.5 1 7.5 1 7.5 MHz ns ns ns Maximum switching frequency for control input (VO > VCC, VI = 5 V, RL ≥ 1 MΩ, CL = 0) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). ron - ON-State Resistance - Ω 16 14 12 VCC = 3.3 V TA = 25°C IO = -15 mA 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VI - V Figure 1. Typical ron vs VI 30 VCC = 3.3 V TA = 25°C A and B Ports Open 25 ICC - mA 20 15 One OE Switching 10 5 0 0 5 10 15 OE Switching Frequency - MHz Figure 2. Typical ICC vs OE Switching Frequency 6 20 25 SN74CB3Q16811 24-BIT SWITCH WITH PRECHARGED OUTPUTS 2.5-V/3.3-V LOW-VOLTAGE FET BUS SWITCH www.ti.com SCDS153B – OCTOBER 2003 – REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION VCC Input Generator VIN 50 Ω 50 Ω VG1 TEST CIRCUIT DUT 2 × VCC Input Generator S1 RL VO VI 50 Ω 50 Ω VG2 CL (see Note A) RL TEST VCC S1 RL VI CL tpd(s) 2.5 V ± 0.2 V 3.3 V ± 0.3 V Open Open 500 Ω 500 Ω VCC or GND VCC or GND 30 pF 50 pF tPLZ/tPZL 2.5 V ± 0.2 V 3.3 V ± 0.3 V 2 × VCC 2 × VCC 500 Ω 500 Ω GND GND 30 pF 50 pF 0.15 V 0.3 V tPHZ/tPZH 2.5 V ± 0.2 V 3.3 V ± 0.3 V GND GND 500 Ω 500 Ω VCC VCC 30 pF 50 pF 0.15 V 0.3 V Output Control (VIN) V∆ VCC VCC/2 VCC VCC/2 VCC/2 0V tPLH VOH Output VCC/2 VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (tpd(s)) Output Waveform 1 S1 at 2 × VCC (see Note B) tPLZ VCC VCC/2 VOL + V∆ VOL tPZH tPHL VCC/2 0V tPZL Output Control (VIN) Open GND Output Waveform 2 S1 at GND (see Note B) tPHZ VOH VCC/2 VOH - V∆ 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). H. All parameters and waveforms are not applicable to all devices. Figure 3. Test Circuit and Voltage Waveforms 7 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74CB3Q16811DGGRE4 ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74CB3Q16811DGVRE4 ACTIVE TVSOP DGV 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74CB3Q16811DLRG4 ACTIVE SSOP DL 56 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3Q16811DGGR ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3Q16811DGVR ACTIVE TVSOP DGV 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3Q16811DL ACTIVE SSOP DL 56 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3Q16811DLG4 ACTIVE SSOP DL 56 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3Q16811DLR ACTIVE SSOP DL 56 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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