TI TMS470R1VC002

TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
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High-Performance Static CMOS Technology
TMS470R1x 16/32-Bit RISC Core (ARM7TDMI)
– 20-MHz System Clock
– Independent 16/32-Bit Instruction Set
– Open Architecture With Third-Party Support
– Built-In Debug Module
– Utilizes Big-Endian Format
Upwardly Software-Compatible With the
TMS470R1VF336 Device
Integrated Memory
– 32K-Byte Program ROM
– 2.5K-Byte Static RAM (SRAM)
Operating Features
– Core Supply Voltage (VCC): 1.8 V Nominal
– I/O Supply Voltage (VCCIO): 3.3 V Nominal
– Low-Power Modes: STANDBY and HALT
– Industrial and Automotive Temperature
Ranges
470+ System Module
– 32-Bit Address Space Decoding
– Bus Supervision for Memory and
Peripherals
– Analog Watchdog (AWD) Timer
– Real-Time Interrupt (RTI)
– System Integrity and Failure Detection
Clock Divider Module (CDM)
– Crystal Oscillator, Clock Monitor Circuit, and
Prescaler
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Serial Peripheral Interface (SPI)
– 255 Programmable Baud Rates
16-Input/Output High-End Timer (HET)
– 16 Programmable I/O Channels:
– 12 High-Resolution Pins
– 4 Standard-Resolution Pins
– High-Resolution Share Feature (XOR)
– High-End Timer RAM
– 32-Instruction Capacity
Seven External Interrupts
Flexible Interrupt Handling
6 Dedicated GIO Pins,1 Input-Only GIO Pin, and
22 Additional Peripheral I/Os
On-Chip Scan-Base Emulation Logic,
IEEE Standard 1149.1† (JTAG) Boundary-Scan
Logic
100-Pin Plastic Low-Profile Quad Flatpack
(PZ Suffix)
Development System Support Tools Available
– Code Composer Studio IDE
– HET Assembler and Simulator
– Real-Time In-Circuit Emulation
External Clock Prescale (ECP) Module
– Programmable Low-Frequency External
Clock (CLK)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are property of their respective owners.
Code Composer Studio is a trademark of Texas Instruments.
ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).
† IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication
date. Products conform to specifications per the Texas
Instruments standard warranty. Production processing does
not necessarily include testing of all parameters.
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1
TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
PLLDIS
TDI
TDO
TCK
HET[8]
NC
VSS
VCCIO
CLKOUT
NC
NC
NC
NC
NC
VCC
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
TMS470R1VC002 100-PIN PZ PACKAGE (TOP VIEW)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
47
HET[20]
80
46
NC
NC
NC
81
45
HET[22]
82
44
NC
NC
83
43
NC
TMS
84
42
NC
TMS2
85
41
NC
VSS
86
40
VCC
VCC
87
39
VSS
HET[0]
88
38
NC
HET[1]
89
37
NC
NC
90
36
NC
NC
91
35
HET[24]
NC
92
34
HET[31]
NC
93
33
HET[30]
NC
94
32
HET[29]
HET[2]
95
31
GIOA[3]/INT3
HET[3]
96
30
GIOA[2]/INT2
HET[4]
97
29
GIOA[1]/INT1/ECLK
HET[5]
98
28
GIOA[0]/INT0†
HET[6]
99
27
TEST
HET[7]
100
26
TRST
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GIOA[4]/INT4
GIOA[5]/INT5
GIOA[6]/INT6
NC
PORRST
NC
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
NC
9
NC
8
NC
7
NC
6
NC
5
NC
4
NC
3
VCCIO
2
RST
VSS
1
VCC
79
NC
OSCIN
NC
OSCOUT
NC
VSS
48
SPICLK
78
SPISOMI
HET[18]
NC
SPISIMO
49
SPISCS
50
77
SPIENA
76
NC
† GIOA[0]/INT0 (pin 28) is an input-only GIO pin.
2
AWD
NC
TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
description
The TMS470R1VC002† device is a member of the Texas Instruments (TI) TMS470R1x family of generalpurpose16/32-bit reduced instruction set computer (RISC) microcontrollers. The VC002 microcontroller offers
high performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting
in a high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU
views memory as a linear collection of bytes numbered upwards from zero. The TMS470R1VC002 utilizes the
big-endian format where the most significant byte of a word is stored at the lowest numbered byte and the least
significant byte at the highest numbered byte.
High-end embedded control applications demand more performance from their controllers while maintaining
low costs. The VC002 RISC core architecture offers solutions to these performance and cost demands while
maintaining low power consumption.
The VC002 device contains the following:
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ARM7TDMI 16/32-Bit RISC CPU
TMS470R1x system module (SYS) with 470+ enhancements
32K-byte ROM
2.5K-byte SRAM
Clock divider module (CDM)
Analog watchdog (AWD) timer
Real-time interrupt (RTI) module
Serial peripheral interface (SPI) module
High-end timer (HET) controlling 16 I/Os
External Clock Prescale (ECP)
Up to 28 I/O pins and 1 input-only pin
The functions performed by the 470+ system module (SYS) include: address decoding; memory and peripherals
bus supervision; reset and abort exception management; prioritization for all internal interrupt sources; device
clock control; and parallel signature analysis (PSA). This data sheet includes device-specific information such
as memory and peripheral select assignment, interrupt priority, and a device memory map. For a more detailed
functional description of the SYS module, see the TMS470R1x System Module Reference Guide (literature
number SPNU189).
The VC002 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte,
half-word, and word modes.
The ROM memory on the VC002 device is programmable read-only memory that is masked at the time of
device fabrication.
The VC002 device has a serial peripheral interface (SPI). The SPI provides a convenient method of serial
interaction for high-speed communications between similar shift-register type devices. For more detailed functional information on the SPI peripheral, see the TMS470R1x Serial Peripheral Interface (SPI) Reference Guide
(literature number SPNU195).
The HET is a 16-bit advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine
and an attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially
well suited for applications requiring multiple sensor information and drive actuators with complex and accurate
time pulses. For more detailed functional information on the HET, see the TMS470R1x High-End Timer (HET)
Reference Guide (literature number SPNU199).
† The TMS470R1VC002 device name shall be referred to as VC002 throughout the remainder of this document.
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3
TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
description (continued)
The clock divider module (CDM) contains a clock-monitor circuit, a clock-enable circuit, and a prescaler (with
prescale values of 1–8). The CDM provides ACLK to the system (SYS) module. The SYS module subsequently
provides system clock (SYSCLK), real-time interrupt clock (RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other VC002 device modules. For more detailed functional information on the CDM, see
the TMS470R1x Clock Divider Module (CDM) Reference Guide (literature number SPNU215).
The VC002 device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous
external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see the
TMS470R1x External Clock Prescaler (ECP) Reference Guide (literature number SPNU202).
4
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TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
device characteristics
The TMS470R1VC002 device is a derivative of the F05 system emulation device SE470R1VB8AD. Table 1
identifies all the characteristics of the TMS470R1VC002 device except the SYSTEM and CPU, which are
generic [the only exception being that the VC002 SYSTEM does not support a memory protection unit (MPU).
The COMMENTS FOR VC002 column aids the user in software-programming and references device-specific
information.
Table 1. Device Characteristics
CHARACTERISTICS
DEVICE DESCRIPTION
TMS470R1VC002
COMMENTS FOR VC002
MEMORY
For the number of memory selects on this device, see the Memory Selection Assignment table (Table 2).
INTERNAL
MEMORY
32K-Byte ROM
2.5K-Byte SRAM
The VC002 RAM is implemented in one 2.5K-byte array selected by two memoryselect signals (see the Memory Selection Assignment table, Table 2).
The VC002 SYSTEM module does not support a memory protection unit (MPU).
PERIPHERALS
For the device-specific interrupt priority configurations, see the Interrupt Priority table (Table 4). And for the 1K peripheral address ranges
and their peripheral selects, see the VC002 Peripherals and System Module Addresses table (Table 3).
The clock divider module (CDM) has no PLL, and therefore, no multiply factors for
the clock.
CLOCK
CDM
GENERAL-PURPOSE
I/Os
6 I/O
1 Input only
ECP
YES
SPI
(5-pin, 4-pin or 3-pin)
1 (5-pin)
Port A has only seven (7) external pins (GIOA[7]/INT7 is not applicable)
The ECP uses the GIOA[1]/INT1/ECLK pin
SPI (5-pin)
The VC002 has both the logic and registers for a 16-I/O HET.
HET with
XOR Share
16 I/O
The high-resolution (HR) SHARE feature allows even HR pins to share the next
higher odd HR pin structures. This HR sharing is independent of whether or not the
odd pin is available externally. If an odd pin is available externally and shared, then
the odd pin can only be used as a general-purpose I/O. For more information on HR
SHARE, see the TMS470R1x High-End Timer (HET) Reference Guide (literature
number SPNU199).
HET RAM
32-Instruction Capacity
CORE VOLTAGE
1.8 V
I/O VOLTAGE
3.3 V
PINS
100
PACKAGE
PZ
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5
TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
functional block diagram
External Pins
OSCIN
RAM
(2.5K Bytes)
ROM
(32K Bytes)
CDM
OSCOUT
Crystal
External Pins
PLLDIS
CPU Address/Data Bus
TRST
TMS470R1x
CPU
TCK
TDI
TDO
TMS
TMS470R1x 470+ SYSTEM MODULE
TMS2
RST
Expansion Address/Data Bus
AWD
PORRST
CLKOUT
SPI
SPISCS
SPIENA
SPISIMO
SPISOMI
SPICLK
GIOA[1]/INT1/
ECLK
ECP
GIO
GIOA[0]/INT0†
GIOA[2:6]/
INT[2:6]
TEST
† GIOA[0]/INT0 is an input-only GIO pin.
6
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HET with
XOR Share
(32-Word)
HET [31:29, 24]
HET[22, 20,18, 8:0]
TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
Terminal Functions
TERMINAL
NAME
NO.
TYPE†‡
INTERNAL
PULLUP/
PULLDOWN§
DESCRIPTION
HIGH-END TIMER (HET)
HET[0]
88
HET[1]
89
HET[2]
95
HET[3]
96
HET[4]
97
HET[5]
98
HET[6]
99
HET[7]
100
HET[8]
55
HET[18]
49
HET[20]
47
HET[22]
45
HET[24]
35
HET[29]
32
HET[30]
33
HET[31]
34
GIOA[0]/INT0
GIOA[1]/INT1/
ECLK
GIOA[2]/INT2
GIOA[3]/INT3
GIOA[4]/INT4
GIOA[5]/INT5
GIOA[6]/INT6
28
The VC002 has both the logic and registers for a 16-I/O HET.
Timer input capture or output compare. The HET[31:0] applicable pins can be
programmed as general-purpose input/output (GIO) pins. HET[22, 20, 18, 8:0] are
high-resolution pins and HET[31:29, 24] are standard-resolution pins.
3.3-V I/O
IPD
The high-resolution (HR) SHARE feature allows even HR pins to share the next higher
odd HR pin structures. This HR sharing is independent of whether or not the odd pin
is available externally. If an odd pin is available externally and shared, then the odd
pin can only be used as a general-purpose I/O. For more information on HR SHARE,
see theTMS470R1x High-End Timer (HET) Reference Guide (literature number
SPNU199).
GENERAL-PURPOSE I/O (GIO)
3.3-V I
29
30
31
25
24
23
SPICLK
5
SPIENA
1
SPISCS
2
SPISIMO
3
SPISOMI
4
General-purpose input/output pins. GIOA[0]/INT0 is an input-only pin. GIOA[6:0]/
INT[6:0] are interrupt-capable pins.
3.3-V I/O
IPD
The GIOA[1]/INT1/ECLK pin is multiplexed with the external clock-out function of the
external clock prescale (ECP) module.
SERIAL PERIPHERAL INTERFACE (SPI)
SPI clock. SPICLK can be programmed as a GIO pin.
SPI chip enable. SPIENA can be programmed as a GIO pin.
3.3-V I/O
IPD
SPI slave chip select. SPISCS can be programmed as a GIO pin.
SPI data stream. Slave in/master out. SPISIMO can be programmed as a GIO pin.
SPI data stream. Slave out/master in. SPISOMI can be programmed as a GIO pin.
CLOCK DIVIDER MODULE (CDM)
Crystal connection pin or external clock input
OSCIN
8
1.8-V I
OSCOUT
7
1.8-V O
External crystal connection pin
3.3-V I
This pin is required for test purposes only. The Clock-Divider Module (CDM) on the
VC002 device does not support a PLL circuit. When PLLDIS is high, the 4 096-cycle
clock counter is disabled.
PLLDIS
51
IPD
† I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect
‡ All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
§ IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
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TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
Terminal Functions (Continued)
TERMINAL
NAME
NO.
TYPE†‡
INTERNAL
PULLUP/
PULLDOWN§
DESCRIPTION
SYSTEM MODULE (SYS)
Bidirectional pin. CLKOUT can be programmed as a GIO pin or the output of SYSCLK,
ICLK, or MCLK.
CLKOUT
59
3.3-V I/O
IPD
Note: If this pin is to be used as an input, it is recommended that an external pulldown
be used.
PORRST
RST
21
10
3.3-V I
3.3-V I/O
IPD
Input master chip power-up reset. External VCC monitor circuitry must assert a poweron reset.
IPU
Bidirectional reset. The internal circuitry can assert a reset, and an external system
reset can assert a device reset.
On this pin, the output buffer is implemented as an open drain (drives low only).
To ensure an external reset is not arbitrarily generated, TI recommends that an
external pullup resistor be connected to this pin.
WATCHDOG/REAL-TIME INTERRUPT (WD/RTI)
Analog watchdog reset. The AWD pin provides a system reset if the WD KEY is not
written in time by the system, providing an external RC network circuit is connected.
IPD
For more details on the external RC network circuit, see the TMS470R1x System
Module Reference Guide (literature number SPNU189).
AWD
50
3.3-V I/O
TCK
54
3.3-V I
IPD
TDI
52
3.3-V I
IPU
Test data in. TDI inputs serial data to the test instruction register, test data register,
and programmable test address (JTAG).
TDO
53
3.3-V O
IPD
Test data out. TDO outputs serial data from the test instruction register, test data
register, identification register, and programmable test address (JTAG).
TEST
27
3.3-V I
IPD
Test enable. Reserved for internal use only.
For proper operation, this pin must be connected to ground.
TMS
84
3.3-V I
IPU
Serial input for controlling the state of the CPU TAP controller (JTAG)
IPU
Serial input for controlling the second TAP.
For proper operation, this pin must be connected to VCC or not connected.
IPD
Test hardware reset to TAP1 and TAP2. IEEE Standard 1149-1 (JTAG) BoundaryScan Logic
For proper device operation, the TRST pin must be externally pulled down with
a 10-kΩ resistor.
TMS2
TRST
85
26
3.3-V I
3.3-V I
TEST/DEBUG (T/D)
Test clock. TCK controls the test hardware (JTAG).
SUPPLY VOLTAGE CORE (1.8 V)
9
VCC
40
66
1.8-V
PWR
Core logic supply voltage
87
SUPPLY VOLTAGE DIGITAL I/O (3.3 V)
VCCIO
12
58
3.3-V
PWR
Digital I/O supply voltage
† I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect
‡ All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
§ IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
8
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TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
Terminal Functions (Continued)
TERMINAL
NAME
NO.
TYPE†‡
INTERNAL
PULLUP/
PULLDOWN§
DESCRIPTION
SUPPLY GROUND
6
11
VSS
39
57
GND
Supply ground reference
65
86
NO CONNECTS
13
14
15
16
17
18
19
20
22
36
37
38
41
42
43
44
46
NC
48
NC
No Connection
56
60
61
62
63
64
67
68
69
70
71
72
73
74
75
76
77
† I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect
‡ All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
§ IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
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9
TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
Terminal Functions (Continued)
TERMINAL
NAME
NO.
TYPE†‡
INTERNAL
PULLUP/
PULLDOWN§
NO CONNECTS (CONTINUED)
DESCRIPTION
78
79
80
81
82
NC
83
NC
No Connection
90
91
92
93
94
† I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect
‡ All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
§ IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
10
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TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
VC002 DEVICE-SPECIFIC INFORMATION
memory
Figure 1 shows the memory map of the VC002 device.
0xFFFF_FFFF
Memory (4G Bytes)
SYSTEM
0xFFFF_FFFF
0xFFFF_FD00
System Module Control Registers
(512K Bytes)
Reserved
0xFFF8_0000
0xFFF7_FFFF
HET
Peripheral Control Registers
(512K Bytes)
0xFFF0_0000
0xFFEF_FFFF
0xFFE8_8080
0xFFE8_807F
0xFFE8_8000
0xFFE8_7FFF
0xFFE8_4024
0xFFE8_4023
0xFFE8_4000
0xFFE8_3FFF
SPI
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GIO/ECP
Reserved
Reserved
Reserved
Reserved
Reserved
0xFFE0_0000
Reserved
0xFFF8_0000
0xFFF7_FC00
0xFFF7_F800
0xFFF7_F500
0xFFF7_F400
0xFFF7_F000
0xFFF7_EC00
0xFFF7_E400
0xFFF7_E000
0xFFF7_DC00
0xFFF7_D800
Reserved
0xFFF7_D400
Reserved
RAM
(2.5K Bytes)
Reserved
Reserved
Program
and
Data Area
0xFFF7_CC00
0xFFF7_C800
0xFFF0_0000
ROM
(32K Bytes)
0x0000_001F
FIQ
IRQ
Reserved
Data Abort
Prefetch Abort
0x0000_0020
0x0000_001F
0x0000_0000
Software Interrupt
Undefined Instruction
Exception, Interrupt, and
Reset Vectors
Reset
0x0000_001C
0x0000_0018
0x0000_0014
0x0000_0010
0x0000_000C
0x0000_0008
0x0000_0004
0x0000_0000
NOTES: A. Memory addresses are configurable by the system (SYS) module within the range of 0x0000_0000 to 0xFFE0_0000.
B. The CPU registers are not a part of the memory map.
Figure 1. Memory Map
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11
TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
memory selects
Memory selects allow the user to address memory arrays (i.e., ROM, RAM, and HET RAM) at user-defined
addresses. Each memory select has its own set (low and high) of memory base address registers (MFBAHRx
and MFBALRx) that, together, define the array’s starting (base) address, block size, and protection.
The base address of each memory select is configurable to any memory address boundary that is a multiple
of the decoded block size. For more information on how to control and configure these memory select registers,
see the bus structure and memory sections of the TMS470R1x System Module Reference Guide (literature
number SPNU189).
For the memory selection assignments and the memory selected, see Table 2.
Table 2. Memory Selection Assignment
MEMORY
SELECT
0 (fine)
MEMORY SELECTED
(ALL INTERNAL)
ROM
1 (fine)
ROM
2 (fine)
RAM
3 (fine)
RAM
4 (fine)
HET RAM
MEMORY
SIZE
32K
2.5K†
1K
MPU
MEMORY BASE ADDRESS REGISTER
NO
MFBAHR0 and MFBALR0
NO
MFBAHR1 and MFBALR1
NO
MFBAHR2 and MFBALR2
NO
MFBAHR3 and MFBALR3
MFBAHR4 and MFBALR4
STATIC MEM
CTL REGISTER
SMCR1
† The starting addresses for both RAM memory-select signals cannot be offset from each other by a multiple of the user-defined block size in
the memory-base address register. There is no illegal address detection for RAM accesses between 2.5 K and 3.0 K bytes.
RAM
The VC002 device contains 2.5K bytes of internal static RAM configurable by the SYS module to be addressed
within the range of 0x0000_0000 to 0xFFE0_0000. This VC002 RAM is implemented in one 2.5K-byte array
selected by two memory-select signals. This VC002 configuration imposes an additional constraint on the
memory map for RAM; the starting addresses for both RAM memory selects cannot be offset from each other
by the multiples of the size of the physical RAM (i.e., 2.5K for the VC002 device). The VC002 RAM is addressed
through memory selects 2 and 3.
ROM
The program ROM consists of 32K bytes mask programmable read-only memory. The program ROM is used
for permanent storage of data or instructions. Programming of the mask ROM is performed at the time of device
fabrication.
HET RAM
The VC002 device contains HET RAM. The HET RAM has a 32-instruction capability. The HET RAM is configurable by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. The HET
RAM is addressed through memory select 4.
memory protection (not available on VC002)
This VC002 device has no memory protection unit (MPU) in the 470+ SYS module; therefore, this device does
not support memory protection for the RAM and ROM (see Table 2).
XOR share
The VC002 HET peripheral contains the XOR-share feature. This feature allows two adjacent HET highresolution channels to be XORed together, making it possible to output smaller pulses than a standard HET.
For more detailed information on the HET XOR-share feature, see the TMS470R1x High-End Timer (HET)
Reference Guide (literature number SPNU199).
12
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TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
peripheral selects and base addresses
The VC002 device uses three of the sixteen peripheral selects to decode the base addresses of the peripherals.
These peripheral selects are fixed and transparent to the user since they are part of the decoding scheme used
by the SYS module.
Control registers for the peripherals and SYS module begin at the base addresses shown in Table 3.
Table 3. VC002 Peripherals and System Module Addresses
CONNECTING MODULE
SYSTEM
RESERVED
HET
SPI
RESERVED
RESERVED
RESERVED
GIO/ECP
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
ADDRESS RANGE
BASE ADDRESS
ENDING ADDRESS
0XFFFF_FD00
0XFFFF_FFFF
0XFFF8_0000
0XFFFF_FCFF
0XFFF7_FC00
0XFFF7_FFFF
0XFFF7_F800
0XFFF7_FBFF
0XFFF7_F500
0XFFF7_F7FF
0XFFF7_F400
0XFFF7_F4FF
0XFFF7_F000
0XFFF7_EC00
0XFFF7_E400
0XFFF7_E000
0XFFF7_DC00
0XFFF7_D800
0XFFF7_D400
0XFFF7_CC00
0XFFF7_C800
0XFFF7_C000
0XFFF0_0000
0XFFE8_8000
0XFFE8_4000
POST OFFICE BOX 1443
0XFFF7_F3FF
0XFFF7_EFFF
0XFFF7_EBFF
0XFFF7_E3FF
0XFFF7_DFFF
0XFFF7_DBFF
0XFFF7_D7FF
0XFFF7_D3FF
0XFFF7_CBFF
0XFFF7_C7FF
0XFFF7_BFFF
0XFFE8_807F
0XFFE8_4023
• HOUSTON, TEXAS 77251-1443
PERIPHERAL SELECTS
N/A
N/A
PS[0]
PS[1]
PS[2]
PS[3]
PS[4]
PS[5] - PS[6]
PS[7]
PS[8]
PS[9]
PS[10]
PS[11] - PS[12]
PS[13]
PS[14] - PS[15]
N/A
N/A
N/A
13
TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
interrupt priority
The central interrupt manager (CIM) portion of the SYS module manages the interrupt requests from the device
modules (i.e., SPI, HET, and RTI, etc.).
Although the CIM can accept up to 32 interrupt request signals, the VC002 device only uses 9 of those interrupt
request signals. The request channels are maskable so that individual channels can be selectively disabled.
All interrupt requests can be programmed in the CIM to be of either type:
●
Fast interrupt request (FIQ)
●
Normal interrupt request (IRQ)
The precedences of request channels decrease with ascending channel order in the CIM (0 [highest] and
31 [lowest] priority). For these channel priorities and the associated modules, see Table 4.
Table 4. Interrupt Priority
MODULES
SPI
INTERRUPT SOURCES
SPI end-transfer/overrun
RTI
COMP2 interrupt
1
RTI
COMP1 interrupt
2
RTI
TAP interrupt
3
Reserved
GIO
4
Interrupt A
5
Reserved
HET
6
Interrupt 1
7
Reserved
8
Reserved
9
Reserved
10
Reserved
11
Reserved
12
Reserved
13
Reserved
14
Reserved
15
Reserved
16
Reserved
17
Reserved
18
Reserved
19
Reserved
System
20
SW interrupt (SSI)
21
Reserved
HET
22
Interrupt 2
23
Reserved
24
Reserved
25
Reserved
26
Reserved
27
Reserved
GIO
14
INTERRUPT LEVEL/CHANNEL
0
28
Interrupt B
29
Reserved
30
Reserved
31
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TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
development system support
Texas Instruments provides extensive hardware and software development support tools for the TMS470R1x
family. These support tools include:
●
Code Composer Studio IDE
–
–
–
Fully integrated suite of software development tools
Includes Compiler/Assembler/Linker, Debugger, and Simulator
Supports Real-Time analysis, data visualization, and open API
●
Optimizing C compiler
– Supports high-level language programming
– Full implementation of the standard ANSI C language
– Powerful optimizer that improves code-execution speed and reduces code size
– Extensive run-time support library included
– TMS470R1x control registers easily accessible from the C program
– Interfaces C functions and assembly functions easily
– Establishes comprehensive, easy-to-use tool set for the development of high-performance
microcontroller applications in C/C++
●
Assembly language tools (assembler and linker)
– Provides extensive macro capability
– Allows high-speed operation
– Allows extensive control of the assembly process using assembler directives
– Automatically resolves memory references as C and assembly modules are combined
●
TMS470R1x CPU Simulator
– Provides capability to simulate CPU operation without emulation hardware
– Allows inspection and modifications of memory locations
– Allows debugging programs in C or assembly language
●
XDS510 emulation communication kit
– Allows high-speed JTAG communication to the TMS470R1x emulator or target board
– Includes XDS510 ISA PC card and JTAG emulation cable
●
XDS510WS emulation communication kit
– Allows high-speed JTAG communication to the TMS470R1x emulator or target board
– Includes XDS510 Workstation communication box and JTAG emulation cable
●
XDS510PP emulation communication kit
– Allows JTAG communication to the TMS470R1x emulator or target board with a connection to the PC
parallel port
– Includes XDS510PP communication box and parallel port cable
●
XDS560 emulator
– Allows high-speed JTAG communication to the TMS470R1x emulator or target board
– Includes XDS560 communication board and cable
Code Composer Studio, XDS510, XDS510WS, XDS510PP, and XDS560 are trademarks of Texas Instruments.
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15
TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
development system support (continued)
Table 5, Table 6, and Table 7 provide the part numbers for the TMS470R1VC002 hardware and software
development tools.
Table 5. Code Development Tools
PRODUCT
TMDX474A596-07
TMDX474H852-02
DESCRIPTION
C/C++ Compiler
Assembler/Linker
HOST
SPARC, HP
HET
Assembler/Simulator
PC, SPARC, HP
OPERATING SYSTEM
SunOS 5.5
HP-UX 10.2
Solaris 2.5
MS-DOS
Windows 95
Windows 98
Windows NT
SunOS 4.1.3
HP-UX 9.0.3
Table 6. Debug Tools
PRODUCT
DESCRIPTION
HOST
OPERATING SYSTEM
Windows 95
Windows 98
Windows NT
TMDS474785F-07
Code Composer Studio IDE
PC
TMDS4740551-07
SW Simulator
SPARC, HP
SunOS 4.1.3
HP-UX 9.0x
Solaris 2.x
TMDX4740600
Emulation SW Kit
XDS510WS Debugger
SPARC, HP
SunOS 5.5x
HP-UX 10.2x
Solaris 2.5x
Table 7. Hardware Tools
PRODUCT
TMDS00510
DESCRIPTION
XDS510 Board JTAG
Controller Kit
Emulator Cable
HOST
PC (ISA)
OPERATING SYSTEM
Windows 95
Windows 98
Windows NT
TMDS00510WS
XDS510WS Box JTAG
Controller Kit
Emulator Cable
SPARC, HP
SunOS 4.1.x
HP-UX 9.0x
TMDS3P701014
XDS510 Parallel Port JTAG
System Kit
PC
Windows 95
Windows 98
Windows NT
Note: Additional hardware and software development tools are available directly from ARM Ltd.
PC is a trademark of International Business Machines Corporation.
MS-DOS, Windows, and Windows NT are registered trademarks of Microsoft Corp.
SPARC is a trademark of SPARC International, Inc.
HP and HP-UX are trademarks of Hewlett-Packard Company.
SunOS and Solaris are trademarks of Sun Microsystems, Inc.
16
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TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
device numbering conventions
Figure 2 illustrates the numbering and symbol nomenclature for the TMS470R1x family.
TMS 470 R1 V C 00 2 PZ A
Prefix: TMS = Standard Prefix for Fully Qualified Devices
Family:
470 = TMS470 RISC-Embedded Microcontroller Family
V = 1.8-V Core Voltage
Program Memory Types:
CPU Type:
Device Type:
Program Memory Size
C
F
L
B
R
=
=
=
=
=
Masked ROM
Flash
ROM-less
System Emulator for Development Tools
RAM
R1 = ARM7TDMI CPU
00 = 00 Devices Containing the Following Modules:
– Clock Divider Module (CDM)
– 2.5K-Byte Static RAM
– 1K-Byte HET RAM (64 Instructions)
– Analog Watchdog (AWD) Timer
– Real-Time Interrupt (RTI)
– Serial Peripheral Interface (SPI) Module
– High-End Timer (HET)
– External Clock Prescaler (ECP)
2 = 0
– No on-chip program memory
1–5 – 1 to < 128K Bytes
6–B – 128K Bytes to < 1M Bytes
C–F – > 1M Bytes
Operating Free-Air
Temperature Ranges:
Package:
A =
T =
Q =
–40°C to 85°C
–40°C to 105°C
–40°C to 125°C
PZ = 100-Pin Plastic Low-Profile Quad Flatpack (LQFP)
Figure 2. TMS470R1x Family Nomenclature
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17
TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
device identification code register
The device identification code register identifies the silicon version, the technology family (TF), a ROM or Flash
device, and an assigned device-specific part number (see Table 8). The VC002 device identification code
register value is 0x0C47.
Table 8. TMS470 Device ID Bit Allocation Register
BIT 31
30
29
28
27
26
25
23
22
21
20
19
18
17
BIT 16
6
5
4
3
2
1
BIT 0
Reserved
FFFF_FFF0
BIT 15
LEGEND:
For bit 15:
For bits 3–14:
For bits 0–2:
24
14
13
12
11
10
9
8
7
0
VERSION
TF
R/F
PART NUMBER
1
1
1
R-0
R-K
R-K
R-K
R-K
R-1
R-1
R-1
R = Read only, -0 = Value after RST
R = Read only, -K = Value constant after RST
R = Read only, -1 = Value after RST
Bits 31:16
Reserved. Reads are undefined and writes have no effect.
Bit 15
"0" Mandatory Low. Bit 15 is tied low by default.
Bits 14:12
VERSION. Silicon version (revision) bits
These bits identify what version of silicon the device is. Initial device version numbers
start at "000".
Bit 11
TF. Technology Family (TF) bit
This bit distinguishes the technology family core power supply:
0 = 3.3 V for F10/C10 devices
1 = 1.8 V for F05/C05 devices
Bit 10
R/F. ROM/Flash bit
This bit distinguishes between ROM and Flash devices:
0 = Flash device
1 = ROM device
Bits 9:3
PART NUMBER. Device-specific part number bits
These bits identify the assigned device-specific part number.
The assigned device-specific part number for the VC002 device is: 0001000.
Bits 2:0
18
"1" Mandatory High. Bits 2,1, and 0 are tied high by default.
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TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
device part numbers
Table 9 lists all the available TMS470R1VC002 devices.
Table 9. Device Part Number
DEVICE PART
NUMBER
TMS470R1VC002PZA
PROGRAM MEMORY
FLASH
ROM
EEPROM
X
PACKAGE TYPE
100-PIN
LQFP
X
TMS470R1VC002PZT
X
X
TMS470R1VC002PZQ
X
X
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TEMPERATURE RANGES
−40°C TO 85°C
−40°C TO 105°C
−40°C TO 125°C
X
• HOUSTON, TEXAS 77251-1443
X
X
19
TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
DEVICE ELECTRICAL SPECIFICATIONS AND TIMING PARAMETERS
absolute maximum ratings over operating free-air temperature range, Q version
(unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 2.5 V
Supply voltage range, VCCIO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−0.3 V to 4.1V
Input voltage range: All input pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V
Input clamp current: IIK (VI < 0 or VI > VCCIO)
All pins except PORRST, TRST, TEST, and TCK . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Operating free-air temperature ranges, TA: A version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
T version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 105°C
Q version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to their associated grounds.
device recommended operating conditions‡
MIN
VCC
Digital logic supply voltage (Core)
VCCIO
Digital logic supply voltage (I/O)
VSS
Digital logic supply ground
TA
TJ
Operating free-air temperature
3
MAX
3.3
UNIT
2.05
V
3.6
V
0
V
A version
− 40
85
°C
T version
− 40
105
°C
Q version
− 40
125
°C
− 40
150
°C
Operating junction temperature
‡ All voltages are with respect to VSS.
20
NOM
1.71
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TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
electrical characteristics over recommended operating free-air temperature range, Q version
(unless otherwise noted)†
PARAMETER
Vhys
TEST CONDITIONS
Input hysteresis
inputs‡
VIL
Low-level input voltage
All
VIH
High-level input voltage
All inputs
Vth
Input threshold voltage
AWD only
Low-level output voltage
VOH
High-level output voltage
IIC
Input clamp current (I/O pins)§
IOL
Input current (I/O pins)
Low-level output
current
TYP
MAX
− 0.3
0.8
V
2
VCCIO + 0.3
V
1.7
V
1.3
0.2 VCCIO
IOL = 50 µA
0.2
IOH = IOH MIN
0.8 VCCIO
IOH = 50 µA
UNIT
V
IOL = IOL MAX
VOL
II
MIN
0.15
V
VCCIO − 0.2
V I < VSSIO − 0.3 or VI > VCCIO + 0.3
−1
IIL Pulldown
VI = VSS
−1
1
IIH Pulldown
VI = VCC
5
40
IIL Pullup
VI = VSS
−40
−5
IIH Pullup
VI = VCC
−1
1
All other pins
No pullup or pulldown
−1
1
1
CLKOUT, AWD, TDO VOL = VOL MAX
8
RST
VOL = VOL MAX
4
All other
output pins
VOL = VOL MAX
2
CLKOUT, AWD, TDO VOH = VOH MIN
−8
All other output pins
except RST
−2
V
mA
µA
mA
IOH
High-level output
current
CI
Input capacitance
2
pF
CO
Output capacitance
3
pF
ICC
VCC Digital supply current (operating mode)
SYSCLK = 20 MHz,
ICLK = 10 MHz, VCC = 2.05 V
VCC Digital supply current (standby mode)
VCC Digital supply current (halt mode)
VCCIO Digital supply current (operating mode)
ICCIO
VOH = VOH MIN
VCCIO Digital supply current (standby mode)
VCCIO Digital supply current (halt mode)
mA
30
mA
OCSIN = 5 MHz, VCC = 2.05 V
1.0
mA
All frequencies, VCC = 2.05 V
200
µA
No DC load, VCCIO = 3.6
V¶
10
mA
No DC load, VCCIO = 3.6
V¶
100
µA
No DC load, VCCIO = 3.6
V¶
20
µA
† Source currents (out of the device) are negative while sink currents (into the device) are positive.
‡ This does not apply to the PORRST pin. For PORRST exceptions, see the RST and PORRST timings section on page 27.
§ This parameter does not apply to input-only or output-only pins.
¶ I/O pins configured as inputs or outputs with no load. All pulldown inputs ≤ 0.2 V. All pullup inputs ≥ VCCIO − 0.2 V.
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21
TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
PARAMETER MEASUREMENT INFORMATION
IOL
Tester Pin
Electronics
50 Ω
VLOAD
Output
Under
Test
CL
IOH
Where: IOL
= IOL MAX for the respective pin (see Note A)
IOH
= IOH MIN for the respective pin (see Note A)
VLOAD = 1.5 V
= 150-pF typical load-circuit capacitance (see Note B)
CL
NOTES: A. For these values, see the electrical characteristics over recommended operating free-air temperature range table.
B. All timing parameters measured using an external load capacitance of 150 pF unless otherwise noted.
Figure 3. Test Load Circuit
22
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TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
timing parameter symbology
Timing parameter symbols have been created in accordance with JEDEC Standard 100. In order to shorten
the symbols, some of the pin names and other related terminology have been abbreviated as follows:
CM
CO
ER
ICLK
M
OSC, OSCI
OSCO
P
R
R0
R1
Compaction, CMPCT
CLKOUT
Erase
Interface clock
Master mode
OSCIN
OSCOUT
Program, PROG
Ready
Read margin 0, RDMRGN0
Read margin 1, RDMRGN1
RD
RST
S
SIMO
SOMI
SPC
SYS
Read
Reset, RST
Slave mode
SPInSIMO
SPInSOMI
SPInCLK
System clock
r
su
t
v
w
rise time
setup time
transition time
valid time
pulse duration (width)
Lowercase subscripts and their meanings are:
a
c
d
f
h
access time
cycle time (period)
delay time
fall time
hold time
The following additional letters are used with these meanings:
H
High
X
L
V
Low
Valid
Z
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Unknown, changing, or don’t care
level
High impedance
• HOUSTON, TEXAS 77251-1443
23
TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
external reference resonator/crystal oscillator clock option
The oscillator is enabled by connecting the appropriate fundamental 4–20 MHz resonator/crystal and load
capacitors across the external OSCIN and OSCOUT pins as shown in Figure 4a. The oscillator is a singlestage inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test measurement and HALT mode. TI strongly encourages each customer to submit samples of the device to the
resonator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will
best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over temperature/voltage extremes.
An external oscillator source can be used by connecting a TTL- or CMOS-level clock signal to the OSCIN pin
and leaving the OSCOUT input pin unconnected (open) as shown in Figure 4b.
OSCIN
C1
(see Note A)
OSCOUT
Crystal
OSCIN
C2
(see Note A)
External
Clock Signal
(toggling 0–3.3 V)
(a)
(b)
NOTE A: The values of C1 and C2 should be provided by the resonator/crystal vendor.
Figure 4. Recommended Crystal/Clock Connection
24
OSCOUT
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TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
clock divider module (CDM) specifications
timing requirements for CDM circuits enabled or disabled
MIN
MAX
UNIT
f(OSC)
Input clock frequency
tc(OSC)
Cycle time, OSCIN
50
ns
tw(OSCIL)
Pulse duration, OSCIN low
15
ns
tw(OSCIH)
Pulse duration, OSCIN high
15
ns
f(OSCRST)
OSC FAIL frequency
4
†
20
53
MHz
kHz
† Causes a device reset (specifically a clock reset) by setting the RST OSC FAIL (GLBCTRL.15) and the OSC FAIL flag (GLBSTAT.1) bits equal
to 1. For more detailed information on these bits and device resets, see the TMS470R1x System Module Reference Guide (literature number
SPNU189).
switching characteristics over recommended operating conditions for clocksद
PARAMETER
MIN
MAX
UNIT
f(SYS)
System clock frequency
20
MHz
f(ICLK)
Interface clock frequency
20
MHz
f(ECLK)
External clock output frequency for ECP Module
20
MHz
tc(SYS)
Cycle time, system clock
50
ns
tc(ICLK)
Cycle time, interface clock
50
ns
tc(ECLK)
Cycle time, ECP module external clock output
50
ns
‡ f(SYS) = f(OSC) / R, where R = {1,2,3,4,5,6,7,8}.
§ f(ICLK) = f(SYS) / X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0.[4:1] bits
in the SYS module.
¶ f(ECLK) = f(ICLK) / N, where N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL.[7:0] register bits in the ECP module.
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25
TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
clock divider module (CDM) specifications (continued)
switching characteristics over recommended operating conditions for external clocks
(see Figure 5 and Figure 6)†‡§
NO.
PARAMETER
TEST CONDITIONS
MIN
¶
SYSCLK or MCLK
1
tw(COL)
ICLK, X is even or 1#
Pulse duration, CLKOUT low
0.5tc(ICLK) – tf
ICLK, X is odd and not
1#
tw(COH)
Pulse duration, CLKOUT high
ICLK, X is even or 1
tw(EOL)
Pulse duration, ECLK low
4
tw(EOH)
Pulse duration, ECLK high
ns
0.5tc(SYS) – tr
#
0.5tc(ICLK) – tr
ICLK, X is odd and not
3
UNIT
0.5tc(ICLK) + 0.5tc(SYS) – tf
SYSCLK or MCLK¶
2
MAX
0.5tc(SYS) – tf
1#
ns
0.5tc(ICLK) – 0.5tc(SYS) – tr
N is even and X is even or odd
0.5tc(ECLK) – tf
N is odd and X is odd and not 1
0.5tc(ECLK) + 0.5tc(SYS) – tf
N is even and X is even or odd
0.5tc(ECLK) – tr
N is odd and X is odd and not 1
0.5tc(ECLK) – 0.5tc(SYS) – tr
ns
ns
† X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0.[4:1] bits in the SYS module.
‡ N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL.[7:0] register bits in the ECP module.
§ CLKOUT/ECLK pulse durations (low/high) are a function of the OSCIN pulse durations.
¶ Clock source bits selected as either SYSCLK (CLKCNTL.[6:5] = 11 binary) or MCLK (CLKCNTL.[6:5] = 10 binary).
# Clock source bits selected as ICLK (CLKCNTL.[6:5] = 01 binary).
2
CLKOUT
1
Figure 5. CLKOUT Timing Diagram
4
ECLK
3
Figure 6. ECLK Timing Diagram
26
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TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
RST and PORRST timings
timing requirements for PORRST (see Figure 7)
NO.
MIN
VCCPORL
VCC low supply level when PORRST must be active during power up
VCCPORH
VCC high supply level when PORRST must remain active during power up and
become active during power down
VCCIOPORL
VCCIO low supply level when PORRST must be active during power up
VIL
Low-level input voltage after VCCIO > VCCIOPORH
VIL(PORRST)
Low-level input voltage of PORRST before VCCIO > VCCIOPORL
MAX
UNIT
0.6
1.5
V
V
1.1
V
0.2 VCC
V
0.5
V
3
tsu(PORRST)r
Setup time, PORRST active before VCCIO > VCCIOPORL during power up
0
ms
5
tsu(VCCIO)r
Setup time, VCCIO > VCCIOPORL before VCC > VCCPORL
0
ms
6
th(PORRST)r
Hold time, PORRST active after VCC > VCCPORH
1
ms
7
tsu(PORRST)f
Setup time, PORRST active before VCC ≤ VCCPORH during power down
8
µs
8
th(PORRST)rio
Hold time, PORRST active after VCC > VCCIOPORH
1
ms
9
th(PORRST)d
Hold time, PORRST active after VCC < VCCPORL
0
ms
10
tsu(PORRST)fio
Setup time, PORRST active before VCC ≤ VCCIOPORH during power down
0
ns
11
tsu(VCCIO)f
Setup time, VCC < VCCPORE before VCCIO < VCCIOPORL
0
ns
3.3 V
VCCIOPORH
VCCIOPORH
VCCIO
8
11
1.8 V
VCC
VCCPORH
6
VCCIOPORL
VCC (1.8 V)
VCCP/VCCIO (3.3 V)
PORRST
VCCPORH
7
6
10
7
VCCPORL
VCCPORL
VCCIOPORL
5
3
9
VIL(PORRST)
VIL
VIL
VIL
VIL
VIL(PORRST)
Figure 7. PORRST Timing Diagram
switching characteristics over recommended operating conditions for RST†
PARAMETER
tv(RST)
MIN
4112tc(OSC)
Valid time, RST active after PORRST inactive
8tc(SYS)
Valid time, RST active (all others)
MAX
UNIT
ns
† Specified values do NOT include rise/fall times. For rise and fall timings, see the switching characteristics for output timings versus load
capacitance table.
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TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
JTAG scan interface timing (JTAG clock specification 10-MHz and 50-pF load on TDO output)
MIN
MAX
UNIT
tc(JTAG)
Cycle time, JTAG low and high period
50
ns
tsu(TDI/TMS - TCKr)
Setup time, TDI, TMS before TCK rise (TCKr)
15
ns
th(TCKr -TDI/TMS)
Hold time, TDI, TMS after TCKr
15
ns
th(TCKr -TDO)
Hold time, TDO after TCKr
10
th(TCKf -TDO)
Hold time, TDO valid after TCK fall (TCKf)
28
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45
• HOUSTON, TEXAS 77251-1443
ns
TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
input and output timings
switching characteristics for output timings versus load capacitance (CL) (see Figure 8)
PARAMETER
tr
tf
tf
tr
tf
Rise time, CLKOUT, AWD, TDO
Fall time, CLKOUT, AWD, TDO
Fall time, RST
Rise time, all other output pins
Fall time, all other output pins
MIN
MAX
CL = 15 pF
0.5
2.5
CL = 50 pF
1.5
5
CL = 100 pF
3
9
CL = 150 pF
4.5
12.5
CL = 15 pF
0.5
2.5
CL = 50 pF
1.5
5
CL = 100 pF
3
9
CL = 150 pF
4.5
12.5
CL = 15 pF
2.5
8
CL= 50 pF
5
14
CL = 100 pF
9
23
CL = 150 pF
13
32
CL = 15 pF
2.5
10
CL = 50 pF
6.0
25
CL = 100 pF
12
45
CL = 150 pF
18
65
CL = 15 pF
3
10
CL = 50 pF
8.5
25
CL = 100 pF
16
45
CL = 150 pF
23
65
tr
ns
ns
ns
ns
ns
tf
80%
Output
UNIT
VCC
80%
20%
20%
0
Figure 8. CMOS-Level Outputs
timing requirements for input timings† (see Figure 9)
MIN
tpw
tc(ICLK) + 10
Input minimum pulse width
MAX
UNIT
ns
† tc(ICLK) = interface clock cycle time = 1/f(ICLK)
tpw
Input
80%
VCC
80%
20%
20%
0
Figure 9. CMOS-Level Inputs
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TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
SPIn master mode timing parameters
SPIn master mode external timing parameters (CLOCK PHASE = 0, SPInCLK = output, SPInSIMO =
output, and SPInSOMI = input)†‡§ (see Figure 10)
NO.
1
2#
3#
MIN
¶
MAX
UNIT
ns
tc(SPC)M
Cycle time, SPInCLK
100
256tc(ICLK)
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
td(SPCH-SIMO)M
Delay time, SPInCLK high to SPInSIMO valid
(clock polarity = 0)
10
td(SPCL-SIMO)M
Delay time, SPInCLK low to SPInSIMO valid
(clock polarity = 1)
10
tv(SPCL-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK low
(clock polarity = 0)
tc(SPC)M – 5 – tf
tv(SPCH-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 1)
tc(SPC)M – 5 – tr
tsu(SOMI-SPCL)M
Setup time, SPInSOMI before SPInCLK low
(clock polarity = 0)
12
tsu(SOMI-SPCH)M
Setup time, SPInSOMI before SPInCLK high
(clock polarity = 1)
12
tv(SPCL-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK low
(clock polarity = 0)
10
tv(SPCH-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 1)
10
4#
5#
6#
7#
ns
ns
ns
ns
ns
ns
† The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
‡ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
§ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
¶ When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255:
tc(SPC)M ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
For PS values of 0:
tc(SPC)M = 2tc(ICLK) ≥ 100 ns.
# The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
30
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SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
SPIn master mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSIMO
Master Out Data Is Valid
6
7
SPInSOMI
Master In Data
Must Be Valid
Figure 10. SPIn Master Mode External Timing (CLOCK PHASE = 0)
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TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
SPIn master mode timing parameters (continued)
SPIn master mode external timing parameters (CLOCK PHASE = 1, SPInCLK = output, SPInSIMO =
output, and SPInSOMI = input)†‡§ (see Figure 11)
NO.
1
2#
3#
tc(SPC)M
Cycle time, SPInCLK
¶
MIN
MAX
UNIT
100
256tc(ICLK)
ns
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
tv(SIMO-SPCH)M
Valid time, SPInSIMO data valid before SPInCLK high
(clock polarity = 0)
0.5tc(SPC)M – 10
tv(SIMO-SPCL)M
Valid time, SPInSIMO data valid before SPInCLK low
(clock polarity = 1)
0.5tc(SPC)M – 10
tv(SPCH-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 0)
0.5tc(SPC)M – 5 – tr
tv(SPCL-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK low
(clock polarity = 1)
0.5tc(SPC)M – 5 – tf
tsu(SOMI-SPCH)M
Setup time, SPInSOMI before SPInCLK high
(clock polarity = 0)
12
tsu(SOMI-SPCL)M
Setup time, SPInSOMI before SPInCLK low
(clock polarity = 1)
12
tv(SPCH-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 0)
10
tv(SPCL-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK low
(clock polarity = 1)
10
4#
5#
6#
7#
ns
ns
ns
ns
ns
ns
† The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is set.
‡ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
§ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
¶ When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255:
tc(SPC)M ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
For PS values of 0:
tc(SPC)M = 2tc(ICLK) ≥ 100 ns.
# The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
32
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16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
SPIn master mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSIMO
Master Out Data Is Valid
Data Valid
6
7
SPInSOMI
Master In Data
Must Be Valid
Figure 11. SPIn Master Mode External Timing (CLOCK PHASE = 1)
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TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
SPIn slave mode timing parameters
SPIn slave mode external timing parameters (CLOCK PHASE = 0, SPInCLK = input, SPInSIMO =
input, and SPInSOMI = output)†‡§¶ (see Figure 12)
NO.
1
#
MIN
MAX
UNIT
ns
tc(SPC)S
Cycle time, SPInCLK
100
256tc(ICLK)
tw(SPCH)S
Pulse duration, SPInCLK high
(clock polarity = 0)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low
(clock polarity = 1)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low
(clock polarity = 0)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCH)S
Pulse duration, SPInCLK high
(clock polarity = 1)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
td(SPCH-SOMI)S
Delay time, SPInCLK high to SPInSOMI valid
(clock polarity = 0)
12 + tr
td(SPCL-SOMI)S
Delay time, SPInCLK low to SPInSOMI valid
(clock polarity = 1)
12 + tf
tv(SPCH-SOMI)S
Valid time, SPInSOMI data valid after
SPInCLK high (clock polarity =0)
tc(SPC)S – 12 – tr
tv(SPCL-SOMI)S
Valid time, SPInSOMI data valid after
SPInCLK low (clock polarity =1)
tc(SPC)S – 12 – tf
tsu(SIMO-SPCL)S
Setup time, SPInSIMO before SPInCLK low
(clock polarity = 0)
10
tsu(SIMO-SPCH)S
Setup time, SPInSIMO before SPInCLK high
(clock polarity = 1)
10
tv(SPCL-SIMO)S
Valid time, SPInSIMO data valid after
SPInCLK low (clock polarity = 0)
10
tv(SPCH-SIMO)S
Valid time, SPInSIMO data valid after
SPInCLK high (clock polarity = 1)
10
2||
3||
4||
5||
6||
7||
ns
ns
ns
ns
ns
ns
† The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
‡ If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1.[12:5].
§ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
¶ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
# When the SPIn is in Slave mode, the following must be true:
For PS values from 1 to 255:
tc(SPC)S ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
For PS values of 0:
tc(SPC)S = 2tc(ICLK) ≥ 100 ns.
||
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
34
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16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
SPIn slave mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSOMI
SPISOMI Data Is Valid
6
7
SPInSIMO
SPISIMO Data
Must Be Valid
Figure 12. SPIn Slave Mode External Timing (CLOCK PHASE = 0)
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TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
SPIn slave mode timing parameters (continued)
SPIn slave mode external timing parameters (CLOCK PHASE = 1, SPInCLK = input, SPInSIMO =
input, and SPInSOMI = output)†‡§¶ (see Figure 13)
NO.
1
MIN
MAX
UNIT
100
256tc(ICLK)
ns
Pulse duration, SPInCLK high
(clock polarity = 0)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low
(clock polarity = 1)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low
(clock polarity = 0)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCH)S
Pulse duration, SPInCLK high
(clock polarity = 1)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tv(SOMI-SPCH)S
Valid time, SPInSOMI data valid before
SPInCLK high (clock polarity = 0)
0.5tc(SPC)S – 12 – tr
tv(SOMI-SPCL)S
Valid time, SPInSOMI data valid before
SPInCLK low (clock polarity = 1)
0.5tc(SPC)S – 12 – tf
tv(SPCH-SOMI)S
Valid time, SPInSOMI data valid after
SPInCLK high (clock polarity =0)
0.5tc(SPC)S – 12 – tr
tv(SPCL-SOMI)S
Valid time, SPInSOMI data valid after
SPInCLK low (clock polarity =1)
0.5tc(SPC)S – 12 – tf
tsu(SIMO-SPCH)S
Setup time, SPInSIMO before SPInCLK
high (clock polarity = 0)
10
tsu(SIMO-SPCL)S
Setup time, SPInSIMO before SPInCLK
low (clock polarity = 1)
10
tv(SPCH-SIMO)S
Valid time, SPInSIMO data valid after
SPInCLK high (clock polarity = 0)
10
tv(SPCL-SIMO)S
Valid time, SPInSIMO data valid after
SPInCLK low (clock polarity = 1)
10
#
tc(SPC)S
Cycle time, SPInCLK
tw(SPCH)S
2||
3||
4||
5||
6||
7||
ns
ns
ns
ns
ns
ns
† The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is set.
‡ If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1.[12:5].
§ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
¶ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
# When the SPIn is in Slave mode, the following must be true:
For PS values from 1 to 255:
tc(SPC)S ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
For PS values of 0:
tc(SPC)S = 2tc(ICLK) ≥ 100 ns.
||
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
36
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16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
SPIn slave mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSOMI
SPISOMI Data Is Valid
Data Valid
6
7
SPInSIMO
SPISIMO Data Must
Be Valid
Figure 13. SPIn Slave Mode External Timing (CLOCK PHASE = 1)
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TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
MECHANICAL DATA
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
0,08 M
51
76
50
100
26
1
0,13 NOM
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
16,20
SQ
15,80
0,05 MIN
1,45
1,35
0,25
0°-7°
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149/B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
Thermal Resistance Characteristics
PARAMETER
°C/W
RΘJA
51
RΘJC
38
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TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
List of Figures
TMS470R1VC002 100-Pin PZ Package (TOP VIEW)
Functional Block Diagram
Figure 1. Memory Map
Figure 2. TMS470R1x Family Nomenclature
Figure 3. Test Load Circuit
Figure 4. Recommended Crystal/Clock Connection
Figure 5. CLKOUT Timing Diagram
Figure 6. ECLK Timing Diagram
Figure 7. PORRST Timing Diagram
Figure 8. CMOS-Level Outputs
Figure 9. CMOS-Level Inputs
Figure 10. SPIn Master Mode External Timing (CLOCK PHASE = 0)
Figure 11. SPIn Master Mode External Timing (CLOCK PHASE = 1)
Figure 12. SPIn Slave Mode External Timing (CLOCK PHASE = 0)
Figure 13. SPIn Slave Mode External Timing (CLOCK PHASE = 1)
Mechanical Data
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TMS470R1VC002
16/32-BIT RISC ROM MICROCONTROLLER
SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
40
Device Characteristics
Memory Selection Assignment
VC002 Peripherals and System Module Addresses
Interrupt Priority
Code Development Tools
Debug Tools
Hardware Tools
TMS470 Device ID Bit Allocation Register
Device Part Number
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16/32-BIT RISC ROM MICROCONTROLLER
REVISION HISTORY
REVISION HISTORY
REV
B
DATE
10/02
AUTHOR
R. Haley
NOTES
Updates:’
Page 8, Pull-down added to TRST and CLKOUT pins
Page 20, VCC min changed to 1.71 V
Page 21, VCC changed to 2.05 V in ICC test conditions
Page 21, ICCIO Standby changed to 100µA
Typographical Changes:
Page 25 and 26, VCC corrected to VCCIO in table note
A
9/02
R. Haley
*
11/01
R. Haley
Updates:
Throughout,Names of Reference Guides updated
Throughout, 1.4mm thickness plastic quad flatpacks referred to as LQFP
Page 8, Option to leave TEST pin disconnected removed from description
Page 15 and 16, development system support updated
Page 20, VCC max changed to 2.05 V, nom value deleted
Page 21, VCC changed to 2.05 V throughout table
Page 21, note concerning VIL value for the PORRST pin added
Initial version
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