SCDS106E − APRIL 2000 − REVISED SEPTEMBER 2003
D Member of the Texas Instruments
D
D
D
D
D Flow-Through Architecture Optimizes PCB
Widebus+ Family
5-Ω Switch Connection Between Two Ports
TTL-Compatible Input Levels
Ioff Supports Partial-Power-Down Mode
Operation
Active-Clamp Undershoot-Protection
Circuit on the I/Os Clamps Undershoots Up
To −2 V
D
D
Layout
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
The SN74CBTK32245 provides 32 bits of high-speed TTL-compatible bus switching. The low on-state
resistance of the switch allows connections to be made with minimal propagation delay.
The A and B ports have an active-clamp undershoot-protection circuit. When there is an undershoot, the
active-clamp circuit is enabled and current from VCC is supplied to clamp the output, preventing the pass
transistor from turning on.
The device is organized as four 8-bit bus switches, two 16-bit bus switches, or one 32-bit bus switch. When the
output-enable (OE) input is low, the switch is on and port A is connected to port B. When OE is high, the switch
is open and the high-impedance state exists between the two ports.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
−40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
LFBGA − GKE
LFBGA − ZKE (Pb-free)
Tape and reel
SN74CBTK32245GKER
SN74CBTK32245ZKER
TOP-SIDE
MARKING
KT245
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
(each 8-bit bus switch)
INPUT
OE
FUNCTION
L
A port = B port
H
Disconnect
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
Copyright 2003, Texas Instruments Incorporated
!"# $ %&'# "$ (&)*%"# +"#',
+&%#$ %! # $('%%"#$ (' #-' #'!$ '."$ $#&!'#$
$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+'
#'$#1 "** (""!'#'$,
POST OFFICE BOX 655303
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1
SCDS106E − APRIL 2000 − REVISED SEPTEMBER 2003
GKE OR ZKE PACKAGE
(TOP VIEW)
1
3
4
5
terminal assignments
6
1
2
3
4
5
6
A
A
1B2
1B1
NC
1OE
1A1
1A2
B
B
1B4
1B3
GND
GND
1A3
1A4
C
C
1B6
1B5
1A6
D
1B8
1B7
VCC
GND
1A5
D
VCC
GND
1A7
1A8
E
2B2
2B1
GND
GND
2A1
2A2
F
2B4
2B3
2A4
2B6
2B5
VCC
GND
2A3
G
VCC
GND
2A5
2A6
H
2B7
2B8
NC
2OE
2A8
2A7
J
3B2
3B1
NC
3OE
3A1
3A2
E
F
G
H
J
K
3B4
3B3
GND
GND
3A3
3A4
K
L
3B6
3B5
3A6
M
3B8
3B7
VCC
GND
3A5
L
VCC
GND
3A7
3A8
M
N
4B2
4B1
GND
GND
4A1
4A2
N
P
4B4
4B3
4A4
R
4B6
4B5
VCC
GND
4A3
P
VCC
GND
4A5
4A6
R
T
4B7
4B8
NC
4OE
4A8
4A7
T
2
2
NC − No internal connection
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SCDS106E − APRIL 2000 − REVISED SEPTEMBER 2003
logic diagram (positive logic)
1A1
VCC
VCC
VCC
VCC
UC†
UC†
UC†
UC†
A5
A2
1B1
2A1
E2
VCC
VCC
VCC
VCC
UC†
UC†
UC†
UC†
D6
D1
1A8
H5
1B8
2B1
H2
2B8
2A8
A4
H4
2OE
1OE
3A1
E5
VCC
VCC
VCC
VCC
UC†
UC†
UC†
UC†
J5
M6
3A8
J2
3B1
4A1
N2
N5
VCC
VCC
VCC
VCC
UC†
UC†
UC†
UC†
M1
3B8
4A8
T5
T2
4B1
4B8
T4
J4
3OE
4OE
† Undershoot clamp
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Package thermal impedance, θJA (see Note 2): GKE/ZKE package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
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3
SCDS106E − APRIL 2000 − REVISED SEPTEMBER 2003
recommended operating conditions (see Note 3)
MIN
MAX
5.5
VCC
VIH
Supply voltage
4
High-level control input voltage
2
VIL
TA
Low-level control input voltage
Operating free-air temperature
−40
UNIT
V
V
0.8
V
85
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to TI application report
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
VIKU
VCC = 4.5 V,
VCC = 5.5 V,
II = −18 mA
0 mA ≥ II ≥ −50 mA,
II
Ioff
VCC = 5.5 V,
VCC = 0,
VI = 5.5 V or GND
VI or VO = 0 to 5.5 V
VCC = 5.5 V,
VCC = 5.5 V,
VI = VCC or GND,
One input at 3.4 V,
ICC
∆ICC‡
Control inputs
Ci
Control inputs
Cio(OFF)
VI = 3 V or 0
VO = 3 V or 0,
MIN
OE = 5.5 V
IO = 0
Other inputs at VCC or GND
OE = VCC
VCC = 4 V,
TYP at VCC = 4 V
ron§
VCC = 4.5 V
TYP†
MAX
UNIT
−1.2
V
−2
V
±5
µA
20
µA
6
µA
3.5
mA
3.5
pF
5.5
pF
VI = 2.4 V,
II = 15 mA
14
20
II = 64 mA
II = 30 mA
5
7
VI = 0
5
7
Ω
VI = 2.4 V,
II = 15 mA
8
12
† All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.
‡ This is the increase in supply current for each input that is at the specified TTL-voltage level, rather than VCC or GND.
§ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 3)
VCC = 4 V
VCC = 5 V
± 0.5 V
MIN
MIN
FROM
(INPUT)
TO
(OUTPUT)
tpd¶
A or B
B or A
0.35
ten
OE
A or B
7.4
PARAMETER
MAX
1.6
UNIT
MAX
0.25
ns
4.9
ns
tdis
A or B
7.4
4.2
7.5
ns
OE
¶ The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
4
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SCDS106E − APRIL 2000 − REVISED SEPTEMBER 2003
undershoot characteristics
PARAMETER
TEST CONDITIONS
VOUTU
See Figures 1 and 2, and Table 1
† All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.
VCC
MIN
TYP†
2
VOH−0.3
MAX
UNIT
V
VTR
R1
50 Ω
DUT
VIN
R2
10 pF
5.5 V
0V
−2 V
Figure 1. Device Test Setup
Figure 2. Transient Input Voltage Waveform
Table 1. Device Test Conditions
PARAMETER
VALUE
B port under test‡
UNIT
See Figure 1
VIN
tw
See Figure 2
V
20
ns
tr
tf
2
ns
2
ns
R1 = R2
100
kΩ
VTR
VCC
11
V
5.5
V
‡ Other B-port outputs are open
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5
SCDS106E − APRIL 2000 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
7V
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
3V
Output
Control
LOAD CIRCUIT
1.5 V
1.5 V
0V
tPLZ
tPZL
3V
Input
1.5 V
1.5 V
0V
tPLH
1.5 V
3.5 V
1.5 V
1.5 V
VOL
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOL + 0.3 V
VOL
tPHZ
tPZH
tPHL
VOH
Output
Output
Waveform 1
S1 at 7 V
(see Note B)
1.5 V
VOH
VOH − 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
6
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74CBTK32245GKER
ACTIVE
LFBGA
GKE
96
1000
SN74CBTK32245ZKER
ACTIVE
LFBGA
ZKE
96
1000 Green (RoHS &
no Sb/Br)
TBD
Lead/Ball Finish
MSL Peak Temp (3)
SNPB
Level-3-220C-168 HR
SNAGCU
Level-3-250C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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