SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
www.ti.com
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
DIFFERENTIAL TRANSLATOR/REPEATER
FEATURES
•
•
•
•
•
•
•
•
•
DESCRIPTION
Designed for Signaling Rates ≥ 2 Gbps
Total Jitter < 65 ps
Low-Power Alternative for the MC100EP16
Low 100 ps (Max) Part-To-Part Skew
25 mV of Receiver Input Threshold Hysteresis
Over 0-V to 4-V Common-Mode Range
Inputs Electrically Compatible With LVPECL,
CML, and LVDS Signal Levels
3.3-V Supply Operation
LVDT Integrates 110-Ω Terminating Resistor
Offered in SOIC and MSOP
(1)
The SN65LVDS100, SN65LVDT100, SN65LVDS101,
and SN65LVDT101 are a high-speed differential receiver and driver connected as a repeater. The
receiver accepts low-voltage differential signaling
(LVDS), positive-emitter-coupled logic (PECL), or current-mode logic (CML) input signals at rates up to 2
Gbps and repeats it as either an LVDS or PECL
output signal. The signal path through the device is
differential for low radiated emissions and minimal
added jitter.
The
outputs
of
the
SN65LVDS100
and
SN65LVDT100 are LVDS levels as defined by
TIA/EIA-644-A. The outputs of the SN65LVDS101
and SN65LVDT101 are compatible with 3.3-V PECL
levels. Both drive differential transmission lines with
nominally 100-Ω characteristic impedance.
APPLICATIONS
•
•
•
•
•
622 MHz Central Office Clock Distribution
High-Speed Network Routing
Wireless Basestations
Low Jitter Clock Repeater
Serdes LVPECL Output to FPGA LVDS
Input Translator
(1)
The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
FUNCTIONAL DIAGRAM
The SN65LVDT100 and SN65LVDT101 include a
110-Ω differential line termination resistor for less
board space, fewer components, and the shortest
stub length possible. They do not include the VBB
voltage reference found in the SN65LVDS100 and
SN65LVDS101. VBB provides a voltage reference of
typically 1.35 V below VCC for use in receiving
single-ended input signals and is particularly useful
with single-ended 3.3-V PECL inputs. When not used,
VBB should be unconnected or open.
All devices are characterized for operation from
–40°C to 85°C.
EYE PATTERN
SN65LVDS100 and SN65LVDS101
VCC
A
8
4
2
7
6
B
VBB
3
SN65LVDT100 and SN65LVDT101
2
A
7
110 Ω
6
3
B
Y
Z
2 Gbps
223 - 1 PRBS
VCC = 3.3 V
VID = 200 mV
VIC = 1.2 V
Vert.Scale= 200 mV/div
1 GHz
Y
Z
Horizontal Scale= 200 ps/div
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
Copyright © 2002–2004, Texas Instruments Incorporated
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
www.ti.com
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION
PART NUMBER (1)
OUTPUT
TERMINATION RESISTOR
VBB
LVDS
No
Yes
SN65LVDS100D
LVDS
No
Yes
SN65LVDS100DGK
LVDS
Yes
No
SN65LVDT100D
LVDS
Yes
No
SN65LVDT100DGK
LVPECL
No
Yes
SN65LVDS101D
LVPECL
No
Yes
SN65LVDS101DGK
LVPECL
Yes
No
SN65LVDT101D
LVPECL
Yes
No
SN65LVDT101DGK
(1)
PART MARKING
PACKAGE
DL100
SOIC
AZK
MSOP
DE100
SOIC
AZL
MSOP
DL101
SOIC
AZM
MSOP
DE101
SOIC
BAF
MSOP
Add the suffix R for taped and reeled carrier (i.e. SN65LVDS100DR).
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range unless otherwise noted
UNIT
VCC
Supply voltage range (2)
IBB
VBB Output current
VI
VO
VID
–0.5 V to 4 V
±0.5 mA
Voltage range, (A, B, Y, Z)
0 V to 4.3 V
Differential voltage, |VA– VB| ('LVDT100 and 'LVDT101 only)
Charged-Device Model (4)
PD
(1)
(2)
(3)
(4)
±5 kV
A, B, Y, Z, and GND
Human Body Model (3)
ESD
1V
All pins
±2 kV
All pins
±1500 V
Continuous power dissipation
See Dissipation Rating Table
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-A.7.
Tested in accordance with JEDEC Standard 22, Test Method C101.
POWER DISSIPATION RATINGS
(1)
2
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR (1)
ABOVE TA = 25°C
TA = 85°C
POWER RATING
DGK
377 mW
3.8 mW/°C
151 mW
D
481 mW
4.8 mW/°C
192 mW
This is the inverse of the junction-to-ambient thermal resistance with no air flow installed on the JESD51-3 low effective thermal
conductivity test board for leadless surface mount packages.
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
www.ti.com
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
RECOMMENDED OPERATING CONDITIONS
MIN NOM
Supply voltage, VCC
3
Magnitude of differential input voltage |VID|
3.6
'LVDS100 or 'LVDS101
0.1
1
'LVDT100 or 'LVDT101
0.1
0.8
Input voltage (any combination of common-mode or input signals), VI
VBB output current, IO(VBB)
Operating free-air temperature, TA
(1)
MAX UNIT
3.3
V
V
0
4
V
–400 (1)
12
µA
–40
85
°C
The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet.
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise specified)
PARAMETER
ICC
PD
VBB
TEST CONDITIONS
MIN
TYP
(1)
MAX
Supply current, 'LVDx100
No load or input
25
30
Supply current, 'LVDx101
RL = 50 Ω to 1 V, No input
50
61
Device power dissipation, 'LVDx100
RL = 100 Ω, No input
Device power dissipation, 'LVDx101
Y and Z to VCC - 2 V through 50 Ω,
No input
Reference voltage output, 'LVDS100 or
'LVDS101
IO = –400 µA or 12 µA
UNIT
mA
110
116
142
VCC–1.4 VCC–1.35
VCC–1.3
mW
mV
SN65LVDS100 and SN65LVDS101 INPUT CHARACTERISTICS (see Figure 1)
Positive-going differential input voltage
threshold
VIT+
VIT-
Negative-going differential input voltage
threshold
II
Input current
100
See Figure 1 and Table 1
mV
–100
VI = 0 V or 2.4 V,
Second input at 1.2 V
–20
VI = 4 V, Second input at 1.2 V
II(OFF)
Power off input current
VCC = 1.5 V, VI = 0 V or 2.4 V,
Second input at 1.2 V
–20
Input offset current (|IIA - IIB|)
VIA = VIB, 0≤ VIA ≤ 4 V
Ci
Small-signall input capacitance to GND
VI = 1.2 V
µA
33
µA
20
µA
VCC= 1.5 V, VI = 4 V,
Second input at 1.2 V
IIO
20
33
–6
6
0.6
µA
pF
SN65LVDT100 and SN65LVDT101 INPUT CHARACTERISTICS (see Figure 1)
Positive-going differential input voltage
threshold
VIT+
VIT-
Negative-going differential input voltage
threshold
II
Input current
II(OFF)
R(T)
Ci
(1)
Power off input current
Differential input resistance
Small-signall differential input capacitance
100
See Figure 1 and Table 1
mV
–100
VI = 0 V or 2.4 V, Other input open
–40
40
VI = 4 V, Other input open
VCC = 1.5 V, VI = 0 V or 2.4 V,
Other input open
66
–40
40
µA
VCC= 1.5 V, VI = 4 V, Other input
open
66
VID = 300 mV or 500 mV, VIC = 0 V
or 2.4 V
90
110
132
VCC= 0 V, VID = 300 mV or 500 mV,
VIC = 0 V or 2.4 V
90
110
132
VI = 1.2 V
µA
Ω
0.6
pF
Typical values are with a 3.3-V supply voltage and room temperature
3
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
www.ti.com
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditions (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
(1)
MAX
340
454
TYP
UNIT
SN65LVDS100 and SN65LVDT100 OUTPUT CHARACTERISTICS (see Figure 1)
|VOD|
Differential output voltage magnitude
∆|VOD|
Change in differential output voltage magnitude between logic states
247
VOC(SS)
Steady-state common-mode output voltage
∆VOC(SS)
Change in steady-state common-mode output
voltage between logic states
VOC(PP)
Peak-to-peak common-mode output voltage
IOS
Short-circuit output current
VO(Y) or VO(Z) = 0 V
IOS(D)
Differential short-circuit output current
VOD = 0 V
See Figure 2
mV
–50
50
1.125
1.375
–50
50
mV
150
mV
–24
24
mA
–12
12
mA
See Figure 3
50
V
SN65LVDS101 and SN65LVDT101 OUTPUT CHARACTERISTICS (see Figure 1)
50 Ω to VCC– 2 V, See Figure 4
VOH
High-level output voltage
VOL
Low-level output voltage
|VOD|
Differential output voltage magnitude
VCC–1.25 VCC–1.02
VCC = 3.3 V, 50-Ω load to 2.3 V
50 Ω to VCC - 2 V, See Figure 4
2055
VCC–0.9
2280
2405
V
mV
VCC–1.83 VCC–1.61 VCC–1.53
VCC = 3.3 V, 50-Ω load to 2.3 V
V
1475
1690
1775
mV
475
575
750
mV
50-Ω load to VCC– 2 V, SeeFigure 4
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay time,
low-to-high-level output
'LVDx100
tPHL
Propagation delay time,
high-to-low-level output
'LVDx100
tr
Differential output signal rise time (20%–80%)
tf
Differential output signal fall time (20%–80%)
tsk(p)
Pulse skew (|tPHL– tPLH|)
tjit(per) RMS period
tjit(cc)
tjit(pp)
(4)
(5)
(6)
4
470
800
'LVDx101
400
630
900
300
470
800
400
630
900
See Figure 5
jitter (4)
Peak cycle-to-cycle jitter (5)
Peak-to-peak jitter
UNIT
ps
ps
220
ps
220
ps
50
ps
100
ps
1
3.7
ps
6
23
ps
2 GHz PRBS, 223–1 run length, VID = 200 mV,
VIC = 1.2 V, See Figure 6
28
65
ps
2 GHz PRBS, 27–1 run length, VID = 200 mV,
VIC = 1.2 V, See Figure 6
17
48
ps
(2)
tjit(det) Peak-to-peak deterministic jitter (6)
(1)
(2)
(3)
300
'LVDx100
tsk(pp) Part-to-part skew (3)
MIN TYP (1) MAX
5
VID = 0.2 V, See Figure 5
1 GHz 50% duty cycle square wave input,
VID = 200 mV, VIC = 1.2 V, See Figure 6
All typical values are at 25°C and with a 3.3 V supply.
tsk(p) is the magnitude of the time difference between the tPLH and tPHL of any output of a single device.
tsk(pp) is the magnitude of the time difference in propagation delay time between any specified terminals of two devices when both
devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
Period jitter is the deviation in cycle time of a signal with respect to the ideal period over a random sample of 1000,000 cycles.
Cycle-to-cycle jitter is the variation in cycle time of a signal between adjacent cycles, over a random sample of 1,000 adjacent cycle
pairs.
Deterministic jitter is the sum of pattern-dependent jitter and pulse-width distortion.
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
www.ti.com
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
PARAMETER MEASUREMENT INFORMATION
IIA
VID
VIC
VIA+VIB
Y
B
Z
IO
VBB
VOD
VIA
VO(Y)
VIB
2
A
+
VBB
-
VOC
VO(Z)
IIB
Figure 1. Voltage and Current Definitions
Table 1. Receiver Input Voltage Threshold Test
APPLIED VOLTAGES
(1)
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMONMODE INPUT VOLTAGE
OUTPUT (1)
VIA
VIB
VID
VIC
1.25 V
1.15 V
100 mV
1.2 V
1.15 V
1.25 V
–100 mV
1.2 V
L
4.0 V
3.9 V
100 mV
3.95 V
H
3.9 V
4. 0 V
–100 mV
3.95 V
L
0.1 V
0.0 V
100 mV
0.05 V
H
0.0 V
0.1 V
–100 mV
0.05 V
L
1.7 V
0.7 V
1000 mV
1.2 V
H
0.7 V
1.7 V
–1000 mV
1.2 V
L
4.0 V
3.0 V
1000 mV
3.5 V
H
3.0 V
4.0 V
–1000 mV
3.5 V
L
1.0 V
0.0 V
1000 mV
0.5 V
H
0.0 V
1.0 V
–1000 mV
0.5 V
L
H
H = high level, L = low level
3.74 kΩ
Y
VOD
Z
+
_
100 Ω
0 V ≤ V(test) ≤ 2.4 V
3.74 kΩ
Figure 2. SN65LVDx100 Differential Output Voltage (VOD) Test Circuit
A
Y
A
1.4 V
B
1.0 V
49.9 Ω ±1%
VID
VOC(PP)
B
Z
49.9 Ω ±1%
1 pF
VOC
VOC(SS)
VOC
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 0.25 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T. The measurement of VOC(PP) is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions for the SN65LVDx100 Driver Common-Mode Output Voltage
5
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
www.ti.com
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
VOY
+
VOD
VOZ
50 Ω
50 Ω
+
-
VCC - 2V
Figure 4. Typical Termination for LVPECL Output Driver (65LVDx101)
A
Y
VOD
1 pF
VID
VIA
B
100 Ω
Z
VIA
1.4 V
VIB
1V
VID
0.4 V
0V
-0.4 V
VIB
VOD
OR
50 Ω
tPHL
tPLH
100%
0V
80%
50 Ω
VOD
+
-
20%
VCC - 2V
tf
0%
tr
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 0.25 ns, pulse repetition rate
(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T. Measurement equipment provides a bandwidth of 5 GHz minimum.
Figure 5. Timing Test Circuit and Waveforms
IDEAL OUTPUT
CLOCK INPUT
0V
0V
1/fo
1/fo
Period Jitter
Cycle to Cycle Jitter
ACTUAL OUTPUT
ACTUAL OUTPUT
0V
0V
tc(n)
tc(n)
tjit(per) = |tc(n) - 1/fo|
PRBS INPUT
0V
PRBS OUTPUT
0V
tjit(pp)
Figure 6. Driver Jitter Measurement Waveforms
6
tc(n+1)
tjit(cc) = |tc(n) - tc(n+1)|
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
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SLLS516C – AUGUST 2002 – REVISED JUNE 2004
Power Supply 1
+
3.3V
-
+
Power Supply 2
1.22V
J3
DUT
GND
J2
J1
VCC
EVM
GND
J6
J4
100 J5
Agilent
E4862B
Pattern
Generator
(Note A)
J7
50 DUT
Matched
Cables
SMA to SMA
Matched
Cables
SMA to SMA
Tektronix
TDS6604
Oscilloscope
(Note B)
EVM
A.
Source jitter is subtracted from the measured values.
B.
TDS JIT3 jitter analysis software installed
50 Figure 7. Jitter Setup Connections for SN65LVDS100 and SN65LVDS101
PIN ASSIGNMENTS
SN65LVDS100 and SN65LVDS101
D AND DGK PACKAGE
(TOP VIEW)
NC
A
B
VBB
1
8
2
7
3
6
4
5
VCC
Y
Z
GND
SN65LVDT100 and SN65LVDT101
D AND DGK PACKAGE
(TOP VIEW)
NC
A
B
NC
1
8
2
7
3
6
4
5
VCC
Y
Z
GND
NC = Not Connected
FUNCTION TABLE
DIFFERENTIAL INPUT
(1)
OUTPUTS (1)
VID= VA– VB
Y
Z
L
VID ≥ 100 mV
H
–100 mV < VID < 100 mV
?
?
VID ≤ – 100 mV
L
H
Open
?
?
H = high level, L = low level, ? = indeterminate
7
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
www.ti.com
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
INPUT
VCC
VCC
B
A
VCC
110 VCC
(SN65LVDT only)
215 A
7V
215 A
7V
350 A
350 A
OUTPUT
(SN65LVDS100 and SN65LVDT100)
OUTPUT
(SN65LVDS101 and SN65LVDT101)
VCC
VCC
R
R
Y
R
Y
7V
R
Z
VCC
7V
Z
7V
7V
8
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
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SLLS516C – AUGUST 2002 – REVISED JUNE 2004
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREQUENCY
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
55
DIFFERENTIAL OUTPUT VOLTAGE
vs
FREQUENCY
60
700
V OD - Differential Output Voltage - mV
LVDS101= Loaded
50
VCC = 3.3 V
TA = 25°C
VIC = 1.2 V
VID = 200 mV
45
I CC - Supply Current - mA
35
LVDS100
25
15
0
200
400
600
800
Frequency - MHz
1000
LVDS100
20
-20
0
20
40
60
80
LVDS101
600
500
LVDS100
400
VCC = 3.3 V
TA = 25°C
VIC = 1.2 V
VID = 200 mV
300
200
100
0
200
TA - Free-Air Temperature - °C
400
600
800
1000
1200
f - Frequency - MHz
Figure 8.
Figure 9.
Figure 10.
SN65LVDS100
PROPAGATION DELAY TIME
vs
COMMON-MODE INPUT VOLTAGE
SN65LVDS101
PROPAGATION DELAY TIME
vs
COMMON-MODE INPUT VOLTAGE
SN65LVDS100
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
550
550
tPHL
500
tPLH
450
400
350
300
0
1
2
3
4
VIC - Common-Mode Input Voltage - V
650
tPLH
600
550
500
1
2
3
4
tPHL
450
400
350
0
tPLH
500
5
-40
-20
0
20
40
60
80
Figure 12.
Figure 13.
SN65LVDS101
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
SN65LVDS100
PEAK-TO-PEAK JITTER
vs
FREQUENCY
SN65LVDS100
PEAK-TO-PEAK JITTER
vs
DATA RATE
30
VCC = 3.3 V
VID = 200 mV
f = 150 MHz
Peak-To-Peak Jitter - ps
25
tPLH
600
tPHL
550
500
60
VCC = 3.3 V
TA = 25°C
VIC = 400 mV
Input = Clock
50
20
15
VID = 0.3 V
10
VID = 0.5 V
VID = 0.8 V
0
20
40
60
TA - Free-Air Temperature - °C
Figure 14.
80
100
0
200
VOC = 3.3 V
TA = 25°C
VIC = 400 mV
Input = PRBS 223-1
40
30
VID = 0.3 V
20
10
5
-20
100
TA - Free-Air Temperature - °C
Figure 11.
650
450
-40
tPHL
VCC = 3.3 V
VID = 200 mV
f = 150 MHz
VIC - Common-Mode Input Voltage - V
750
700
700
450
5
VCC = 3.3 V
TA = 25°C
VID = 200 mV
f = 150 MHz
t pd - Propagation Delay Time - ps
750
VCC = 3.3 V
TA = 25°C
VID = 200 mV
f = 150 MHz
t pd - Propagation Delay Time - ps
t pd - Propagation Delay Time - ps
30
10
-40
1200
600
t pd - Propagation Delay Time - ps
VCC = 3.3 V
VIC = 1.2 V
VID = 200 mV
f = 750 MHz
40
Peak-To-Peak Jitter - ps
I CC - Supply Current - mA
LVDS101 = Loaded
VID = 0.8 V
VID = 0.5 V
0
400
600
800
f - Frequency - MHz
Figure 15.
1000
300
800
1300
1800
Data Rate - Mbps
2300
Figure 16.
9
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
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SLLS516C – AUGUST 2002 – REVISED JUNE 2004
TYPICAL CHARACTERISTICS (continued)
SN65LVDS101
PEAK-TO-PEAK JITTER
vs
FREQUENCY
SN65LVDS101
PEAK-TO-PEAK JITTER
vs
DATA RATE
60
VCC = 3.3 V
TA = 25°C
VIC = 400 mV
Input = Clock
50
Peak-To-Peak Jitter - ps
20
15
VID = 0.8 V
10
VID = 0.3 V
40
VID = 0.5 V
VID = 0.8 V
30
20
10
5
0
200
400
600
800
0
300
1000
15
VID = 0.8 V
VID = 0.5 V
10
VID = 0.3 V
0
800
f - Frequency - MHz
1300
1800
Data Rate - Mbps
2300
200
400
600
f - Frequency - MHz
800
Figure 17.
Figure 18.
Figure 19.
SN65LVDS100
PEAK-TO-PEAK JITTER
vs
DATA RATE
SN65LVDS101
PEAK-TO-PEAK JITTER
vs
FREQUENCY
SN65LVDS101
PEAK-TO-PEAK JITTER
vs
DATA RATE
VCC = 3.3 V
TA = 25°C
VIC= 1.2 V
Input = PRBS 223-1
Peak-To-Peak Jitter - ps
40
25
VID = 0.3 V
VID = 0.8 V
VID = 0.5 V
30
20
10
VCC = 3.3 V
TA = 25°C
VIC= 1.2 V
Input = Clock
50
20
15
10
1000
60
30
60
Peak-To-Peak Jitter - ps
20
5
VID = 0.3 V
VID = 0.5 V
VCC = 3.3 V
TA = 25°C
VIC = 1.2 V
Input = Clock
25
Peak-To-Peak Jitter - ps
Peak-To-Peak Jitter - ps
25
30
VCC = 3.3 V
TA = 25°C
VIC = 400 mV
Input = PRBS 223-1
Peak-To-Peak Jitter - ps
30
50
SN65LVDS100
PEAK-TO-PEAK JITTER
vs
FREQUENCY
VID = 0.8 V
VID = 0.3 V
VID = 0.5 V
VCC = 3.3 V
TA = 25°C
VIC= 1.2 V
Input = PRBS 223-1
40
VID = 0.8 V
VID = 0.5 V
30
20
10
5
VID = 0.3 V
800
1300
1800
Data Rate - Mbps
0
200
2300
15
800
1300
1800
Data Rate - Mbps
Figure 22.
SN65LVDS100
PEAK-TO-PEAK JITTER
vs
FREQUENCY
SN65LVDS100
PEAK-TO-PEAK JITTER
vs
DATA RATE
SN65LVDS101
PEAK-TO-PEAK JITTER
vs
FREQUENCY
60
VCC = 3.3 V
TA = 25°C
VIC = 2.9 V
Input = Clock
50
VID = 0.8 V
10
25
40
VID = 0.3 V
30
VID = 0.8 V
20
400
600
800
f - Frequency - MHz
Figure 23.
VCC = 3.3 V
TA = 25°C
VIC = 2.9 V
Input = Clock
20
15
VID = 0.5 V
10
VID = 0.8 V
5
VID = 0.5 V
VID = 0.3 V
1000
0
300
2300
30
VCC = 3.3 V
TA = 25°C
VIC = 2.9 V
Input = PRBS 223-1
10
5
10
1000
Figure 21.
VID = 0.5 V
0
200
800
Figure 20.
Peak-To-Peak Jitter - ps
Peak-To-Peak Jitter - ps
20
600
f - Frequency - MHz
30
25
400
0
300
Peak-To-Peak Jitter - ps
0
300
800
1300
Data Rate - Mbps
Figure 24.
1800
2300
0
200
VID = 0.3 V
400
600
f - Frequency - MHz
Figure 25.
800
1000
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
www.ti.com
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
TYPICAL CHARACTERISTICS (continued)
SN65LVDS100
PEAK-TO-PEAK JITTER
vs
FREE-AIR TEMPERATURE
60
VID = 0.5 V
30
20
30
1800
60
LVDS101
50
VCC = 3.3 V,
VIC = 1.2 V,
|V ID| = 200 mV,
TA = 25°C,
Input = Clock
150
0
-40
40
30
100
20
50
10
Added Random Jitter
0
-20
0
20
40
60
80
TA - Free-Air Temperature - °C
0
100
500
1000
1500
2000
Figure 27.
Figure 28.
SN65LVDS100
PEAK-TO-PEAK JITTER
vs
DATA RATE
SN65LVDS101
DIFFERENTIAL OUTPUT VOLTAGE
vs
FREQUENCY
SN65LVDS101
PEAK-TO-PEAK JITTER
vs
DATA RATE
700
60
40
20
620
540
30
460
20
380
10
2000
3000
Data Rate - Mbps
Figure 29.
4000
VCC = 3.3 V,
VIC = 1.2 V,
|V ID| = 200 mV,
TA = 25°C,
Input = PRBS 223-1
80
40
60
40
20
Added Random Jitter
300
1000
100
50
VCC = 3.3 V,
VIC = 1.2 V,
|V ID| = 200 mV,
TA = 25°C,
Input = Clock
Peak-to-Peak Jitter - ps
VCC = 3.3 V,
VIC = 1.2 V,
|V ID| = 200 mV,
TA = 25°C,
Input = PRBS 223-1
0
2500
f - Frequency - MHz
Figure 26.
V OD - Differential Output Voltage - mV
Peak-to-Peak Jitter - ps
70
300
200
2300
100
0
0
80
350
250
20
Data Rate - Mbps
80
LVDS100
10
1300
800
40
Period Jitter - ps
0
300
VID = 0.8 V
VCC = 3.3 V
TA = 25°C
VIC = 2.9 V
Input = PRBS 223-1
VCC = 3.3 V
VIC = 1.2 V
VID = 200 mV
Input = 2 Gbps 223-1
V OD - Differential Output Voltage - mV
Peak-To-Peak Jitter - ps
Peak-To-Peak Jitter - ps
VID = 0.3 V
10
400
50
50
40
SN65LVDS100
DIFFERENTIAL OUTPUT VOLTAGE
vs
FREQUENCY
Period Jitter - ps
SN65LVDS101
PEAK-TO-PEAK JITTER
vs
DATA RATE
0
400
800
1200
f - Frequency - MHz
Figure 30.
1600
0
2000
0
0
1000
2000
3000
4000
5000
Data Rate - Mbps
Figure 31.
11
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
www.ti.com
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
TYPICAL CHARACTERISTICS (continued)
SN65LVDS100
622 Mbps, 223– 1 PRBS
Horizontal Scale= 200 ps/div
LVPECL-to-LVDS
Horizontal Scale= 100 ps/div
LVPECL-to-LVDS
Figure 32.
Figure 33.
SN65LVDS101
622 Mbps, 223– 1 PRBS
SN65LVDS101
2 Gbps, 223– 1 PRBS
Horizontal Scale= 200 ps/div
LVDS-to-LVPECL
Figure 34.
12
SN65LVDS100
2 Gbps, 223– 1 PRBS
Horizontal Scale= 100 ps/div
LVDS-to-LVPECL
Figure 35.
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
www.ti.com
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
TYPICAL CHARACTERISTICS (continued)
20
3.6 V, 85°C
3 V, 85°C
Input Voltage Threshold - mV
15
3.6 V, -40°C
10
VIT+
5
3 V, -40°C
0
|VOD| = 250 mV,
RL = 100 Ω,
Nominal Process
3 V, -40°C
-5
-10
VIT-
3.6 V, -40°C
-15
3.6 V, 85°C
-20
0
1
3 V, 85°C
2
3
4
Common-Mode Input Voltage - V
5
NOTE: VIT is a steady-state parameter. The switching time is influenced by the input overdrive above this steady-state
threshold up to a differential input voltage magnitude of 100 mV.
Figure 36. SN65LVDS100 Simulated Input Voltage Threshold vs
Common-Mode Input Voltage, Supply Voltage, and Temperature
13
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
www.ti.com
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
APPLICATION INFORMATION
The SN65LVDS100, SN65LVDT100, SN65LVDS101, and SN65LVDT101 inputs will detect a 100-mV difference
between any two signals between 0 V and 4 V, This range will allow receipt of many different single-ended and
differential signals. Following are some of the more common connections.
VCC
SN65LVDS100
ECL
100 VEE
50 50 VCC-2 V
Figure 37. PECL-to-LVDS Translation
LVDS
SN65LVDT101
3.3 v
PECL
LVDS
50 50 Figure 38. LVDS-to-3.3 V PECL Translation
5V
ECL
SN65LVDS101
3.3 v
PECL
VEE
50 50 50 50 3V
Figure 39. 5-V PECL to 3.3-V PECL Translation
VTT
50 CML
50 SN65LVDS100 or
SN65LVDS101
Figure 40. CML-to-LVDS or 3.3-V PECL Translation
14
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
www.ti.com
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
APPLICATION INFORMATION (continued)
3.3 V
ECL
SN65LVDS100
Z0 = 50 100 50 VEE
LVDS
VBB
0.01 F
22 k
Figure 41. Single-Ended 3.3-V PECL-to-LVDS Translation
VDD
VDD/600 A*
1 V < VDD < 4 V
CMOS
SN65LVDS100
100 0.01 F
LVDS
VDD/600 A*
* closest standard value
Figure 42. Single-Ended CMOS-to-LVDS Translation
VDD
1 V < VDD < 4 V
VDD/600 A*
CMOS
SN65LVDS101
3.3 v
PECL
50 0.01 F
50 VDD/600 A*
* closest standard
value
Figure 43. Single-Ended CMOS-to-3.3-V PECL Translation
C
50 C
SN65LVDS100 or
SN65LVDS101
50 VBB
0.01 F
22 k
Figure 44. Receipt of AC-Coupled Signals
15
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
www.ti.com
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
APPLICATION INFORMATION (continued)
FAILSAFE CONSIDERATIONS
Failsafe, in regard to a line receiver, usually means that the output goes to a defined logical state with no input
signal. To keep added jitter to an absolute minimum, the SN65LVDS100 does not include this feature. It does
exhibit 25 mV of input voltage hysteresis to prevent oscillation and keep the output in the last state prior to
input-signal loss (assuming the differential noise in the system is less than the hysteresis).
Should failsafe be required, it may be added externally with a 1.6-kΩ pull-up resistor to the 3.3-V supply and a
1.6-kΩ pull-down resistor to ground as shown in Figure 45 The default output state is determined by which line is
pulled up or down and is the user's choice. The location of the 1.6-kΩ resistors is not critical. However the 100-Ω
resistor should be located at the end of the transmission line.
3.3 V
1.6 kΩ
100 Ω
1.6 kΩ
Figure 45. External Failsafe Circuit
Addition of this external failsafe will reduce the differential noise margin and add jitter to the output signal. The
roughly 100-mV steady-state voltage generated across the 100-Ω resistor adds (or subtracts) from the signal
generated by the upstream line driver. If the line driver's differential output is symmetrical about zero volts, then
the input at the receiver will appear asymmetrical with the external failsafe. Perhaps more important, is the extra
time it takes for the input signal to overcome the added failsafe offset voltage.
In Figure 46 and using an external failsafe, the high-level differential voltage at the input of the SN65LVDS100
reaches 340 mV and the low-level –400 mV indicating a 60-mV differential offset induced by the external failsafe
circuitry. The figure also reveals that the lowest peak-to-peak time jitter does not occur at zero-volt differential
(the nominal input threshold of the receiver) but at –60 mV, the failsafe offset.
The added jitter from external failsafe increases as the signal transition times are slowed by cable effects. When
a ten-meter CAT-5 UTP cable is introduced between the driver and receiver, the zero-crossing peak-to-peak jitter
at the receiver output adds 250 ps when the external failsafe is added with this specific test set up. If external
failsafe is used in conjunction with the SN65LVDS100, the noise margin and jitter effects should be budgeted.
16
www.ti.com
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
SLLS516C – AUGUST 2002 – REVISED JUNE 2004
Figure 46. Receiver Input Eye Pattern With External Failsafe
17
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