Typical Size
6,4 mm X 9,7 mm
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SLVS523− OCTOBER 2004
FEATURES
D Low Voltage Separate Power Bus
D 15-mΩ MOSFET Switches for High Efficiency
DESCRIPTION
As a member of the SWIFT family of dc/dc regulators,
the SN0401093 low-input voltage high-output current
synchronous buck PWM converter integrates all
required active components. Included on the substrate
with the listed features are a true, high performance,
voltage error amplifier that enables maximum
performance under transient conditions and flexibility in
choosing the output filter L and C components; an
under-voltage-lockout circuit to prevent start-up until
the VIN input voltage reaches 3 V; an internally and
externally set slow-start circuit to limit in-rush currents;
and a power good output useful for processor/logic
reset, fault signaling, and supply sequencing.
at 9-A Continuous Output
D Adjustable Output Voltage
D Externally Compensated With 1% Internal
Reference Accuracy
D Fast Transient Response
D Wide PWM Frequency:
D
D
Adjustable 280 kHz to 700 kHz
Load Protected at Thermal Shutdown
Integrated Solution Reduces Board Area and
Total Cost
APPLICATIONS
D Low-Voltage, High-Density Systems With
D
D
The SN0401093 is available in a thermally enhanced
28-pin TSSOP (PWP) PowerPAD package, which
eliminates bulky heatsinks.
Power Distribution at 1.0 V
Point of Load Regulation for High
Performance DSPs, FPGAs, ASICs and
Microprocessors
Broadband, Networking and Optical
Communications Infrastructure
SIMPLIFIED SCHEMATIC
EFFICIENCY
vs
OUTPUT CURRENT
SIMPLIFIED SCHEMATIC
100
Input2
PVIN
PH
SN0401093
BOOT
PGND
3.3 V
VIN
Output
95
90
85
Efficiency − %
Input1
COMP
VBIAS
AGND VSENSE
80
75
70
65
Compensation
Network
VIN = 3.3 V,
PVIN = 2.5 V,
VO = 1.8 V,
fs= 700 kHz
60
55
50
0
1
2
3
4
5
6
7
8
9
10
IO − Output Current − A
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD and SWIFT are trademarks of Texas Instruments.
!"#$%&'#! ()$$*!' & #" +),-(&'#! .&'*/ $#.)('
(#!"#$% '# +*("(&'#! +*$ '0* '*$% #" *1& !'$)%*!' '&!.&$. 2&$$&!'3/
$#.)('#! +$#(*!4 .#* !#' !*(*&$-3 !(-).* '*'!4 #" &-- +&$&%*'*$/
Copyright 2004, Texas Instruments Incorporated
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SLVS523− OCTOBER 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA
−40°C to 85°C
OUTPUT VOLTAGE
Adjustable down to 0.9 V
PACKAGE
Plastic HTSSOP (PWP)(1)
PART NUMBER
SN0401093PWP
(1) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., SN0401093PWPR). See the application section of
the data sheet for PowerPAD drawing and layout information.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
SN0401093
Input voltage range, VI
Output voltage range, VO
SS/ENA
−0.3 to 7
RT
−0.3 to 6
VSENSE
−0.3 to 4
PVIN, VIN
−0.3 to 4.5
BOOT
−0.3 to 10
VBIAS, COMP, PWRGD
−0.3 to 7
PH
−0.6 to 6
PH
Source current, IO
Sink current, IS
UNIT
V
V
Internally limited
COMP, VBIAS
6
mA
PH
16
A
COMP
6
SS/ENA, PWRGD
10
mA
±0.3
V
Operating virtual junction temperature range, TJ
−40 to 125
°C
Storage temperature, Tstg
−65 to 150
°C
Voltage differential
AGND to PGND
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
300
°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
UNIT
3
4
V
1.6
4.0
V
−40
125
°C
Input voltage, VIN, VI
Power input voltage, PVIN
Operating junction temperature, TJ
NOM
DISSIPATION RATINGS(1)(2)
PACKAGE
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
TA = 25°C
POWER RATING
TA = 70°C
POWER RATING
28 Pin PWP with solder
18.8°C/W
5.32 W
2.93 W
(1) For more information on the PWP package, refer to TI technical brief, literature number SLMA002.
(2) Test board conditions:
1. 3” x 3”, 4 layers, thickness: 0.062”
2. 2.0 oz. copper traces and ground area located on the top of the PCB
3. 2.0 oz. copper ground area with VOUT fill area and two signal traces on the bottom layer of the PCB
4. 2.0 oz. copper ground planes on the 2 internal layers
5. 12 thermal vias (see “Recommended Land Pattern” in applications section of this data sheet)
2
TA = 85°C
POWER RATING
2.13 W
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SLVS523− OCTOBER 2004
ELECTRICAL CHARACTERISTICS
TJ = –40°C to 125°C, VIN = 3 V to 4 V, PVIN = 1.6 V to 4.0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE, VIN
Input voltage range, VIN
Supply voltage range, PVIN
Output = 1.2 V
3.0
4.0
V
1.6
4.0
V
fs = 350 kHz, RT open, PH pin open,
PVIN = 1.8 V
VIN
I(Q)
Quiescent current
PVIN
6.3
10.0
1
1.4
4.0
7.0
mA
SHUTDOWN, SS/ENA = 0 V,
PVIN = 1.8 V
fs = 350 kHz, RT open, PH pin open,
VIN = 3.3 V
t100
SHUTDOWN, SS/ENA = 0 V, VIN = 3.3 V
mA
µA
UNDER VOLTAGE LOCK OUT (VIN)
Start threshold voltage, UVLO
2.95
Stop threshold voltage, UVLO
2.70
Hysteresis voltage, UVLO
Rising and falling edge deglitch, UVLO(1)
3.0
2.80
V
V
0.12
V
2.5
µs
BIAS VOLTAGE
Output voltage, VBIAS
I(VBIAS) = 0
2.70
2.80
Output current, VBIAS (2)
2.90
V
100
µA
CUMULATIVE REFERENCE
Vref
Accuracy
REGULATION
Line regulation(1)
Load regulation(1)
0.882
0.891
IL = 4.5 A, fs = 350 kHz, TJ = 85°C
IL = 0 A to 9 A, fs = 350 kHz, TJ = 85°C
0.900
V
0.07
%/V
0.03
%/A
kHz
OSCILLATOR
Internally set—free running frequency
Externally set—free running frequency range
RT open(1)
280
350
420
RT = 180 kΩ (1% resistor to AGND)(1)
252
280
308
RT = 100 kΩ (1% resistor to AGND)
RT = 68 kΩ (1% resistor to AGND)(1)
460
500
540
663
700
762
Ramp valley(1)
0.75
Ramp amplitude (peak-to-peak)(1)
Minimum controllable on time(1)
Maximum duty cycle(1)
kHz
V
1
V
200
ns
90%
(1) Specified by design
(2) Static resistive loads only
3
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SLVS523− OCTOBER 2004
ELECTRICAL CHARACTERISTICS (continued)
TJ = –40°C to 125°C, VIN = 3 V to 4 V, PVIN = 1.6 V to 4.0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ERROR AMPLIFIER
Error amplifier open loop voltage gain
1 kΩ COMP to AGND(1)
90
110
Error amplifier unity gain bandwidth
Parallel 10 kΩ, 160 pF COMP to AGND(1)
3
5
Error amplifier common mode input voltage
range
Powered by internal LDO(1)
0
Input bias current, VSENSE
VSENSE = Vref
Output voltage slew rate (symmetric), COMP
VBIAS
60
1.0
dB
MHz
250
1.4
V
nA
V/µs
PWM COMPARATOR
PWM comparator propagation delay time,
PWM comparator input to PH pin
(excluding deadtime)
10-mV overdrive(1)
70
85
ns
1.2
1.4
V
SLOW-START/ENABLE
Enable threshold voltage, SS/ENA
0.82
Enable hysteresis voltage, SS/ENA(1)
Falling edge deglitch, SS/ENA(1)
Internal slow-start time
0.03
V
2.5
µs
2.6
3.35
4.1
Charge current, SS/ENA
SS/ENA = 0 V
2
5
8
ms
µA
Discharge current, SS/ENA
SS/ENA = 0.2 V, VIN = 2.7 V
1
2
4
mA
POWER GOOD
Power good threshold voltage
VSENSE falling
90
Power good hysteresis voltage(1)
Power good falling edge deglitch(1)
Output saturation voltage, PWRGD
Leakage current, PWRGD
%Vref
%Vref
3
µs
35
I(sink) = 2.5 mA
VIN = 3.3 V
0.18
0.3
V
1
µA
THERMAL SHUTDOWN
Thermal shutdown trip point(1)
Thermal shutdown hysteresis(1)
135
165
°C
10
°C
OUTPUT POWER MOSFETS
rDS(on)
Power MOSFET switches
(1) Specified by design
(2) Static resistive loads only
4
VIN = 3 V
15
30
VIN = 3.6 V
14
28
mΩ
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SLVS523− OCTOBER 2004
PWP PACKAGE
(TOP VIEW)
AGND
VSENSE
COMP
PWRGD
BOOT
PH
PH
PH
PH
PH
PH
PH
PH
PH
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
THERMAL 22
PAD
21
20
19
18
17
16
15
RT
VIN
SS/ENA
VBIAS
PVIN
PVIN
PVIN
PVIN
PVIN
PGND
PGND
PGND
PGND
PGND
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
DESCRIPTION
AGND
1
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, and RT resistor.
Connect PowerPAD to AGND.
BOOT
5
Bootstrap output. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the
high-side FET driver.
COMP
3
Error amplifier output. Connect frequency compensation network from COMP to VSENSE
PGND
15−19
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas
to the input and output supply returns, and negative terminals of the input and output capacitors. A single point connection
to AGND is recommended.
PH
6−14
Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
PVIN
20−24
Input supply for the power MOSFET switches. Bypass PVIN pins to PGND pins close to device package with a
high-quality, low-ESR 10-µF ceramic capacitor.
PWRGD
4
Power good open drain output. High when VSENSE ≥ 90% Vref, otherwise PWRGD is low. Note that output is low when
SS/ENA is low or the internal shutdown signal is active.
RT
28
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs.
SS/ENA
26
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and
capacitor input to externally set the start-up time.
VBIAS
25
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a
high-quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor.
VIN
27
Input supply for the internal bias regulator. An external capacitor of 1 µF to be connected to the VIN pin.
VSENSE
2
Error amplifier inverting input. Connect to output voltage compensation network/output divider.
5
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SLVS523− OCTOBER 2004
INTERNAL BLOCK DIAGRAM
VBIAS
AGND
VIN
SS/ENA
Falling
Edge
Deglitch
1.2 V
REG
VBIAS
Enable
Comparator
Hysteresis: 0.03 V
2.5 µs
VIN UVLO
Comparator
VIN
2.95 V
Hysteresis: 0.16 V
VIN
SHUTDOWN
PVIN
Thermal
Shutdown
150°C
Falling
and
Rising
Edge
Deglitch
BOOT
2.5 µs
SS_DIS
SHUTDOWN
Internal/External
Slow-start
(Internal Slow-start Time = 3.35 ms
PH
+
−
R Q
Error
Amplifier
Reference
VREF = 0.891 V
S
PWM
Comparator
LOUT
CO
Adaptive Dead-Time
and
Control Logic
VIN
OSC
PGND
Powergood
Comparator
PWRGD
VSENSE
Falling
Edge
Deglitch
0.90 Vref
Hysteresis: 0.03 Vref
VSENSE
6
COMP
RT
SHUTDOWN
35 µs
VO
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SLVS523− OCTOBER 2004
TYPICAL CHARACTERISTICS
DRAIN-SOURCE
ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
VIN = 3.0 V
PVIN = 2.5 V
IO = 9 A
20
15
10
5
0
−40
0
25
85
TJ − Junction Temperature − °C
25
VIN = 3.6 V
PVIN = 2.5 V
IO = 9 A
20
15
10
5
0
−40
125
0
85
125
650
550
450
350
250
−40
0
4
VI = 3.3 V
TA = 25°C
3.5
600
500
RT = 100 kΩ
400
300
0.893
Device Power Losses − W
V ref − Voltage Reference − V
RT = 68 kΩ
125
DEVICE POWER LOSSES
vs
LOAD CURRENT
0.895
700
85
Figure 3
VOLTAGE REFERENCE
vs
JUNCTION TEMPERATURE
800
25
TJ − Junction Temperature − °C
Figure 2
EXTERNALLY SET
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
0.891
0.889
0.887
3
2.5
2
1.5
1
0.5
RT = 180 kΩ
0.885
0
25
85
125
0
−40
TJ − Junction Temperature − °C
0
25
85
TJ − Junction Temperature − °C
Figure 4
RL = 10 kΩ,
CL = 160 pF,
TA = 25°C
120
0.893
100
Gain − dB
0.891
0.889
Phase
−40
−80
−120
40
Gain
20
0.887
−140
−160
0
0.885
−180
−20
Figure 7
3.5
3.6
1
10
100
−200
1 k 10 k 100 k 1 M 10 M
f − Frequency − Hz
Figure 8
10
12
3.80
VIN = 3.3 V,
PVIN = 2.5 V
−20
−100
60
8
INTERNAL SLOW-START TIME
vs
JUNCTION TEMPERATURE
−60
80
6
Figure 6
0
140
PVIN = 2.5 V
3.2
3.3
3.4
VI − Input Voltage − V
4
IL − Load Current − A
ERROR AMPLIFIER
OPEN LOOP RESPONSE
0.895
3.1
2
Figure 5
REFERENCE VOLTAGE
vs
INPUT VOLTAGE
3
0
125
Phase − Degrees
200
−40
Internal Slow-Start Time − ms
f − Externally Set Oscillator Frequency − kHz
25
750
TJ − Junction Temperature − °C
Figure 1
VO − Output Voltage Regulation − V
INTERNALLY SET
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
f − Internally Set Oscillator Frequency − kHz
25
Drain Source On-State Reststance − m Ω
Drain Source On-State Reststance − m Ω
DRAIN-SOURCE
ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
3.65
3.50
3.35
3.20
3.05
2.90
2.75
−40
0
25
85
125
TJ − Junction Temperature − °C
Figure 9
7
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SLVS523− OCTOBER 2004
proportional to the slow-start capacitor. The
slow-start time set by the capacitor is
approximately:
DETAILED DESCRIPTION
UNDERVOLTAGE LOCK OUT (UVLO)
The SN0401093 incorporates an under voltage
lockout circuit to keep the device disabled when
the input voltage (VIN) is insufficient. During
power up, internal circuits are held inactive until
VIN exceeds the nominal UVLO threshold voltage
of 2.95 V. Once the UVLO start threshold is
reached, device start-up begins. The device
operates until VIN falls below the nominal UVLO
stop threshold of 2.8 V. Hysteresis in the UVLO
comparator, and a 2.5-µs rising and falling edge
deglitch circuit reduce the likelihood of shutting
the device down due to noise on VIN. UVLO with
respect to VIN and not PVIN, see application note.
SLOW-START/ENABLE (SS/ENA)
The slow-start/enable pin provides two functions.
First, the pin acts as an enable (shutdown) control
by keeping the device turned off until the voltage
exceeds the start threshold voltage of
approximately 1.2 V. When SS/ENA exceeds the
enable threshold, device start-up begins. The
reference voltage fed to the error amplifier is
linearly ramped up from 0 V to 0.891 V in 3.35 ms.
Similarly, the converter output voltage reaches
regulation in approximately 3.35 ms. Voltage
hysteresis and a 2.5-µs falling edge deglitch
circuit reduce the likelihood of triggering the
enable due to noise.
The second function of the SS/ENA pin provides
an external means of extending the slow-start
time with a low-value capacitor connected
between SS/ENA and AGND.
Adding a capacitor to the SS/ENA pin has two
effects on start-up. First, a delay occurs between
release of the SS/ENA pin and start-up of the
output. The delay is proportional to the slow-start
capacitor value and lasts until the SS/ENA pin
reaches the enable threshold. The start-up delay
is approximately:
t +C
d
(SS)
1.2 V
5 mA
(1)
Second, as the output becomes active, a brief
ramp-up at the internal slow-start rate may be
observed before the externally set slow-start rate
takes control and the output rises at a rate
8
t
(SS)
+C
(SS)
0.7 V
5 mA
(2)
The actual slow-start time is likely to be less than
the above approximation due to the brief ramp-up
at the internal rate.
VBIAS REGULATOR (VBIAS)
The VBIAS regulator provides internal analog and
digital blocks with a stable supply voltage over
variations in junction temperature and input
voltage. A high quality, low-ESR, ceramic bypass
capacitor is required on the VBIAS pin. X7R or
X5R grade dielectrics are recommended because
their values are more stable over temperature.
The bypass capacitor must be placed close to the
VBIAS pin and returned to AGND.
External loading on VBIAS is allowed, with the
caution that internal circuits require a minimum
VBIAS of 2.70 V, and external loads on VBIAS
with ac or digital switching noise may degrade
performance. The VBIAS pin may be useful as a
reference voltage for external circuits. VBIAS is
derived from the VIN pin, see the internal block
diagram on page 6.
VOLTAGE REFERENCE
The voltage reference system produces a precise
Vref signal by scaling the output of a temperature
stable bandgap circuit. During manufacture, the
bandgap and scaling circuits are trimmed to
produce 0.891 V at the output of the error
amplifier, with the amplifier connected as a
voltage follower. The trim procedure adds to the
high precision regulation of the SN0401093, since
it cancels offset errors in the scale and error
amplifier circuits.
OSCILLATOR AND PWM RAMP
The oscillator frequency is set to an internally fixed
value of 350 kHz. The oscillator frequency can be
externally adjusted from 280 to 700 kHz by
connecting a resistor between the RT pin to
ground. The switching frequency is approximated
by the following equation, where R is the
resistance from RT to AGND:
(3)
Switching Frequency + 100 kW 500 [kHz]
R
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SLVS523− OCTOBER 2004
ERROR AMPLIFIER
The high performance, wide bandwidth, voltage
error amplifier sets the SN0401093 apart from most
dc/dc converters. The user is given the flexibility to
use a wide range of output L and C filter components
to suit the particular application needs. Type-2 or
Type-3 compensation can be employed using
external compensation components.
PWM CONTROL
Signals from the error amplifier output, oscillator, and
current limit circuit are processed by the PWM
control logic. Referring to the internal block diagram,
the control logic includes the PWM comparator, OR
gate, PWM latch, and portions of the adaptive
dead-time and control-logic block. During
steady-state operation below the current limit
threshold, the PWM comparator output and
oscillator pulse train alternately reset and set the
PWM latch. Once the PWM latch is set, the low-side
FET remains on for a minimum duration set by the
oscillator pulse width. During this period, the PWM
ramp discharges rapidly to its valley voltage. When
the ramp begins to charge back up, the low-side FET
turns off and high-side FET turns on. As the PWM
ramp voltage exceeds the error amplifier output
voltage, the PWM comparator resets the latch, thus
turning off the high-side FET and turning on the
low-side FET. The low-side FET remains on until the
next oscillator pulse discharges the PWM ramp.
During transient conditions, the error amplifier output
could be below the PWM ramp valley voltage or
above the PWM peak voltage. If the error amplifier
is high, the PWM latch is never reset, and the
high-side FET remains on until the oscillator pulse
signals the control logic to turn the high-side FET off
and the low-side FET on. The device operates at its
maximum duty cycle until the output voltage rises to
the regulation set-point, setting VSENSE to
approximately the same voltage as VREF. If the error
amplifier output is low, the PWM latch is continually
reset and the high-side FET does not turn on. The
low-side FET remains on until the VSENSE voltage
decreases to a range that allows the PWM
comparator to change states. The SN0401093 is
capable of sinking current continuously until the
output reaches the regulation set-point.
If the current limit comparator trips for longer than
100 ns, the PWM latch resets before the PWM ramp
exceeds the error amplifier output. The high-side
FET turns off and low-side FET turns on to decrease
the energy in the output inductor and consequently
the output current. This process is repeated each
cycle in which the current limit comparator is tripped.
DEAD-TIME CONTROL AND MOSFET
DRIVERS
Adaptive dead-time control prevents shoot-through
current from flowing in both N-channel power
MOSFETs
during the switching transitions by actively
controlling the turnon times of the MOSFET drivers.
The high-side driver does not turn on until the voltage
at the gate of the low-side FET is below 2 V. While
the low-side driver does not turn on until the voltage
at the gate of the high-side MOSFET is below 2 V.
The high-side and low-side drivers are designed with
300-mA source and sink capability to quickly drive
the power MOSFETs gates. The low-side driver is
supplied from VIN, while the high-side drive is
supplied from the BOOT pin. A bootstrap circuit uses
an external BOOT capacitor and an internal 2.5-Ω
bootstrap switch connected between the VIN and
BOOT pins. The integrated bootstrap switch
improves drive efficiency and reduces external
component count.
THERMAL SHUTDOWN
The device uses the thermal shutdown to turn off the
power MOSFETs and disable the controller if the
junction temperature exceeds 150°C. The device is
released from shutdown automatically when the
junction temperature decreases to 10°C below the
thermal shutdown trip point, and starts up under
control of the slow-start circuit.
Thermal shutdown provides protection when an
overload condition is sustained for several
milliseconds. With a persistent fault condition, the
device cycles continuously; starting up by control of
the slow-start circuit, heating up due to the fault
condition, and then shutting down upon reaching the
thermal shutdown trip point. This sequence repeats
until the fault condition is removed.
POWER-GOOD (PWRGD)
The power good circuit monitors for under voltage
conditions on VSENSE. If the voltage on VSENSE
is 10% below the reference voltage, the open-drain
PWRGD output is pulled low. PWRGD is also pulled
low if VIN is less than the UVLO threshold or
SS/ENA is low. When VIN ≥ UVLO threshold,
SS/ENA ≥ enable threshold, and VSENSE > 90% of
Vref, the open drain output of the PWRGD pin is high.
A hysteresis voltage equal to 3% of Vref and a 35 µs
falling edge deglitch circuit prevent tripping of the
power good comparator due to high frequency noise.
9
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SLVS523− OCTOBER 2004
THERMAL PAD MECHANICAL DATA
PWP (R−PDSO−G28)
PowerPADt PLASTIC SMALL−OUTLINE
PPTD032
10
PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN0401093PWP
PREVIEW
HTSSOP
PWP
28
None
CU NIPDAU
Level-1-220C-UNLIM
SN0401093PWPR
PREVIEW
HTSSOP
PWP
28
None
CU NIPDAU
Level-1-220C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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