SN74BCT29843 9-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCBS022C – FEBRUARY 1989 – REVISED NOVEMBER 1993 • • • DW OR NT PACKAGE (TOP VIEW) BiCMOS Process With CMOS Inputs and TTL Outputs Substantially Reduces Standby Current Input Has 50 kΩ Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic 300-mil DIPs (NT) OE 1D 2D 3D 4D 5D 6D 7D 8D 9D CLR GND description The SN74BCT29843 features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q PRE LE The nine latches are transparent D-type latches. When the latch-enable (LE) input is high, the Q outputs are complementary to the noninverting data (D) inputs. A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high or low level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pull-up components. The output enable (OE) does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN74BCT29843 is characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS PRE CLR OE LE D OUTPUT Q H L X L X X H L L X X L H H L H L L H H L H H H H H L L X Q0 X X H X X Z Copyright 1993, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–1 SN74BCT29843 9-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCBS022C – FEBRUARY 1989 – REVISED NOVEMBER 1993 logic symbol† OE PRE CLR LE 1D 2D 3D 4D 5D 6D 7D 8D 9D 1 14 11 13 2 logic diagram (positive logic) EN OE S2 PRE R CLR C1 1D 23 2 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 LE 1 14 11 13 1Q S 2Q 3Q 1D 23 C1 2 1Q 1D 4Q R 5Q 6Q 7Q 8Q 9Q To Eight Other Channels † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Voltage range applied to any output in the disabled or power-off state, VO . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Voltage range applied to any output in the high state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30 mA Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the “recommended operating conditions” section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. recommended operating conditions MIN NOM MAX 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IIK Low-level input voltage 0.8 V Input clamp current –18 mA IOH IOL High-level output current – 24 mA 48 mA TA Operating free-air temperature 70 °C 2–2 High-level input voltage 2 Low-level output current 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V V SN74BCT29843 9-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCBS022C – FEBRUARY 1989 – REVISED NOVEMBER 1993 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VCC = 4.5 V, VOH VCC = 4 4.5 5V VOL II VCC = 4.5 V, VCC = 5.5 V, IIH IIL VCC = 5.5 V, VCC = 5.5 V, IOS‡ ICCL VCC = 5.5 V, VCC = 5.5 V, ICCH ICCZ VCC = 5.5 V, VCC = 5.5 V, MIN II = –18 mA IOH = – 15 mA 2.4 IOH = – 24 mA IOL = 48 mA TYP† MAX UNIT –1.2 V 3.2 V 2 0.35 VI = 7 V VI = 2.7 V –10 VI = 0.4 V VO = 0 –75 0.55 V 0.1 mA –75 µA – 0.2 mA – 275 mA Outputs open 24 35 mA Outputs open 3 7 mA Outputs open 3 7 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) MIN tw Pulse duration tsu Setup time, time data before LE↓ th Hold time, data after LE↓ PRE low 7 CLR low 5 LE high 4 High or low MAX ns 1.5 PRE or CLR inactive ns 2 High or low UNIT 3.5 ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Note 2) FROM (INPUT) TO (OUTPUT) tPLH tPHL D Q tPLH tPHL LE Q tPLH tPHL PRE Q tPLH tPHL CLR Q tPZH tPZL OE Q tPHZ tPLZ OE Q PARAMETER VCC = 5 V, TA = 25°C MIN MAX 7 1.5 8 5.7 8 1.5 9 1.5 6 8 1.5 10 1.5 6 8 1.5 10 1.5 6 8 1.5 12 1.5 6 10 1.5 12 1.5 6 10 1.5 12 1.5 6 10 1.5 12 2 10 13 2 15 2 10 13 2 15 2 5 7 2 8 2 5 7 2 8 MIN TYP MAX 1.5 4.5 1.5 UNIT ns ns ns ns ns ns NOTE 2: Load circuits and voltage waveforms are shown in Section 1. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–3 SN74BCT29843 9-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCBS022C – FEBRUARY 1989 – REVISED NOVEMBER 1993 2–4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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