TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M HIGH-PERFORMANCE IMPACT PAL CIRCUITS SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996 D D D D TIBPAL16L8’ J OR W PACKAGE High-Performance Operation: Propagation Delay . . . 15 ns Max Power-Up Clear on Registered Devices (All Register Outputs are Set High, but Voltage Levels at the Output Pins Go Low) Package Options Include Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Ceramic (J) 300-mil DIPs Dependable Texas Instruments Quality and Reliability I INPUTS 3-STATE O OUTPUTS REGISTERED Q OUTPUTS I/O PORTS PAL16L8 10 2 0 6 PAL16R4 8 0 4 (3-state buffers) 4 PAL16R6 8 0 6 (3-state buffers) 2 PAL16R8 8 0 8 (3-state buffers) 0 DEVICE (TOP VIEW) I I I I I I I I I GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC O I/O I/O I/O I/O I/O I/O O I TIBPAL16L8’ FK PACKAGE (TOP VIEW) I I I VCC O description These programmable array logic devices feature high speed and functional equivalency when compared with currently available devices. These IMPACT-X circuits combine the latest Advanced Low-Power Schottky technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes for conventional TTL logic. Their easy programmability allows for quick design of custom functions and typically results in a more compact circuit board. In addition, chip carriers are available for futher reduction in board space. 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 I/O I/O I/O I/O I/O I GND I O I/O I I I I I Pin assignments in operating mode The TIBPAL16’ M series is characterized for operation over the full military temperature range of –55°C to 125°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. IMPACT is a trademark of Texas Instruments Incorporated. PAL is a registered trademark of Advanced Micro Devices Inc. Copyright 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M HIGH-PERFORMANCE IMPACT PAL CIRCUITS SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996 TIBPAL16R4’ J OR W PACKAGE TIBPAL16R4’ FK PACKAGE 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC I/O I/O Q Q Q Q I/O I/O OE I I I I I 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 TIBPAL16R6’ FK PACKAGE TIBPAL16R6’ J OR W PACKAGE 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC I/O Q Q Q Q Q Q I/O OE I I I I I 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 I GND 1 (TOP VIEW) I I CLK VCC I/O (TOP VIEW) CLK I I I I I I I I GND TIBPAL16R8’ J OR W PACKAGE 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 I I CLK VCC Q 20 2 (TOP VIEW) VCC Q Q Q Q Q Q Q Q OE I I I I I Pin assignments in operating mode 2 POST OFFICE BOX 655303 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 I GND 1 Q Q Q Q Q TIBPAL16R8’ FK PACKAGE (TOP VIEW) CLK I I I I I I I I GND I/O Q Q Q Q OE I/O I/O 19 OE I/O Q 20 2 • DALLAS, TEXAS 75265 OE Q Q 1 I GND CLK I I I I I I I I GND (TOP VIEW) I I CLK VCC I/O (TOP VIEW) Q Q Q Q Q TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M HIGH-PERFORMANCE IMPACT PAL CIRCUITS SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996 functional block diagrams (positive logic) TIBPAL16L8’ & 32 X 64 16 x I 10 16 6 16 EN ≥ 1 7 O 7 O 7 I/O 7 I/O 7 I/O 7 I/O 7 I/O 7 I/O 6 TIBPAL16R4’ OE CLK EN 2 C1 & 32 X 64 16 x I 8 ≥1 8 I=1 2 1D Q 8 Q 8 Q 8 Q 16 4 4 16 EN ≥ 1 7 I/O 7 I/O 7 I/O 7 I/O 4 4 denotes fused inputs POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M HIGH-PERFORMANCE IMPACT PAL CIRCUITS SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996 functional block diagrams (positive logic) TIBPAL16R6’ OE CLK EN 2 C1 & 32 X 64 16 x I 8 ≥1 8 I=1 2 Q 1D 8 Q 8 Q 8 Q 8 Q 8 Q 16 6 2 16 EN ≥ 1 7 I/O I/O 7 2 6 TIBPAL16R8’ OE CLK EN 2 C1 & 32 X 64 16 x I 8 8 ≥1 I=1 2 8 Q 8 Q 8 Q 8 Q 8 Q 8 Q 8 Q 16 8 16 8 denotes fused inputs 4 Q 1D POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M HIGH-PERFORMANCE IMPACT PAL CIRCUITS SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996 TIBPAL16L8-15M logic diagram (positive logic) I 1 Increment First Fuse Numbers I I I I I I I I 2 3 4 5 6 7 8 9 0 4 8 12 16 20 24 28 0 32 64 96 128 160 192 224 31 19 256 288 320 352 384 416 448 480 18 512 544 576 608 640 672 704 736 17 768 800 832 864 896 928 960 992 16 1024 1056 1088 1120 1152 1184 1216 1248 15 1280 1312 1344 1376 1408 1440 1472 1504 14 1536 1568 1600 1632 1664 1696 1728 1760 13 1792 1824 1856 1888 1920 1952 1984 2016 12 11 O I/O I/O I/O I/O I/O I/O O I Fuse number = First fuse number + Increment POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M HIGH-PERFORMANCE IMPACT PAL CIRCUITS SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996 TIBPAL16R4-15M logic diagram (positive logic) CLK 1 Increment First Fuse Numbers I I I I I I I I 2 3 4 5 6 7 8 9 0 4 8 12 16 20 24 28 19 256 288 320 352 384 416 448 480 18 512 544 576 608 640 672 704 736 I=1 1D 768 800 832 864 896 928 960 992 I=1 1D 1024 1056 1088 1120 1152 1184 1216 1248 I=1 1D 1280 1312 1344 1376 1408 1440 1472 1504 I=1 1D 17 I/O I/O Q C1 16 Q C1 15 Q C1 14 Q C1 1536 1568 1600 1632 1664 1696 1728 1760 13 1792 1824 1856 1888 1920 1952 1984 2016 12 11 Fuse number = First fuse number + Increment 6 31 0 32 64 96 128 160 192 224 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 I/O I/O OE TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M HIGH-PERFORMANCE IMPACT PAL CIRCUITS SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996 TIBPAL16R6-15M logic diagram (positive logic) CLK 1 Increment First Fuse Numbers I I I I I I I I 2 3 4 5 6 7 8 9 0 4 8 12 16 20 24 28 31 0 32 64 96 128 160 192 224 19 256 288 320 352 384 416 448 480 I=1 1D 512 544 576 608 640 672 704 736 I=1 1D 768 800 832 864 896 928 960 992 I=1 1D 1024 1056 1088 1120 1152 1184 1216 1248 I=1 1D 1280 1312 1344 1376 1408 1440 1472 1504 I=1 1D 1536 1568 1600 1632 1664 1696 1728 1760 I=1 1D 18 I/O Q C1 17 Q C1 16 Q C1 15 Q C1 14 Q C1 13 Q C1 1792 1824 1856 1888 1920 1952 1984 2016 12 11 I/O OE Fuse number = First fuse number + Increment POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M HIGH-PERFORMANCE IMPACT PAL CIRCUITS SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996 TIBPAL16R8-15M logic diagram (positive logic) CLK 1 Increment First Fuse Numbers I I I I I I I I 2 3 4 5 6 7 8 9 0 4 8 12 16 20 24 31 I=1 1D 256 288 320 352 384 416 448 480 I=1 1D 512 544 576 608 640 672 704 736 I=1 1D 768 800 832 864 896 928 960 992 I=1 1D 1024 1056 1088 1120 1152 1184 1216 1248 I=1 1D 1280 1312 1344 1376 1408 1440 1472 1504 I=1 1D 1536 1568 1600 1632 1664 1696 1728 1760 I=1 1D 1792 1824 1856 1888 1920 1952 1984 2016 I=1 1D 19 Q C1 18 Q C1 17 Q C1 16 Q C1 15 Q C1 14 Q C1 13 Q C1 12 Q C1 11 Fuse number = First fuse number + Increment 8 28 0 32 64 96 128 160 192 224 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 OE TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M HIGH-PERFORMANCE IMPACT PAL CIRCUITS SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: These ratings apply except for programming pins during a programming cycle. recommended operating conditions MIN NOM MAX UNIT 4.5 5 5.5 V 5.5 V VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 V High-level output current –2 mA IOL fclock Low-level output current 12 mA 50 MHz High-level input voltage 2 Clock frequency 0 tw duration clock (see Note 2) Pulse duration, tsu th Setup time, input or feedback before clock↑ TA Operating free-air temperature High 9 Low 10 ns 15 Hold time, input or feedback after clock↑ ns 0 – 55 ns 25 125 °C NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency, fclock. The minimum pulse durations specified are only for clock high or low, but not for both simultaneously. electrical characteristics over recommended operating free-air temperature range PARAMETER TEST CONDITIONS VIK VOH VCC = 4.5 V, VCC = 4.5 V, II = – 18 mA IOH = – 2 mA VOL VCC = 4.5 V, IOL = 12 mA VCC = 5 5.5 5V V, VO = 2 2.7 7V 5V VCC = 5 5.5 V, 4V VO = 0 0.4 VCC = 5 5.5 5V V, VI = 5 5.5 5V VCC = 5.5 V, VI = 2.7 V VCC = 5.5 V, VCC = 5.5 V, VI = 0.4 V VO = 0.5 V IOZH IOZL II Outputs I/O ports Outputs I/O ports Pin 1, 11 All others TIBPAL16R4-15M TYP‡ MAX MIN – 1.5 2.4 I/O ports 20 – 20 – 250 0.2 0.1 V µA µA mA 50 100 All others IIL IOS§ V V 0.5 100 Pin 1, 11 IIH 3.3 0.35 UNIT µA 25 – 30 – 0.25 mA – 250 mA ICC VCC = 5.5 V, VI = 0, Outputs open 170 220 mA ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second. Set VO at 0.5 V to avoid test equipment degradation. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M HIGH-PERFORMANCE IMPACT PAL CIRCUITS SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996 electrical characteristics over recommended operating free-air temperature range TIBPAL16L8-15M PARAMETER TEST CONDITIONS VIK VOH VCC = 4.5 V, VCC = 4.5 V, II = – 18 mA IOH = – 2 mA VOL VCC = 4.5 V, IOL = 12 mA 5V VCC = 5 5.5 V, 27V VO = 2.7 VCC = 5 5.5 5V V, VO = 0.4 04V VCC = 5 5.5 5V V, VI = 5 5.5 5V VCC = 5.5 V, VI = 2.7 V IOZH IOZL II Outputs I/O ports Outputs I/O ports Pin 1, 11 All others TIBPAL16R6-15M TIBPAL16R8-15M MIN TYP† MAX – 1.5 2.4 3.3 0.35 I/O ports 20 – 20 – 250 0.2 0.1 IIL All others V µA µA mA 50 100 All others I/O ports V V 0.5 100 Pin 1, 11 IIH UNIT µA 20 VCC = 5 5.5 5V V, – 0.25 VI = 0 0.4 4V – 0.2 mA IOS‡ VCC = 5.5 V, VO = 0.5 V – 30 – 250 mA ICC VCC = 5.5 V, VI = 0, Outputs open 170 220 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second. Set VO at 0.5 V to avoid test equipment degradation. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) FROM (INPUT) TO (OUTPUT) I, I/O O, I/O tpd ten CLK↑ Q OE↓ Q tdis ten OE↑ Q I, I/O tdis I, I/O PARAMETER fmax§ tpd TYP† MAX 8 15 ns R1 = 390 Ω, 7 12 ns R2 = 750 Ω, 8 12 ns See Figure 1 7 12 ns O, I/O 8 15 ns O, I/O 8 15 ns TEST CONDITIONS MIN 50 UNIT MHz † All typical values are at VCC = 5 V, TA = 25°C. § Maximum operating frequency and propagation delay are specified for the basic building block. When using feedback, limits must be calculated accordingly. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M HIGH-PERFORMANCE IMPACT PAL CIRCUITS SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996 programming information Texas Instruments programmable logic devices can be programmed using widely available software and inexpensive device programmers. The TIBPAL16R4-15M with date codes prior to 9616A must be programmed according to programming algorithms/specifications corresponding to the TIBPAL16R4-12C. The TIBPAL16R4-15M with date code 9616A or newer must be programmed according to programming algorithms/specifications corresponding to the TIBPAL16R4-10C. Regardless of date code, the TIBPAL16L8-15M, TIBPAL16R6-15M, and TIBPAL16R8-15M must be programmed according to programming algorithms/specifications corresponding to the TIBPAL16L8-12C, TIBPAL16R6-12C, and TIBPAL16R8-12C, respectively. Failure to do so may damage the devices. Complete programming specifications, algorithms, and the latest information on hardware, software, and firmware are available upon request. Information on programmers capable of programming Texas Instruments programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI distributor, or by calling Texas Instruments at (214) 997-5666. Table 1. Programming Reference Table (see Note 3) DESC SMD NUMBER FAMILY/PINOUT CODE TIBPAL16L8-15MJB 5962-8515509RA 9A/17 TIBPAL16L8-15MFKB 5962-85155092A 9A/717 TIBPAL16L8-15MWB 5962-8515509SA 9A/17 TIBPAL16R4-15MJB 5962-8515512RA A1/24 TIBPAL16R4-15MFKB 5962-85155122A 0A1/724 TIBPAL16R4-15MWB 5962-8515512SA A1/24 TIBPAL16R6-15MJB 5962-8515511RA 9A/24 TIBPAL16R6-15MFKB 5962-85155112A 9A/724 TIBPAL16R6-15MWB 5962-8515511SA 9A/24 TIBPAL16R8-15MJB 5962-8515510RA 9A/24 TIBPAL16R8-15MFKB 5962-85155102A 9A/724 TIBPAL16R8-15MWB 5962-8515510SA 9A/24 DEVICE NOTE 3: Programming information for TIBPAL16R4-15M with date codes 9616A or newer. Programming information for TIBPAL16L8-15M, TIBPAL16R6-15M, and TIBPAL16R8-15M regardless of date code. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M HIGH-PERFORMANCE IMPACT PAL CIRCUITS SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996 PARAMETER MEASUREMENT INFORMATION 5V S1 R1 From Output Under Test Test Point CL (see Note A) R2 LOAD CIRCUIT FOR 3-STATE OUTPUTS 3V Timing Input 1.5 V 3V High-Level Pulse 1.5 V 1.5 V 0 0 tw th tsu 3V Data Input 1.5 V 1.5 V 0 3V Low-Level Pulse VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 1.5 V 0 VOLTAGE WAVEFORMS PULSE DURATIONS 3V 3V 1.5 V Input 1.5 V 0 tpd tpd In-Phase Output 1.5 V VOH 1.5 V VOL tpd tpd Out-of-Phase Output (see Note D) 1.5 V VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES Output Control (low-level enabling) 1.5 V 1.5 V 0 ten tdis ≈ 3.3 V 1.5 V Waveform 1 S1 Closed (see Note B) VOL + 0.5 V VOL tdis ten Waveform 2 S1 Open (see Note B) VOH 1.5 V VOH – 0.5 V ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses have the following characteristics: PRR ≤ 10 MHz, tr and tf ≤ 2 ns, duty cycle = 50%. D. When measuring propagation delay times of 3- state outputs, switch S1 is closed. E. Equivalent loads may be used for testing. Figure 1. Load Circuit and Voltage Waveforms 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated